SmartFusion 2 System-on-Chip FPGA

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2 SmartFusion 2 System-on-Chip FPGA Breakthrough in Security, Reliability and Low Power Microsemi s next-generation SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM Cortex -M3 processor, advanced security processing accelerators, DSP blocks, SRAM, envm, and industry-required high-performance communication interfaces all on a single chip. LEADERSHIP IN FPGA SECURITY State-of-the-art security enables root-of-trust applications Radically transforms the usefulness of FPGAs in security applications LEADERSHIP IN FPGA RELIABILITY Only SoC FPGA with SEU immune FPGA configuration cells and processor Reliability designed for safety critical and mission critical systems LEADERSHIP IN LOW POWER FPGAS same performance LEADERSHIP IN REAL-TIME FPGA PERFORMANCE ARM Cortex -M3 real-time microcontroller Flash*Freeze real-time power management Instant on real-time availability INDUSTRIAL DEFENSE AVIATION COMMUNICATIONS MEDICAL 2

3 When Failure Is Not An Option SECURITY Recent attacks on military, industrial, communications and aviation systems have highlighted the need for security and anti-tamper safeguards within electronic systems. Design Security SmartFusion2 includes breakthrough security capabilities that make it easy to protect classified and highly-valuable designs against tampering, cloning, overbuilding, reverse engineering and counterfeiting with state-of-the-art design protection based on non-volatile flash technology. SmartFusion2 provides the most advanced design and data security capabilities starting with a robust root-of-trust device with secure key storage Data Security capability using the SoC FPGA industry s only physically unclonable function (PUF) key enrollment and regeneration capability from Intrinsic ID. SmartFusion2 is also the only SoC FPGA protected from differential power analysis (DPA) attacks using technology from Cryptographic Research Incorporated (CRI) portfolio. Users may also leverage built-in cryptographic processing accelerators including; advanced encryption standard (AES) AES-256, secure hash algorithm (SHA) SHA-256, 384 bit elliptical curve cryptographic (ECC) engine, and a nondeterministic random bit generator (NRBG). RELIABILITY Microsemi s programmable logic solutions are used extensively in military, aviation and space applications due to their high reliability and protection against single event upset (SEU) occurrences, which can cause binary bits to change state and corrupt data and cause hardware malfunction. Industrial and medical safety markets are also requiring SEU protection as vital requirement for their applications. configuration cells DDR Bridges (MSS, MDDR, FDDR), Instruction Cache, Ethernet, CAN and USB Buffers, PCIe, MMUARTand SPI FIFOs SECDED (aka ECC or EDAC) protection SmartFusion2 architecture is designed to target reliability applications with the following features: LOW POWER SmartFusion2 is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power 01.0 mw operation for low duty cycle applications. The device family includes important low power features: Flash*Freeze Duty Cycle operation on the 50K LUT device real-time low power state 3

4 SmartFusion 2 Block Diagram FPGA fabric and firmware. The Microcontroller Subsystem (MSS) has multiple interfaces to the FPGA, to allow for peripheral expansion and algorithm acceleration in the fabric. By using the flash process we can include embedded nonvolatile memory for data and code storage, and have significant advantages in design and data security. JTAG I/O SPI I/O Multi-Standard User I/O (MISO) DDR User I/O System Controller SPI x 2 MMUART x 2 I 2 C x 2 Timer x 2 Microcontroller Subsystem (MSS) ARM Cortex -M3 MPU ETM D I S Instruction Cache AES256 ECC SHA256 NRBG Flash*Freeze SRAM-PUF In-Application Programming CAN WDT RTC FIIC APB PDMA HS USB OTG ULPI SYSREG AHB Bus Matrix (ABM) envm DDR Bridge MSS DDR Controller + PHY Multi-Standard User I/O (MISO) FPGA Fabric Micro SRAM (64x18) COMM_BLK FIC_0 FIC_1 TSE MAC esram HPDMA Interupts AHB AHB AHB SMC_FIC Config AXI/AHB Large SRAM (1024x18) Math Block MACC (18x18) INDUSTRIAL DEFENSE AVIATION COMMUNICATIO Multi-Standard User I/O (MISO) Micro SRAM (64x18) Large SRAM (1024x18) Math Block MACC (18x18) Config AXI/AHB/XGXS Config AXI/AHB/XGXS Config AXI/AHB Serial Controller 0 (PCIe, XAUI/XGXS) + Native SERDES OSCs Serial Controller 1 (PCIe, XAUI/XGXS) + Native SERDES PLLs Fabric DDR Controller + PHY Standard Cell / SEU Immune Flash Based / SEU Immune Serial 0 I/O Serial 1 I/O DDR User I/O AES Advanced Encryption Standard MDDR DDR2/3 Controller in MSS AHB Advanced High-Performance Bus MMUART Multi-Mode UART APB Advanced Peripheral Bus MPU Memory Protection Unit AXI Advanced extensible Interface MSS Microcontroller Subsystem COMM_BLK Communication Block SECDED Single Error Correct Double Error Detect DDR Double Data Rate SEU Single Event Upset DPA Differential Power Analysis SHA Secure Hashing Algorithm ECC Elliptical Curve Cryptography SMC_FIC Soft Memory Controller EDAC Error Detection And Correction TSE Triple Speed Ethernet (10/100/1000 Mbps) ETM Embedded Trace Macrocell ULPI UTMI + Low Pin Interface FDDR DDR2/3 controller in FPGA fabric UTMI USB 2.0 Transceiver Macrocell Interface FIC Fabric Interface Controller WDT Watchdog Timer FIIC Fabric Interface Interrupt Controller XAUI 10 Gbps Attachment Unit Interface HS USB OTG High Speed USB (2.0) On-The-Go XGMII 10 Gigabit Media Independent Interface IAP In-Application Programming XGXS XGMII Extended Sublayer MACC Multiply-Accumulate 4

5 SmartFusion 2 Architecture SmartFusion2 integrates for the first time non-volatile flash-based FPGA with a full-feature microcontroller subsystem, enhanced FPGA fabric and high-speed serial and memory interfaces. The FPGA fabric composed of 4-input LUT logic elements, includes embedded memories and mathblocks for DSP processing capabilities. The MSS subsystem adds the embedded trace macrocell, instruction cache and includes USB, CAN and gigabit Ethernet. The addition of high-speed serial interfaces with up to 16 SERDES lanes supports PCIe Gen2 x 4, XAUI and Native SERDES interfaces. Up to two high-speed DDR interfaces are included, one from the MSS and one from the fabric supporting LPDDR, DDR2 and DDR3. SPECIFICATIONS NS High-Performance SoC FPGA performance and low power and 1 write port (micro SRAM) - Up to 240 fast math blocks with 18 x 18 multiplier and 44-bit accumulator High-Speed Serial Interfaces Ethernet PHY interface) - Native SERDES interface facilitates implementation of serial RapidIO in Fabric or an SGMII interface to the Ethernet MAC in MSS - PCI Express (PCIe) Endpoint Controller x1, x2, x4 lane master and slave interfaces to the application layer High-Speed Memory Interfaces - MSS DDR (MDDR) and fabric DDR (FDDR) controllers - Supports various DRAM bus width modes, x16, x18, x32, x36 - Supports data reordering, returning critical word first for each command Microcontroller Subsystem - 8 KB instruction cache - Embedded Trace macrocell (ETM) - Memory protection unit (MPU) - Single cycle multiplication, hardware divide - JTAG debug (4 wires), serial wire debug (SWD, 2 wires), and serial wire viewer (SWV) interfaces supporting bit rate of 480 Mbps with ULPI interface 32 transmit and 32 receive buffers DDR memory) with 64-bit AXI interface Cortex-M3 processor - 8-Channel peripheral DMA (PDMA) for data transfer between MSS peripherals and memory - High-performance DMA (HPDMA) for data transfer between esram and DDR memories 5

6 Select Applications Motor Control Aviation New mandates for power efficiency and security in motor control applications are increasing the complexity of motor and motion control algorithms. To meet these new requirements users are replacing critical firmware algorithms with hardware acceleration. SmartFusion2 SoC FPGAs offer the designers of motor control systems flexibility, reliability and security for today s and tomorrow s complex motor control systems all in a single chip. Being immune to SEU FPGA configuration upsets, Microsemi SoC FPGAs can be used at the highest Design Assurance Level (DAL) for flight critical operations with confidence. Reliable, secure, and low power AFDX end systems can be created in a single chip using SmartFusion2, alternatively a PCI Express or PCI interface can be used to support existing Host Processors. Or the device can be used as an AFDX switch as shown. System Management For designers of complex, high availability systems, SmartFusion2 is a reliable system management solution that provides superior uptime. System Management is a collection of functions that are needed to control to fan control to reset management to booting the host CPU securely, every design has unique system management requirements. A highly flexible, reliable, and secure system management solution is needed to address all aspects of today s complex system management requirements. 6

7 SmartFusion 2 Design Resources Libero System Builder System designers can leverage the newly released, easy-to-use Libero system-on-chip (SoC) software toolset for designing SmartFusion2 devices. Libero SoC integrates industry leading synthesis, debug and DSP support from Synopsys, simulation from Mentor Graphics with power analysis, timing analysis and push button design flow. Firmware development is fully integrated into Libero SoC with compile and debug available from GNU, IAR and Keil, and all device drivers on System Builder selections. The ARM Cortex-M3 processor includes operating system support for based designs. System builder walks the user through the following steps: SmartDebug is a new debug tool added in Libero SoC v11.0 software that supports probe capabilities in the SmartFusion2 architecture and also supports device debug features for memory. SmartFusion2 devices have built in probe points that greatly enhance the ability to debug logic elements within the device. The enhanced debug features implemented into the SmartFusion2 devices give access to any logic element and enable designers to check the state of inputs and outputs in real time, without any relayout of the design. Live Probe and Active Probe are only available on the SmartFusion2 family of products. With Live Probe, two dedicated probes can be configured to observe a Probe Point which is any input or output of a logic element. The probe data can then be sent to an oscilloscope or even redirected back to Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This will enable a user to quickly observe the output of the logic internally or to quickly experiment on how the logic will be affected by writing to a probe point. SmartDebug features can be accessed from within the Libero design flow or FlashPro software. Compile and Debug Support Software IDE SoftConsole IAR Embedded Workbench Free Versions from Microsemi Free with Libero SoC 32 K Code Limited 32 K Code Limited Available from Vendor Full version Full Version Compiler GNU GCC RealView IAR ARM Compiler Debugger GDB Debug μvision Debugger C-SPY Debugger Instruction Set Simulator No μvision Simulator Yes Debug Hardware FlashPro4 ULINK 2 or ULINK-ME J-LINK or J-LINK Lite 7

8 SmartFusion 2 Product Family Features M2S005 M2S010 M2S025 M2S050 M2S080 M2S120 FPGA MSS High Speed User I/Os Logic Modules (4-Input LUT) 82, ,348 LSRAM 18K Blocks usram1k Blocks Total RAM (bits) 400K 1,314K 3,040K 4,500K Math Blocks PLLs and CCCs YES YES YES YES YES YES envm (Bytes) 128K 256K 256K 256K 512K 512K esram (Bytes) 64K 64K 64K 64K 64K 64K esram (Bytes non-secded) 80K 80K 80K 80K 80K 80K CAN 2.0A and B USB 2.0 High Speed On-The-Go Multi-Mode UART SPI I2C Timer DDR Controllers 1x18 1x18 1x18 2x36 2x36 2x36 SERDES Channels PCIe End Point x V MSIO MSIOD DDRIO Package Options VF400 FG484 FG896 FC 1152 Pin Count Ball Pitch 0.8 mm 1.0 mm 1.0 mm 1.0 mm 23 mm x 23 mm 31 mm x 31 mm 35 mm x 35 mm XCVR s XCVR s XCVR s XCVR s M2S M2S M2S M2S M2S080 8 M2S Microsemi Corporate Headquarters sales.support@microsemi.com Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance, radiation-hardened and highly reliable analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.