SmartFusion 2 SoC FPGAs

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Roland Crawford
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1 FPGAs and SOCs s

the communications, industrial, medical,

2 SmartFusion2 SoC FPGAs SmartFusion2 SoC FPGAs More Resources in Low-Density Devices with the Lowest Power, Proven Security and Exceptional Reliability These devices are ideal for general-purpose functions such as Gigabit or dual PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management and secure connectivity. Microchip FPGAs are used by customers in the communications, industrial, medical, defense and aviation markets. Communications Industrial Defense Automotive SmartFusion2 Advantages More Resources in Low-Density Devices Arm Cortex -M3 with embedded fl ash PCIe Gen2 support in 10K LE Comprehensive microcontroller subsystem With Clear Advantages Lowest Power Reduces total power by up to 50% 70 mw per 5G SERDES (PCIe Gen2) Proven Security Protection from overbuilding and cloning Secure boot for FPGA and processors Exceptional Reliability SEU immune zero FIT fl ash FPGA confi guration Reliable safety-critical and mission-critical systems Integration Low Power Reliability Security 2

SmartFusion2 FPGA Architecture SmartFusion2 SoC FPGAs SmartFusion2 SoC FPGAs offer 5K 150K LEs with a 166 MHz Arm Cortex-M3 processor, including ETM and instruction cache with on-chip esram and envm,

2G Up to 150K LEs, 5 Mb SRAM, 4 Mb envm Hard 667 Mbps DDR2/3 controllers Integrated DSP processing blocks Power as low as 7 mw standby, typical DPA-hardened, AES256, SHA256, on-demand NVM data

Timer x 2 Microcontroller Subsystem (MSS) MPU ARM Cortex -M3 ETM D I S Instruction Cache CAN Multi-standard User I/O (MSIO) ECC Flash*Freeze NRBG In-Application Programming WDT RTC FIIC APB COMM_BLK

3 SmartFusion2 FPGA Architecture SmartFusion2 SoC FPGAs SmartFusion2 SoC FPGAs offer 5K 150K LEs with a 166 MHz Arm Cortex-M3 processor, including ETM and instruction cache with on-chip esram and envm, and a complete microcontroller subsystem with extensive peripherals, including CAN, TSE and USB. Up to 16 transceiver lanes PCIe Gen2, XAUI/XGXS+, generic (EPCS) mode at 3.2G Up to 150K LEs, 5 Mb SRAM, 4 Mb envm Hard 667 Mbps DDR2/3 controllers Integrated DSP processing blocks Power as low as 7 mw standby, typical DPA-hardened, AES256, SHA256, on-demand NVM data integrity check SEU-protected-tolerant memories: esrams, DDR bridges JTAG I/O SPI I/O Multi-standard User I/O (MSIO) DDR User I/O AES256 System Controller SHA256 SRAM-PUF SPI x 2 MMUART x 2 I 2 C x 2 Timer x 2 Microcontroller Subsystem (MSS) MPU ARM Cortex -M3 ETM D I S Instruction Cache CAN Multi-standard User I/O (MSIO) ECC Flash*Freeze NRBG In-Application Programming WDT RTC FIIC APB COMM_BLK PDMA FIC_0 HS USB OTG ULPI SYSREG AHB Bus Matrix (ABM) FIC_1 TSE MAC envm DDR Bridge Interrupts APB AHB AHB SMC_FIC Config AXI/AHB FPGA Fabric (Up to 150K Logic Elements) esram HPDMA MSS DDR Controller + PHY Multi-standard User I/O (MSIO) Micro SRAM (64x18) Large SRAM (1024x18) Math Block MACC (18x18) Micro SRAM (64x18) Large SRAM (1024x18) Math Block MACC (18x18) Config AXI/AHB/XGXS Config AXI/AHB/XGXS Config AXI/AHB Serial Controller 0 (PCIe, XAUI/XGXS) + Native SERDES OSCs Serial Controller 1 (PCIe, XAUI/XGXS) + Native SERDES PLLs Fabric DDR Controller + PHY Serial 0 I/O Serial 1 I/O DDR User I/O Standard Cell/ SEU Immune Flash-based/ SEU Immune AES Advanced Encryption Standard AHB Advanced High-Performance Bus APB Advanced Peripheral Bus AXI Advanced extensible COMM_BLK Communication Block DDR Double Data Rate DPA Diff erential Power Analysis ECC Elliptical-Curve Cryptography EDAC Error Detection and Correction ETM Embedded Trace Macrocell FDDR DDR2/3 Controller in FPGA Fabric FIC Fabric Controller FIIC Fabric Interrupt Controller HS USB OTG High-Speed USB (2.0) On-The-Go IAP In-Applications Programming MACC Multiple-Accumulate MDDR DDR2/3 Controller in MSS MMUART Multi-Mode UART MPU Memory Protection Unit MSS Microcontroller Subsystem SECDED Single Error Correct Double Error Detect SEU Single Event Upset SHA Secure Hashing Algorithm SMC_FIC Soft Memory Controller TSE Tiple Speed (10/100/1000 Mbps) ULPI UTMI + Low Pin UTMI USB 2.0 Transceiver Macrocell WDT Watchdog Timer XAUI 10 Gbps Attachment Unit XGMII 10 Gigabit Media Independent XGXS XGMII Extended Sublayer SmartFusion2 SoC FPGAs 3

4 General-Purpose Applications PCIe 1G Control Plan PCIe Gen2 in 10K LE devices with I/O expansion Board Initialization PMBus, instant-on and MSS peripherals 10/100 PHY DDR3 DRAM SPI FLASH Gigabit PHY SmartFusion 2 Soc FPGA SERDES Security Arm Cortex -M3 PCIe SPI MCU Peripherals Flash, SRAM SPI USB DDR3 DRAM LCD RJ45/SFP RJ45/SFP PHY PoE PD69208 PHY PoE PD69208 Switch Host I 2 C PoE Managers espi I 2 C Controller System Control espi Controller PMBus PMBus 5 V PoL Supply 3.3 V PoL Supply 2.5 V PoL Supply 1.5 V PoL Supply I 2 C GPIO FPGA Fabric CPU RJ45/SFP PHY PoE PD69208 Clock Management Status LEDs Multi-Axis Motor Control Deterministic and secure multi-axis/high-rpm solutions Motor-control IP and development kit Secure Connectivity: Gaming Security, anti-tamper and MAC low power Timing Battery Battery Monitor PCIe PCIe Host Automation Controller/ Host CPU System Control PWM Timing Inverter Bridge, IGBTs, SiC MOSFETS Anti-Tampering Sensors Anti-Tamper Monitor Memory Controller I/O Expander DDR Memory Status LEDs Serial IO, Diagnostics Port Power Supply/ Conversion Host envm, esram Power Management PID Control Loop Transforms Sensors: Speed, Torque, Position A/D Conversion PHY System Monitoring MAC System Diagnostics HMI Speaker, Keypad, Joystick IEEE 1588 Slave/Client IEEE 1588 and small form factor, Cortex-M3, low power Audio Processing, Storage and Retrieval I 2 S and SPI bridge allows multiple audio recordings and playbacks SmartFusion2 Soc FPGA SPI Flash 1588 PTP OC IP Algorithm Time and Synch IP Oscillator 2 Digital MEMS Microphones DDR3 VSC8572 PHY Time Stamp Unit Transport Layer Protocols Time Stamp Unit ARM Cortex -M3 SPI SPI ZL30722 IEEE 1588 PLL Clock and PPS Timberwolf ZL38051 Audio Audio Jack I 2 S Conversion, Buffering and Formatter Host SPI SPI Flash SyncE PLL 4

Clear Advantages Low Power SmartFusion2 Reduces Total Power Flash FPGAs deliver lowest power without sacrifi cing

Error-free SEU immune fabric confi guration No scrubbing required All SoC memory SEU-protected Built-in error

systems SRAM Configuration Failures Alpha/ Neutron particles strike routing matrix Proven Security Protect Systems

cloning Only FPGA vendor with validated DPA countermeasures Secure boot for FPGAs and processors Flash FPGA No

5 Clear Advantages Low Power SmartFusion2 Reduces Total Power Flash FPGAs deliver lowest power without sacrifi cing performance 70 mw per 5G SERDES (PCIe Gen2) Flash*Freeze ultra-low-power mode 12 mw Exceptional Reliability Error-free SEU immune fabric confi guration No scrubbing required All SoC memory SEU-protected Built-in error detection and correction SEU-tolerant implementation Devices deployed in safety-critical and mission-critical systems SRAM Configuration Failures Alpha/ Neutron particles strike routing matrix Proven Security Protect Systems from Over-building and Cloning HSMs protection from overbuilding DPA countermeasures protect bitstream from cloning Only FPGA vendor with validated DPA countermeasures Secure boot for FPGAs and processors Flash FPGA No Error SRAM FPGA Functional Failure The following logo is a trademark of Cryptography Research, Inc. used under license. SmartFusion2 SoC FPGAs 5

SmartFusion2 Design Resources Design Resrouces The Libero SoC Design Suite enables high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with

The suite integrates industry-standard Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim simulation tools with best-in-class constraints management, debug capabilities, and secure

6 SmartFusion2 Design Resources Design Resrouces The Libero SoC Design Suite enables high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with Microchip s power-efficient SmartFusion2, IGLOO 2, and RTG4 FPGAs. The suite integrates industry-standard Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim simulation tools with best-in-class constraints management, debug capabilities, and secure production programming support. Libero SoC Design Suite provides a comprehensive design flow including traditional FPGA design flow, embedded design flow and graphical configurators. FPGA design flow is the standard VLSI design flow starting from design entry till programing and debug. The embedded design flow enables development of embedded processing solutions for high performance and high reliability applications using low-power SoC FPGAs and FPGAs. It provides comprehensive development environment to build embedded solutions using hard core and soft core processors. Graphical configurators provide a user friendly design entry approach for various peripherals, applications and solutions. System Builder Wizard For more information, please see the following website: Software IDE SoftConsole Keil MDK IAR Embedded Workbench Free Versions from Microchip Free with Libero SoC 32K Code Limited 32K Code Limited Available from Vendor N/A Full Version Full Version Compiler GNU GCC RealView C/C++ IAR Arm Compiler Debugger GDB Debug μvision Debugger C-SPY Debugger Instruction Set Simulator No μvision Simulator Yes Debug Hardware FlashPro4 ULINK 2 or ULINK-ME J-LINK or J-LINK Lite Trace Capability No ULINKpro JTAGjet-Trace Intellectual Property Microchip enhances your design productivity by providing an extensive suite of proven and optimized IP cores for use with Microchip FPGAs. Our extensive suite of IP cores covers all key markets and applications. Our cores are organized into Microchipdeveloped DirectCores and third-party-developed CompanionCores. Most DirectCores are available for free within our Libero tool suite and include common communications interfaces, peripherals and processing elements. Functionality Connectivity DSP Memory Controller Security DirectCore Examples UART, 16550, 429, PCI, JESD204B CIC, FFT, FIR, CORDIC, RS FIFO, DDR, QDR, SDR, MemCtrl, MMC 8051, 8051s, ARM7TDMI MII, RGMII, GMII, DES, 3DES, AES, SHA Functionality CompanionCore Examples Connectivity CAN, CAN FD, PCIe, VME DSP FFT, JPEG, RS, DVBMOD Memory Controller SDRAMDDR, Flash, SD 80188, 80186, LEON3, 6809 Security MD5, ARC4, RNG, ZUC, AES, SHA, 802.1ae (MACSec) 6

7 Product Family SmartFusion2 Product Family SmartFusion2 Features M2S005 M2S010 M2S025 M2S050 M2S060 M2S090 M2S150 Logic/DSP MSS Fabric Memory High Speed User I/O Maximum Logic Elements (4LUT + DFF) 6,060 12,084 27,696 56,340 56,520 86, ,124 Math Blocks (18x18) Fabric Controllers (FICs) PLLs and CCCs Security AES256, SHA256, RNG AES256, SHA256, RNG, ECC, PUF Cortex -M3 + Instruction Cache Yes envm (KBytes) esram (KBytes) 64 esram (KBytes) Non-SECDED 80 CAN, 10/100/1000, HS USB 1 Each Multi-Mode UART, SPI, I 2 C Timer 2 Each LSRAM 18K Block usram 1K Blocks Total RAM (Kbits) ,314 2,074 4,488 DDR Controllers (count x width) 1 x 18 2 x 36 1 x 18 2 x 36 SERDES Lanes PCIe End Point MSIO (3.3V) MSIOD (2.5V) DDRIO (2.5V) Total User I/Os I/Os Per Package Package Types FCS(G)325 VF(G)256 FCS(G)536 VF(G)400 FCV(G)484 TQ(G)144 FG(G)484 FG(G)676 FG(G)896 FC(G)1152 Pitch (mm) Length x Width (mm) 11 x x x x x x x x x x 35 Device I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes M2S005 (S) M2S010 (S/T/TS) M2S025 (T/TS) M2S050 (T/TS) M2S060 (T/TS) M2S090 (T/TS) M2S150 (T/TS) Note: 090 FCSG325 is 11x13.5 package dimension SmartFusion2 SoC FPGAs 7

8 Support Microchip is committed to supporting its customers in developing products faster and more effi ciently. We maintain a worldwide network of fi eld applications engineers and technical support ready to provide product and system assistance. For more information, please visit Technical Support: Evaluation samples: Knowledge base and peer help: /forums Sales and Global Distribution: /sales Training If additional training interests you, Microchip off ers several resources including in-depth technical training and reference material, self-paced tutorials and signifi cant online resources. Overview of Technical Training Resources: /training MASTERs Conferences: /masters Developer Help Website: /developerhelp Technical Training Centers: /seminars Sales Office Listing AMERICAS EUROPE EUROPE ASIA/PACIFIC ASIA/PACIFIC Atlanta, GA Tel: Austria - Wels Tel: Israel - Ra anana Tel: Australia - Sydney Tel: China - Zhuhai Tel: Austin, TX Tel: Denmark - Copenhagen Tel: Italy - Milan Tel: China - Beijing Tel: India - Bangalore Tel: Boston, MA Tel: Finland - Espoo Tel: Italy - Padova Tel: China - Chengdu Tel: India - New Delhi Tel: Chandler, AZ (HQ) Tel: France - Paris Tel: Netherlands - Drunen Tel: China - Chongqing Tel: India - Pune Tel: Chicago, IL Tel: Germany - Garching Tel: Norway - Trondheim Tel: China - Dongguan Tel: Japan - Osaka Tel: Dallas, TX Tel: Germany - Haan Tel: Poland - Warsaw Tel: China - Guangzhou Tel: Japan - Tokyo Tel: Detroit, MI Tel: Germany - Heilbronn Tel: Romania - Bucharest Tel: China - Hangzhou Tel: Korea - Daegu Tel: Houston, TX Tel: Germany - Karlsruhe Tel: Spain - Madrid Tel: China - Hong Kong SAR Tel: Korea - Seoul Tel: Indianapolis, IN Tel: Tel: Los Angeles, CA Tel: Tel: Raleigh, NC Tel: New York, NY Tel: San Jose, CA Tel: Tel: Canada - Toronto Tel: Germany - Munich Tel: Germany - Rosenheim Tel: Sweden - Gothenberg Tel: Sweden - Stockholm Tel: UK - Wokingham Tel: China - Nanjing Tel: China - Qingdao Tel: China - Shanghai Tel: China - Shenyang Tel: China - Shenzhen Tel: China - Suzhou Tel: China - Wuhan Tel: China - Xiamen Tel: China - Xian Tel: Malaysia - Kuala Lumpur Tel: Malaysia - Penang Tel: Philippines - Manila Tel: Singapore Tel: Taiwan - Hsin Chu Tel: Taiwan - Kaohsiung Tel: Taiwan - Taipei Tel: Thailand - Bangkok Tel: Vietnam - Ho Chi Minh Tel: /15/18 Microchip Technology Inc W. Chandler Blvd. Chandler AZ, The Microchip name and logo, the Microchip logo, IGLOO, Libero and SmartFusion are trademarks and RG4 and Timberwolf are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies. 2019, Microchip Technology Incorporated. All Rights Reserved. 1/19 DS A

+/- X EN. SmartFusion 2 SoC FPGAs CO LO LUT4 CIN NC_SR CLK RST. ARM Cortex -M3 HS USB OTG 10/100/1000 Ethernet PCI Express Gen2 Up to 150K LEs

+/- X EN. SmartFusion 2 SoC FPGAs CO LO LUT4 CIN NC_SR CLK RST. ARM Cortex -M3 HS USB OTG 10/100/1000 Ethernet PCI Express Gen2 Up to 150K LEs SmartFusion 2 SoC FPGAs ARM Cortex -M3 HS USB OTG 10/100/1000 PCI Express Gen2 Up to 150K LEs CO LO A B C D CIN _BYP EN NC_SR CLK RST LUT4 OVFL UB ADD_S ] A[17:0 D EN RO D +/- X EN ] C[43:0 SL ] B[17:0