ADVANCES IN PROCESSOR DESIGN AND THE EFFECTS OF MOORES LAW AND AMDAHLS LAW IN RELATION TO THROUGHPUT MEMORY CAPACITY AND PARALLEL PROCESSING

Transcription

1 ADVANCES IN PROCESSOR DESIGN AND THE EFFECTS OF MOORES LAW AND AMDAHLS LAW IN RELATION TO THROUGHPUT MEMORY CAPACITY AND PARALLEL PROCESSING Evan Baytan Department of Electrical Engineering and Computer Science University of Central Florida Orlando, FL Page! 1 of! 7

2 Abstract In this paper we analyze the implementation of varying design techniques and their effects on processor architecture metrics. The metrics closely analyzed include: Die Area, CPU Clock Rate, Memory Capacity, Data Bus Word Width, Number of Cores or CPUs and Ideal Speedup for 99% parallel code. The metrics analyzed are then compared across the different processor architectures to identify trends or observations in relation to Moore s Law, Amdahl s Law and other relationships for performance. The references for the processor architectures used provide the year they were developed, and this is utilized to visually observe the changes to the chosen metrics over time. Keywords Clock Rate, Memory Capacity, Moore s Law, Amdahl s Law, Power Dissipation, Parallel Processing, Throughput, Pipelined, Multi-core, Multi-threaded, FIR Filter I. OVERVIEW OF PROCESSOR ARCHITECTURE 1) Classic Components: The five classic components of a computer system consist of: Data Path, Control, Memory, Input and Output. Control communicates with Memory, ALU, and I/O by providing signals on how to reply to calls from the CPU. Data Path performs the actual processing and data transfer from the Memory to the CPU. These methods of I/O provide the ability for the CPU and Memory to communicate and operate. Von Neumann architecture also consists of five components. Arithmetic Logic Unit, Control Unit, Memory, Input and Output. These components are seen to be synonymous with the five classic components of a computer system. 2) Processor Busses and Bit Width: CPU and Memory are two of the five classic components needed for computation. Data is often read and written to Memory due to the space required. When the CPU requests data from Memory, it will send the address of where it is stored across the address bus. Memory is accessed by means of these addresses. Memory then outputs the data at that corresponding address across the data bus to the CPU. The address bus is unidirectional from the CPU to Memory. The data bus is bidirectional between the CPU and Memory. 3) Metrics Studied: Clock Rate is a measure of how many clocks are executed per second. Clock Rate is typically expressed in the unit hertz (e.g. MHz, GHz). The unit hertz represents frequency or one cycle per second. Memory Capacity is the amount of space available for the storage and transfer of data (e.g. variables, instructions). Memory Capacity is typically represented in the unit byte (e.g. MB, GB). A byte also represents 8 bits and is often referred to as being the smallest addressable unit of memory. MB refers to a magnitude of a million bytes, and GB refers to a magnitude of a billion bytes. Number of Processors or Cores is a measure of how many instructions that can be processed at the same time. MIPS is a single core processor, in which only one instruction can be executed at a time. The number of cores is typically expressed in terms of Dual-Core, Quad-Core, 8- Core, etc. Data Bus Word-Width is a metric of how large the registers are in a CPU. It also determines the size of data that can be transferred to and from memory. Word- Width is expressed in the unit of bits. A bit can only have the values or 1 when representing information. Most computer systems use word-widths of 32 or 64 bits. MIPS is a 32-bit CPU that is used in the lab for EEL381C. Instruction Set Size represents the data types and instructions that can be used by a particular CPU. Instruction Set is often referred to as ISA or Instruction Set Architecture. The types of data and memory access are also determined by the ISA for the CPU. MIPS and x86 vary in their ISA s and therefore provide different instructions and their manipulation of registers. 4) Significance: Metrics examined and evaluated in Table 1 provide a general but supportive analysis of a CPU and its relative performance. All metrics covered have increased respectively over the past 2 years. In particular, transistor count has been closely following the observation of Moore s Law. The amount of transistors has doubled every 18 months to 2 years. The four metrics analyzed can be applied to any CPU in question to measure it s relative performance. These metrics can be used as benchmarks towards improvement and speedup factors for a given computer system. Amdahl s Law is also closely referenced in relation to parallel processing and usage for speedup. This is achieved by the introduction of multiple cores in CPU s. 5) Processor Performance Equation: IC represents Instruction Count in the equation above. IC equates to the number of dynamic instructions executed at runtime. This can be obtained in MARS4.5 > Tools > Instruction Counter. CPI represents the effective or average number of clocks per instruction (e.g. 1.5, 4.5). Cycle Time represents the time for one complete clock cycle (e.g..5 nsec, 5 psec). 6) Parallelism: Involves the process of dividing a larger task into numerous smaller sub-tasks to be computed at the same time. Multi-core computer systems utilize this principle to process multiple instructions simultaneously. Each core reads and executes instructions which greatly reduces execution time and increases throughput. Execution Time is the best performance metric for benchmarking performance. Multiple cores are typically integrated onto the same die of a packaged CPU. The limits of parallelism and it s applications to program code rely on the fraction that is sequential code. The ideal case is for 1. or 1% of code to be parallelizable. Amdahl s Law revolves around the effects of improving a particular component of a system, and how the speedup ultimately relies on the proportion the component is utilized in the system. In other words, to obtain a higher speedup factor, it is best to improve the component that makes up a larger percentage of the system. Page! 2 of! 7

3 Section II proceeds with the evaluation and analysis of five baseline computer systems, and five comparison design systems in relation to the metrics discussed in Section I Part 3. The data and results obtained are then organized based on decade to express the metrics covered and their effects over the years. Section III dives deeper into the analysis of the respective metrics covered. The trends for the metrics are tabulated and plotted to show a visual representation of Moore s Law, Amdahl s Law, and the improvement of computer systems as a whole. II. LITERATURE REVIEW 1. Five Baseline Design Computer Systems: 1. [1] 2. [1] 3. Athlon XP3+ [1] 4. FIR Filter [2] 5. [3] Metrics analyzed for the design of architecture includes: Die Area, CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [1]. Metrics analyzed for the design of architecture includes: Die Area, CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [1]. and architectures were evaluated using the same metrics [1]. Metrics analyzed for the design of FIR Filter architecture includes: CPU Clock Rate and Data Bus Word Width [2]. Metrics analyzed for the design of architecture includes: CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup [3]. Memory Capacity was obtained for 8% of the baseline designs [1, 3] and three of the comparison designs [6, 7, 8]. 2. Five Comparison Design Computer Systems: 1. [4] 2. Processor [5] 3. Processor [6] 4. Processor [7] 5. Processor [8] Metrics analyzed for the design of architecture includes: CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [4]. Metrics analyzed for the design of Processor architecture includes: Die Area, CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [5]. Metrics analyzed for the design of 8-Core Enterprise Xeon Processor architecture includes: Die Area, CPU Clock Rate, Data Bus Word Width, Number of Cores/ CPUs and Ideal Speedup for 99% parallel code [6]. Metrics analyzed for the design of Processor architecture includes: Die Area, CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [7]. Metrics analyzed for the design of Processor architecture includes: CPU Clock Rate, Data Bus Word Width, Number of Cores/CPUs and Ideal Speedup for 99% parallel code [8]. CMOS logic was determined for 6% of the comparison designs [6, 7, 8] and one of the baseline designs [2]. 3) Baseline and Comparison Designs Timeline* (1993) 2-29 (25) (25) Athlon XP3+ (25) FIR Filter (26) (29) Processor (21) Processor (211) Processor (211) Processor (214) * Timeline years are based off the year of the paper 4) Summary of Baseline and Comparison Designs In 1993, the architecture design was introduced [3]. The design was applied to natural language understanding (NLU). NLU is a component of artificial intelligence. It contained 144 DSP chips connected to 8 circuit boards. The DSP chips had a clock rate of 25 MHz and a data bus word width of 32 bits. The design consisted of 144 single core processors. SNAP-1 utilized parallelism to increase speed and accuracy. In 25, the architecture design was introduced [1]. The design was applied to One Semi- Automated Forces Testbed (OTBSAF). OTBSAF is a simulation application that was adapted for embedded training and benchmarking. The area of the die was 8 mm 2. Not as large of a die compared to the design. The chips had a clock rate of 1 MHz and a data bus word width of 32 bits. The design consisted of a single core, in which parallelism was not introduced. In 25, the architecture design was introduced [1]. The design was also applied to OTBSAF simulation benchmarking. The area of the die was 217 mm 2. The die was more than double the size of the previous design. The chips had a clock rate of 2 MHz and a data bus word width of 32 or 64 bits. introduced 64-bit instruction set architecture. The design consisted of a single core, in which parallelism was not introduced to increase speed and throughput. In 25, the Athlon XP3+ architecture design was introduced [1]. The design was also applied to OTBSAF simulation benchmarking. The area of the die was 11 mm 2. The die size was around the same as a chip. The chips had a clock rate of 2 MHz and a data bus word Page! 3 of! 7

4 width of 32 bits. The design consisted of a single core processor, in which parallelism was not utilized. In 26, the FIR Filter architecture design was introduced [2]. The design was applied by 2-Dimensional pipeline gating in order to improve power awareness of pipelined array multipliers. The design consisted of.24 µm static CMOS logic. The hardware had a clock rate of 125 MHz and a data bus word width of 16 bits. The design did not specify the amount of cores and their affects on speedup. In 29, the architecture design was introduced [4]. The architecture was applied to parallel pipelined design to reduce power usage. The design consisted of 189 four-input LUTs and 397 flip-flops. The chip had a clock rate of 25.7 MHz and a data bus word width of 32 bits. The design consisted of a single core processor. In 21, the Processor design was introduced [6]. The architecture was implemented using a 45 nm nine-metal process. The design consisted of numerous clock and voltage domains to increase efficiency and decrease power consumed. The design incorporated 2.3 billion transistors. The area of the die was 684 mm 2. The chip had a clock rate of 227 MHz and a data bus word width of 64 bits. The design consisted of 8 cores and utilized parallelism to increase speed and throughput. In 211, the Processor design was introduced [7]. The architecture was applied with on-die message-passing and Dynamic Voltage and Frequency Scaling (DVFS) to increase performance and manage power. The design incorporated 1.3 billion transistors. The area of the die was 567 mm 2. The chip had a clock rate of 1 MHz and a data bus word width of 32 bits. The design consisted of 48 cores and utilized parallelism to increase speed and throughput. In 211, the Processor design was introduced [5]. The architecture was applied to signal processing applications, and more specifically convolution. The area of the die was.65 mm 2. The chip had a clock rate of 2 MHz and a data bus word width of 16 bits. The design consisted of a single core processor. The design did not utilize parallelism in its approach. In 214, the Processor design was introduced [8]. The architecture was applied with reconfigurable same-instruction multiple process (RSIMP) to decrease the amount of power that instruction memory consumes. The chip had a clock rate of 8 MHz and a data bus word width of 32. The design consisted of 16 cores and utilized parallelism to increase performance. III. DATA ANALYSIS Multiple plots were developed based on the data obtained from the reference papers. The X-Axis for the plots is organized chronologically from left to right. This is intended to show the differences between the metrics in question, and the year of when the paper was written. CPU clock rate is plotted in Figure 1 to compare the different architecture designs. The architectures that were used for embedded systems tended to have slower clock rates than those used for desktop applications (e.g. vs MIPS). Some designs developed between 2-29 had faster clock rates than those from This was not due to technology restrictions, but the specific design application. Number of Cores or CPUs CPU Clock Rate (MHz) Figure 1 - CPU Clock Rate vs. Architecture Design Athlon XP3+ FIR Filter Figure 2 - Number of Cores vs. Architecture Design Athlon XP3+ Page! 4 of! 7

5 Number of cores or CPUs is plotted in Figure 2 to compare the different architecture designs. There wasn t necessarily a correlation between when the design was developed and the number of cores or CPUs. This can be seen visually in the figure. The was developed around 1993 and supported 144 cores, while the was developed in 25 and supported 1 core. Die area (mm 2 ) is plotted in Figure 3 below to compare the different architecture designs. 6% of the architecture design papers provided the size for the die. Die area size peaks tremendously for the architecture, and then decreases in a linear scale. Desktop level architectures with multiple cores tended to have larger die areas than single core systems. Die Area (mm^2) Figure 3 - Die Area vs. Architecture Design Athlon XP3+ Ideal speedup for 99% parallel code is plotted in Figure 4 to compare the different architecture designs. Designs with multicore architectures resulted in higher speedup. Single processor designs did not utilize parallelism to increase performance and resulted in a speedup less than 1. Multicore processor architectures resulted in a speedup greater than 1. These observations can be seen in the figure. The FIR Filter architecture design did not provide the number of cores or CPUs. All but one of the computer architectures was plotted. Data bus word width is plotted in Figure 5 to compare the different architecture designs. There was no correlation between data bus word width and year. The and were the only 64-bit architecture designs. The was developed in 1993 and has a word width of 32-bits. The Low Power Multicore design was developed 214 and also has a word width of 32-bits. Thus, there is not a linear correlation. Page! 5 of! 7 Ideal Speedup for 99% Parallel Data Bus Word Width (bits) Figure 4 - Ideal Speedup for 99% Parallel Code vs. Architecture Design Athlon XP3+ Figure 5 - Data Word Width vs. Architecture Design Athlon XP3+ FIR Filter

6 Memory Capacity (MB) Figure 6 Memory Capacity vs. Architecture Design Memory capacity is plotted in Figure 6 above to compare the different architecture designs. There was no direct correlation between memory capacity increasing or decreasing depending on the year. The had the largest memory capacity, compared to the other three architecture designs that provided the metric. This is largely due to the amount of cores that the architecture design supported. The Processor had a significantly lower memory capacity compared to the rest. The memory capacity was all dependent on the architecture design used and its application. instead for small embedded systems. This affected metrics such as CPU Clock Rate, Die Area, Data Bus Word Width and more just to name a few. Energy efficiency was not closely analyzed for the different architecture designs, but from the research performed, processor architectures are becoming more energy efficient and consume less power over the past 15 years. The different techniques used for the architecture designs impact not only performance in regards to throughput and speed, but also towards energy efficiency. V. REFERENCES 1. H. A. Bahr and R. F. DeMara, "OTBSAF Scalability on /4 and Athlon 64/XP3 Architectures," in MSIAC Modeling and Simulation Journal, on February 9, 25, Vol.6, No. 3, March, 25, pp J. Di, J. S. Yuan, and R. F. DeMara, "Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application to FIR Design," Integration, the VLSI Journal, Vol. 39, No. 2, March, 26, pp R. F. DeMara and D. I. Moldovan, "The SNAP-1 Parallel AI Prototype," IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 8, August, 1993, pp Gautham, P.; Parthasarathy, R.; Balasubramanian, K., "Low-power pipelined MIPS processor design," Integrated Circuits, ISIC '9. Proceedings of the 29 12th International Symposium on, vol., no., pp.462,465, Dec Sakthikumaran, S.; Salivahanan, S.; Bhaaskaran, V.S.K., "16-Bit RISC processor design for convolution application," Recent Trends in Information Technology (ICRTIT), 211 International Conference on, vol., no., pp.394,397, 3-5 June Rusu, S.; Simon Tam; Muljono, H.; Stinson, J.; Ayers, D.; Chang, Jonathan; Varada, R.; Ratta, M.; Kottapalli, S.; Vora, S., "A 45 nm 8- Core Enterprise Xeon Processor," Solid-State Circuits, IEEE Journal of, vol.45, no.1, pp.7,14, Jan Howard, J.; Dighe, S.; Vangal, S.R.; Ruhl, G.; Borkar, N.; Jain, S.; Erraguntla, V.; Konow, M.; Riepen, M.; Gries, M.; Droege, G.; Lund- Larsen, T.; Steibl, S.; Borkar, S.; De, V.K.; Van Der Wijngaart, R., "A Processor in 45 nm CMOS Using On-Die Message- Passing and DVFS for Performance and Power Scaling," Solid-State Circuits, IEEE Journal of, vol.46, no.1, pp.173,183, Jan Zheng Yu; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng, "Low- Power Multicore Processor Design With Reconfigurable Same- Instruction Multiple Process," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.61, no.6, pp.423,427, June 214. IV. CONCLUSION Numerous metrics were evaluated for each processor architecture design. The designs differed in their approaches for optimization and increasing performance. Parallelism seemed to be the most used strategy for increasing throughput and speed. Amdahl s Law is closely observed in regards to speedup for multicore architectures. However, not all architecture designs were multicore in order to take advantage of parallelism. Five plots were created to compare the metrics observed versus the year the paper was published. It was assumed that the architecture design was developed around the same time as the year the paper was written. All of the metrics and data were tabulated into Table 1 and certain trends can be made. For one, Moore s Law can be identified when comparing the increase in the number of transistors for the architectures. The plots are not as linear as would be expected. This is largely due to the applications for the different architecture designs. Not all designs were used for use, but Page! 6 of! 7

7 Metrics Analyzed for Computer Architecture Designs Name of Architecture Design [reference] Purpose: Application-Specific or General-purpose Computation Die Area, Number of Transistors, or Number of Chips/ Boards/etc. CPU Clock Rate (MHz) Memory Capacity (MB) Data Bus Word Width (bits) Number of Cores or CPUs Ideal Speedup for 99% parallel code (ignoring overheads) [3] NLU: Special Purpose 144 DSP Chips on 8 large circuit boards KB/ CPU* 144 CPU = 36.86MB single core CPUs = 144 cores 144 cores so Told/ Tnew= 1/(.1+ (.99/144)) = fold [1] Desktop/Mobile Die Area = 8 mm 2 1 N/A 32 1 core 1/(.1 + (.99/1)) =.92-fold [1] Desktop/Mobile Die Area = 217 mm 2 2 N/A 32/64 1 core 1/(.1 + (.99/1)) =.92-fold Athlon XP3+ [1] Desktop/Mobile Die Area = 11 mm 2 2 N/A 32 1 core 1/(.1 + (.99/1)) =.92-fold FIR Filter [2] Low Power Design: 2D Pipeline Gating.24 um static CMOS logic 125 N/A 16 N/A N/A [4] Embedded Systems 189 four-input LUTs and 397 flipflops 25.7 N/A 32 1 core 1/(.1 + (.99/1)) =.92-fold Processor [5] Supercomputers / Microprocessors Die Area =.65 mm 2 2 N/A 16 1 core 1/(.1 + (.99/1)) =.92-fold Processor [6] Desktop 2.3 Billion transistors, Die Area = 684 mm 2, 45nm CMOS MB 64 8 core 1/(.1 + (.99/8)) = 4.47-fold Processor [7] Desktop Microprocessors 1.3 Billion transistors, Die Area = 567 mm 2, 45nm CMOS KB/ CPU* 48 CPU = 18.43MB core 1/(.1 + (.99/48)) = 8.29-fold Processor [8] Embedded Systems, Reduce IM power consumption 65 nm CMOS 8 32 KB/ CPU* 16 CPU =.5MB core 1/(.1 + (.99/16)) = 6.18-fold Page! 7 of! 7