Determining the Relevancy of Moore's Law Through the Comparison of Ten Distinct Processor Systems

Transcription

1 Determining the Relevancy of Moore's Law Through the Comparison of Ten Distinct Processor Systems Nickolas DeVito Department of Electrical Engineering and Computer Science University of Central Florida Orlando, FL Abstract The main purpose of this project is to compare and contrast the fundamental metrics and specifications of ten example processor architectures, dating from the 199s to the present day. CPU systems are analyzed based on their clock rates, memory capacity, number of or cores, and data bus word width. The most popular designs studied were parallel, multi-core microarchitectures for general or special purposes. baseline designs, such as Intel Pentium, AMD Athlon, and Xilinx FPGA-based architectures, were examined in this project, as were less historical designs, such as Xeon EX and OpenSPACE T1. Through this project's research, a better understanding of how different CPU systems operate will be achieved, as well as how Moore's Law still defines processor improvement rates in the computer industry. It is important to acknowledge these systems similarities and differences, as CPU architecture design is a massive field worldwide, and future innovations will determine how they improve. Keywords Amdahl's Law, Architecture, Baseline Computer Systems, Clock rate, Core, Data bus, Memory capacity, Moore s Law, Parallelism, Specifications, Speedup, Transistors. I. OVERVIEW OF PROCESSOR ARCHITECTURE Computer hardware involves a carefully implemented system of instruction sets operating under defined specifications. This project studies processor architecture by looking at ten different CPU systems, including five baseline computer systems. The components and principles being used to explore processor architecture are defined below. Performance data for the ten systems is also shown. 1) Classic Components: A computer system is typically made up of five classic components: datapath, control, memory, input, and output [1]. The datapath manipulates data that will be used within the computer. The control takes that data and determines how it will operate, effectively giving directions to the datapath. Together, the datapath and control form the computer's processor. Memory acts outside of the processor, storing and transmitting data, which can then be retrieved or rewritten after following directions from the control. The input and output both connect to external devices that the user can observe or manipulate. Input takes actions from the user, and translates them into directions for the processor, while output often takes data and gives it to the user to observe or download. Examples of input include keyboards, microphones, and the mouse, while output includes monitors and printers. In addition, certain systems act as both input and output, such as external hard drives and memory sticks. 2) Processor Buses and Bit Width: Interaction between a computer's processor and memory is necessary to complete basic functions. Data is transferred between the two components by the use of two buses, the address bus and data bus. Bits from the processor can be sent along the address bus to the memory, so that they can be stored. While the address bus can only send data in one direction, the data bus can transfer data to and from the processor and memory. This is because the information sent along the address bus is simply a direction for the memory address where information is stored. The actual data at that address can be sent to the processor along the data bus, so that it can be "crunched," and then sent back to the memory once the execution has been completed. The bit width refers to the number of wires in each bus. Since each wire can submit one binary digit at a time, having n wires allows for 2^n possible values to be had. 3) Metrics Studied: This project refers to several metrics that are used to study and evaluate the processor architectures. CPU clock rate (measured in MHz) generally refers to how fast a processor performs. This speed rate is evaluated by determining how many clock cycles can be executed in a second. Instruction set size (measured in bits) refers to how large a length the instructions held on a processor can be. Having a larger data bus width (and effectively greater instruction set size) means more machine instructions can be held, meaning a greater variety of CPU tasks can be executed. Memory capacity (measured in MB) refers to how large the memory of a computer system is, and therefore how much data can be stored. These metrics, and their respective units, can be seen in the graphs in Section 3 of this project. 4) Significance: It is important to look at these metrics when comparing computer architectures, because they can inherently be used to evaluate performance, and determine the rate at which they have improved over a period of time. Looking at clock rates between different is a good way to determine time enhancement, and the overall speedup of a system, in line with Amdahl's Law. Memory capacity can be used to illustrate Moore's Law. Page 1 of 5

2 Since having larger memory means more transistors are being used, systems of increasing memory capacity can be compared to evaluate the rate at which a system's memory doubles. 5) Processor Performance Equation: An equation exists that can be used to evaluate processor performance for different systems. Performance is inversely proportional to execution time, and execution time can be defined as a combination of instruction count, CPI, and clock rate. Instruction count refers to the number of instructions that need to be executed. CPI stands for clocks per instructions, and means how many clock cycles are needed to complete a single instruction. Clock rate (or cycle time) means the number of clocks needed to complete the program. Overall, the equation states: [Performance] = 1/[CPU Time] = 1/[Instruction Count]*[CPI]*[Cycle Time]. 6) Parallelism: Parallelism explains that multiple processor systems can be used in unison to form one large computer architecture, effectively increasing execution time, memory capacity, and overall performance [2]. Parallelism is a practice often used in large server mills and supercomputers, accomplishing more than a single desktop could achieve. While connecting hundreds of CPU units isn't cost or space efficient for consumer-based computers, parallelism can still be used on a smaller scale by installing multiple core. Dual core CPUs can store twice as much memory as single cores. Quad core CPUs can store four times as much, and so on. Having more cores also lowers execution time. Speedup factor compares the execution time of two different systems. If a single core system is turned into a dual core system, then programs could be executed twice as fast, as expressed by the following equation: [Speedup] = 1/[1-Fraction_ Enhanced]+[Franction_Enhanced/Speedup_Enhanced]. The next sections in this report will give a more direct look to how these concepts can be used to study processor architectures, by looking at ten specific examples. In Section 2 the ten processor architectures spanning from 199s until today will be introduced in detail. Section 3 will evaluate the data achieved by studying these architectures, and Section 4 will conclude with what can be learned from the charted metrics. II. LITERATURE REVIEW All ten processor systems were researched from various reports and sources. The findings for each system can be found below, starting with the five baseline computer systems and following with five non-baseline designs used as comparisons. The metrics can also be seen in Table : The MasPar MP-1 Model 128 Backend was developed in 1992, as a special purpose highly parallel architecture [2]. The SIMD architecture includes 8192 PEs, each containing a 4-bit processor with 16 KB of RAM. A -bit, 128 MHz processor controls data flow in the PE array. The SNAP-1 Parallel AI Prototype was first developed in 1992, as a special purpose architecture for natural language understanding [3]. Known as the SNAP project, the University of Southern California processor system included 144 -bit DSP chips (distributed over 8 different boards), each operating at 25 MHz. The local memory for each chip in the system was capable of storing 256 KB. The Intel Pentium III processor system was first designed in 1999, as a general purpose desktop architecture [1]. It utilized 18 -bit, each running at 1 GHz. Each CPU unit could store 256 KB of memory, making the computer system an ideal option for conducting simulation tests and achieving benchmark results. 2-29: The AMD Athlon 24+ Processor System was developed in 22, as a general purpose desktop architecture [1]. The computer system contains 256 parallelized, each running at 24 MHz (as the name suggests). All in the systems have a data length of bits, and can store 256 KB of memory. Like the Intel Pentium III, the AMD Athlon 24+ is also ideal for simulation tests and benchmark results, but the larger amount of and later release date means it has a better performance overall. In 26, the Xilinx Virtex-4 SX35 FPGA-Based Scalable Architecture was released as a special purpose architecture for DCT computation [4]. It achieved FPGA dynamic partial reconfiguration with 8 distinct core hardware arrangements (73577 gates overall), each operating at 1 MHz. The -bit single core CPUs could each store 2.3 MB of memory. The OpenSPARC T1 CPU Microarchitecture was also released in 26 (originally named the UltraSPARC T1) [8]. It was developed by Oracle with 8, 4-way multithreaded -bit cores, using a RTL model for simulation. Each core could store up to 3.19 MB of memory, and could run at 8 MHz. 28 saw the release of an Experimental Intel Core 2 Quad Machine, which was designed as a special purpose architecture for workload synthesis and statistical modeling (although a commercial version for general purposes came shortly after) [5]. It included 4 homogeneous -bit dual cores (8 in total), each operating at 24 MHz. The cores could each store 4.1 GB of memory, which is a huge amount compared to most other architectures, but having a smaller number of cores balanced out the total memory capabilities of the system. The Xeon EX Processor System was designed in 29 as a general purpose processor system with eight dual-threaded cores [6]. Each core held a data length of 64 bits, and overall, the system was made up of 2.3 billion transistors (45 nm in length). The CPU ran at MHz, and each core could contain 24 MB of system memory. 21-present: In 21, the IA 2D-Mesh Network-On-Chip Architecture was constructed as a special purpose message passing computer system [7]. Having 48 integrated cores (with 1.3 billion transistors) enabled the processor to accomplish rapid calculations at a pace previous CPU systems could not match. Page 2 of 5

3 The processor had a word width of bits, and each core could operate at 2 MHz, storing 256 KB of memory. The LTE MIMO Processor SIMT Architecture was first released in 213, to be a special purpose RSIMP approach system for parallel instruction sequences [9]. The system relied on 16 unique quad-core CPUs (4core-4wide), totaling 64 -bit cores in total. Each core could store KB of memory, while operating at a 8 MHz clock rate Clock Rate (MHz) vs. Time (Year) III. DATA ANALYSIS The data abstracted for all ten computer architectures (detailed in Table 1) were used to chart four different graphs evaluating relevant metrics over time. The four key metrics used to determine performance were clock rate, memory capacity, the number of total cores, and the data bus word width (see Figure 1 for more detailed explanation). Figure 2 shows the clock rates of each of the ten processor architectures over time. As can be seen in the graph, there is a visible growth in the amount of clocks a processor can compute per second. Naturally, the older architectures operate more slowly. Since having more transistors enables a higher clock rate, this graph shows a clear representation of Moore's Law acting on these systems. The rate of changing memory capacity for all systems over time can be seen in Figure 3. Although the graph shows a slight decline over time, this is due in part to the fact some architectures studied were special purpose systems with multiple parallel cores, and others were simple desktop systems. Looking at the potential for systems to store more memory, those that appear later over time (such as the Xilinx Virtex-4 SX35 and the Xeon EX) have the largest capacity. Figure 4 displays the number of cores present in architectures over time. This graph also shows a decline, but this is due to the 1992 MasPar MP-1 Model 128 Back End being an outlier with 8192 combined cores. Ignoring this shows a more reasonable range of cores being present in the architectures. Moreso, many newer systems are able to achieve greater or similar results with fewer cores because they have been better optimized for performance. Lastly, Figure 5 shows the varying lengths of each processor system's word width over time. Although the graph shows a visible increase, it's important to note that all but one of the systems studied supported a data bus with bits. The Xeon EX system's data bus was 64-bits long, despite having less cores than most architectures Fig. 2. Plot shows exponential growth of processor clock rate over time. Memory Capacity (MB) vs. Time (Year) Fig. 3. Plot shows total memory capacity of architectures over time. Number of Cores vs. Time (Year) Fig. 4. Plot shows number of cores present in compared CPU designs. Metrics covered analyzed in this paper: CPU clock rate (MHz) vs. Year Memory Capacity (MB) vs. Year Number of Processors or Cores vs. Year Data bus Word Width (bits) vs. Year Fig. 1. These metrics were used to study each of the ten processor systems by evaluating varying performance over time. Page 3 of 5

4 Data Bus Word Width (bits) vs. Time (Year) Fig. 5. Plot shows exponential growth of CPU data bus length over time. IV. CONCLUSION This project set out to display the validity of Moore's Law using ten processor architectures (five baseline systems and five non-baseline). Overall, the findings were agreeable, as especially observed by the comparable clock rates of each system, seen in Figure 2. Other metrics weren't as reliable in expressing Moore's Law, but this was largely due to the types of example architecture systems used. Rather than select ten general purpose desktop to compare in succession, a wide arrange of architectures designed for different purposes. Some systems didn't chart well in the metric graphs because they were lower profile than systems before them, and had less operating cores with lower memory capacity. This isn't to say that Moore's Law can't be applied, but that certain architecture systems only require a certain amount of specifications to complete their purposes. If more closely similar systems were studied, perhaps the findings would have been more noticeable. V. REFERENCES [1] H. A. Bahr and R. F. DeMara, "OTBSAF Scalability on Pentium III/4 and Athlon 64/XP3 Architectures," in MSIAC Modeling and Simulation Journal, on February 9, 25, Vol.6, No. 3, March, 25, pp [2] H. Bahr, R. F. DeMara, and M. Georgiopoulos, "Integer-Encoded Massively Parallel Processing of Fast-Learning ARTMAP Networks," in Proceedings of the 1997 SPIE AeroSense Symposium (AeroSense-97), pp , Orlando, Florida, U.S.A., April 21-24, [3] R. F. DeMara and D. I. Moldovan, "The SNAP-1 Parallel AI Prototype," IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 8, August, 1993, pp [4] J. Huang, M. Parris, J. Lee, and R. F. DeMara, "Scalable FPGA-based Architecture for DCT Computation Using Dynamic Partial Reconfiguration," ACM Transactions on Embedded Computing Systems, Vol. 9, No. 1, Art. 9, October, 29, pp [5] Hughes, C.; Tao Li, "Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis," Workload Characterization, 28. IISWC 28. IEEE International Symposium on, vol., no., pp.163,172, Sept. 28. [6] Rusu, S.; Simon Tam; Muljono, H.; Stinson, J.; Ayers, D.; Chang, Jonathan; Varada, R.; Ratta, M.; Kottapalli, S.; Vora, S., "A 45 nm 8- Core Enterprise Xeon Processor," Solid-State Circuits, IEEE Journal of, vol.45, no.1, pp.7,14, Jan. 21. [7] Howard, J.; Dighe, S.; Vangal, S.R.; Ruhl, G.; Borkar, N.; Jain, S.; Erraguntla, V.; Konow, M.; Riepen, M.; Gries, M.; Droege, G.; Lund- Larsen, T.; Steibl, S.; Borkar, S.; De, V.K.; Van Der Wijngaart, R., "A 48-Core IA- Processor in 45 nm CMOS Using On-Die Message- Passing and DVFS for Performance and Power Scaling," Solid-State Circuits, IEEE Journal of, vol.46, no.1, pp.173,183, Jan [8] Kahng, A.B.; Seokhyeong Kang; Kumar, R.; Sartori, J., "Designing a processor from the ground up to allow voltage/reliability tradeoffs," High Performance Computer Architecture (HPCA), 21 IEEE 16th International Symposium on, vol., no., pp.1,11, 9-14 Jan. 21. [9] Zheng Yu; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng, "Low- Power Multicore Processor Design With Reconfigurable Same- Instruction Multiple Process," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.61, no.6, pp.423,427, June 214. [1] Shute, G., "Components of a Computer," Computer Components, June 214 University of Minnesota Duluth, August 215. TABLE I. SPECIFICATIONS FOR TEN CPU ARCHITECTURES STUDIED IN PROJECT Name of Architecture [reference] SNAP-1 Parallel AI Prototype [3] Intel Pentium III Processor System [1] AMD Athlon 24+ Processor System [1] Xilinx Virtex-4 SX35 FPGA-Based Scalable Architecture [4] MasPar MP-1 Model 128 Back End [2] Xeon EX Processor System [6] : Application- Specific or -purpose Computation NLU: Special DCT Computation: Special Highly Parallel Architecture: Special Die Area, Number of Transistors, or Number of Chips/Boards/etc. 144 DSP Chips on 8 large circuit boards Computer System utilizing 18 Computer System utilizing Distinct HW arrangements and gate count of clusters of PEs, holding bit 8 dual-threaded 64- bit cores, each with CPU Clock Rate (MHz) Memory Capacity (MB) U* MB U* MB U* MB 2.3MB/CP U* 8 CPU = 184 MB 16KB/CPU * 8192 CPU = MB 24MB/CPU * 8 Data Bus Word Width (bits) 64 Number of Cores or CPUs 144 single core CPUs = 144 cores 18 single core CPUs = 18 cores 256 single core CPUs = 256 cores 8 single core CPUs = 8 cores 8192 single core CPUs = 8192 cores 8 dual-threaded CPUs = 8 cores Ideal Speedup for 99% parallel code (ignoring overheads) 144 cores so Told/Tnew= 1/(.1+ (.99/144)) = fold 1 1/(.1+ (.99/18)) = fold 256 cores so Told/Tnew= 1/(.1+ (.99/256)) = fold 1/(.1+ (.99/8)) = fold 8192 cores so Told/Tnew = 1/(.1+ (.99/8192)) = fold 1/(.1+ (.99/8)) = Page 4 of 5

5 Name of Architecture [reference] LTE MIMO Processor SIMT Architecture [9] IA 2D-Mesh Network- On-Chip Architecture [7] Experimental Intel Core 2 Quad Machine [5] OpenSPARC T1 CPU Microarchitecture [8] : Application- Specific or -purpose Computation Die Area, Number of Transistors, or Number of Chips/Boards/etc. CPU Clock Rate (MHz) Memory Capacity (MB) Data Bus Word Width (bits) Number of Cores or CPUs Ideal Speedup for 99% parallel code (ignoring overheads) 2.3 B transistors 192 MB 7.48-fold RSIMP Approach: Special Message Passing: Special Workload Synthesis and Statistical Modeling: Special 16-core processor, each 4core-4wide 48 integrated CPUs, with 1.3 B total transistors 4 homogeneous dual cores, with shared L2 caches 8 CPU cores, with each being 4-way multithreaded KB/CPU * MB U* 48 CPU = MB 4.1GB/CPU * 8.77 MB 3.19MB/CP U* MB 16 quad core CPUs = 64 cores 48 single core CPUs = 48 cores 4 dual core CPUs = 8 cores 8 single core CPUs = 8 cores 64 cores so Told/Tnew= 1/(.1+ (.99/64)) = fold 4 1/(.1+ (.99/48)) =.65-fold 1/(.1+ (.99/8)) = 7.48-fold 1/(.1+ (.99/8)) = 7.48-fold Page 5 of 5