VLSI Design Automation. Maurizio Palesi

Transcription

1 VLSI Design Automation 1

2 Outline Technology trends VLSI Design flow (an overview) 2

3 Outline Technology trends VLSI Design flow (an overview) 3

4 IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars, factories Network cards System-on-chip (SoC) 4

5 Integrated Circuit Revolution Geoffrey W.A. Dummer ( ) 1958: First integrated circuit (germanium) Built by Jack Kilby at Texas Instruments: Contained five components: transistors, resistors, and capacitors Robert Noyce ( ) Jack Kilby ( ) 5

6 Integrated Circuit Revolution Federico Faggin (1941-) 1972: Intel 4004 Microprocessor Clock speed: 108 KHz # Transistors: 2,300 # I/O pins: 16 Technology: 10μm 6

7 Integrated Circuit Revolution 2000: Intel Pentium 4 Processor Clock speed: 1.5 GHz # Transistors: 42 million Technology: 0.18μm CMOS 7

8 Integrated Circuit Revolution 2006: Intel Core 2 Duo Clock speed: 3.73 GHz # Transistors: 1 billion Technology: 65nm CMOS 8

9 Integrated Circuit Revolution 2005: Sun UltraSpartc T1 8 cores, 4 threads per core Clock speed: 1.2 GHz # Transistors: 300 million Technology: 90nm CMOS 9

10 Moore s Law Gordon Moore predicted in 1965 that the number of transistors that can be integrated on a die would double every 18 months. 10

11 Semiconductor Growth 11

12 What Makes it Happen 12

13 Processor Power (Watts) 13

14 Intel Microprocessor Performance 14

15 Device and Context Complexity Exponential increase in device complexity More complex system contexts System contexts in which devices are deployed (e.g. cellular radio) are increasing in complexity Complexity Increasing with Moore's law (or faster)! Require exponential increases in design productivity We have exponentially more transistors! 15

16 Deep Submicron Effects Cross-coupled capacitances Signal integrity Resistance Inductance DSM Effects Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: Design of each transistor is getting more difficult! 16

17 Heterogeneity on Chip Greater diversity of onchip elements Processors Software Memory Analog Heterogeneity More transistors doing different things! 17

18 Stronger Market Pressures Decreasing design window Less tolerance for design revisions Time-to-market 18

19 A Quadruple Complexity Time-to-market Heterogeneity DSM Effects Exponentially more complex, greater design risk, greater variety, and a smaller design window! 19

20 How Are We Doing? 58% / Yr. compound complexity growth rate 100,000 10,000 1,000 ic g Lo./C r T hip 100,000,000 10,000,000 1,000, ,000 Productivity gap.m S /. r T 10,000 1, % / Yr. compound productivity growth rate Productivity Trans. / Staff. Month 1,000, Logic transistors per chip (K) 10,000,000 Role of EDA: close the productivity gap 20

21 Evolution of Design Methodology We are now entering the era of block-based design ASIC/ASSP Design Yesterday Bus Standards, Predictable, Preverified /Block Authoring Today VSI Compatible Standards, Predictable, Preverified System Board Integration System Chip Integration 21

22 Trends A inexpensive 200mm2 die has 75M logic transistors, or 375M SRAM transistors A 1000mm2 die would have 400M logic transistors Core Trans. Count 486DX4 0.7 million Pentium/MMX 2.8 million MPEG-2 encoder 1.5 million MPEG-2 decoder 0.5 million 8051 microcontroller 0.05 million Up to microcontrollers on a single chip! cores on a single chip Pentium/MMX 22

23 Evolution of SoC Platforms General-purpose Scalable RISC Processor 50 to 300+ MHz 32-bit or 64-bit Library of Device Blocks Image coprocessors DSPs UART 1394 USB Scalable VLIW Media Processor: 100 to 300+ MHz 32-bit or 64-bit Nexperia System Buses bit 2 Cores: Philips Nexperia PNX8850 SoC platform for High-end digital video (2001) 23

24 Running Forward Four 350/400 MHz StarCore SC140 DSP extended cores 16 ALUs: 5600/6400 MMACS 1436 KB of internal SRAM & multilevel memory hierarchy Internal DMA controller supports 16 TDM unidirectional channels, Two internal coprocesssors (TCOP and VCOP) to provide specialpurpose processing capability in parallel with the core processors 6 Cores: Motorola s MSC8126 SoC platform for 3G base stations (late 2003) 24

25 What s Happening in SoCs? Technology: no slow-down in sight! Faster and smaller transistors: nm but slower wires, lower voltage, more noise! 80% or more of the delay of critical paths will be due to interconnects Design complexity: from 2 to 10 to 100 cores! Design reuse is essential but differentiation/innovation is key for winning on the market! Performance and power: GOPS for MWs! Performance requirements keep going up but power budgets don t! 25

26 The Deep Submicron Effects 26

27 Communication Architectures Shared bus Low area Poor scalability High energy consumption Shared bus Network-on-Chip Scalability and modularity Low energy consumption Increase of design complexity 27

28 Intel s Teraflops 100 Million transistors 80 cores, 160 FP engines Teraflops 62 Watts On-die mesh network Power aware design 28

29 Terascale vs. ASCI RED ASCI Red the first computer to reach a Teraflops of processing (1996) 10, MHz 500kW of power (+500kW to keep the room cool) Terascale the first on-chip solution reaching Teraflop of processing (2006) 80 core chip (VLIW based) GHz 62W-256W 29

30 Outline Technology trends VLSI Design flow (an overview) 30

31 IC Design Steps Specifications High-level Description Functional Description Behavioral VHDL, C Structural VHDL 31

32 IC Design Steps High-level Description Specifications Functional Description Synthesis Physical Design Placed & Routed Design Packaging Technology Mapping Gate-level Design Fabrication Logic Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) 32

33 Circuit Models A model of a circuit is an abstraction A representation that shows relevant features without associated details Circuit Model (few details) Synthesis Circuit Model (many details) 33

34 Model Classification 34

35 Levels of Abstraction Architectural A circuit performs a set of operation, such as data computation or transfer HDL models, Flow diagrams, Logic A circuit evaluate a set of logic functions FSMs, Schematics, Geometrical A circuit is a set of geometrical entities Floor plans, layouts,... 35

36 Levels of Abstraction PC = PC + 1; Fetch(PC); Decode(Inst);... Design consists of refining the abstract specification of the architectural model into the detailed geometricallevel model 36

37 Views of a Model Behavioral Describe the function of a circuit regardless of its implementation Structural Describe a model as an interconnection of components Physical Relate to the physical object (e.g., transistors) of a design 37

38 The Y-chart Structural-view Behavioral-view Architectural-level Logic-level Geometrical-level Physical-view Gajski and Kuhn s Y-chart (Silicon Compilers, Addison-Wesley, 1987) 38

39 The Y-chart Structural-view Behavioral-view PC = PC + 1; Fetch(PC); Decode(Inst);... MULT CTRL ADD Architectural level RAM S0 S3 Logic level S1 S2 Geometrical level Physical-view 39

40 Synthesis Behavioral-view High-level synthesis (or architectural synthesis) Structural-view Assignment to resources Interconnection Scheduling Architectural-level Logic synthesis Interconnection of istances of library cells (technology mapping) Logic-level Physical design Physical layout of the chip (placement, routing) Geometrical-level Physical-view 40