Kirill Rogozhin. Intel

Transcription

1 Kirill Rogozhin Intel

2 From Old HPC principle to modern performance model Old HPC principles: 1. Balance principle (e.g. Kung 1986) hw and software parameters altogether 2. Compute Density, intensity, machine balance - (FLOP/byte or Byte/FLOP ratio for algorithm or hardware). E.g. Kennedy, Carr: 1988, 1994: Improving the Ratio of Memory operations to Floating-Point Operations in Loops. More research catalyzed by memory wall/ gap growth and by GPGPU , Berkeley: generalized into Roofline Performance Model. Williams, Waterman, Patterson. Roofline: an insightful visual performance model for multicore : Cache-aware Roofline model: Ilic, Pratas, Sousa. INESC-ID/IST, Technical Uni of Lisbon. Intel Confidential 2

3 Memory Wall Patterson, 2011 Intel Confidential 3

4 From Old HPC principle to modern performance model Old HPC principles: 1. Balance principle (e.g. Kung 1986) hw and software parameters altogether 2. Compute Density, intensity, machine balance - (FLOP/byte or Byte/FLOP ratio for algorithm). E.g. Kennedy, Carr: 1988, 1994: Improving the Ratio of Memory operations to Floating-Point Operations in Loops. More research catalyzed by memory wall/ gap growth and by GPGPU: , Berkeley: generalized into Roofline Performance Model. Williams, Waterman, Patterson. Roofline: an insightful visual performance model for multicore : Cache-aware Roofline model: Ilic, Pratas, Sousa. INESC-ID/IST, Technical Uni of Lisbon. Intel Confidential 4

5 Density, Intensity, Machine balance Arithmetic Intensity = Total Flops computed Total Bytes transferred WIP OI Arithmetic Operational Intensity = Total Flops computed Total Bytes transferred between DRAM (MCDRAM) and LLC Implemented in 2017 Update 1 WIP AI Arithmetic Intensity = Total Flops computed Total Bytes transferred between CPU and memory Arithmetic Intensity = Total Intops+Flops computed Total Bytes transferred between CPU and memory 5

6 Agenda - Roofline origins - Roofline as a visual performance model - Roofline: under the hood - Cache-aware vs. Traditional Roofline - Roofline interpretation - Customer adoption. Internal and external collaboration. Next Steps. - Customer use cases. Value proposition. Intel Confidential 6

7 Attainable Performance (Gflops/s) Roofline [1] is a visual performance model NERSC+Intel, Intel HPC Dev Conf 17 Arithmetic Intensity (flops/byte) Computation Limit Roofline is a visually intuitive performance model used to bound the performance of various numerical methods and operations running on multicore, manycore, or accelerator processor architectures

8 Roofline Automation in Intel Advisor Each Roof (slope) Gives peak CPU/Memory throughput of your PLATFORM (benchmarked) Each Dot represents loop or function in YOUR APPLICATION (profiled) Interactive mapping to source and performance profile Synergy between Vector Advisor and Roofline: FMA example Customizable chart 8

9 Roofline model: Am I bound by VPU/CPU or by Memory? A B C What makes loops A, B, C different? 9

10 Advisor Roofline: under the hood Seconds User-mode sampling Root access not needed Roofline application profile: Axis Y: FLOP/S = #FLOP (mask aware) / #Seconds Axis X: AI = #FLOP / #Bytes Roofs Microbenchmarks Actual peak for the current configuration Performance = Flops/seconds #FLOP Binary Instrumentation Does not rely on CPU counters AI = Flop/byte Bytes Binary Instrumentation Counts operands size (not cachelines) 10

11 Getting Roofline in Advisor FLOP/S = #FLOP/Seconds Step 1: Survey - Non intrusive. Representative - Output: Seconds (+much more) Step 2: FLOPS - Precise, instrumentation based - Physically count Num-Instructions - Output: #FLOP, #Bytes Seconds #FLOP Count - Mask Utilization - #Bytes Intel Confidential 11

12 Mask Utilization and FLOPS profiler 12

13 Why Mask Utilization Important? for(i = 0; i <= MAX; i++) c[i] = a[i] + b[i]; 100% a[i] + b[i] a[i+7] a[i+6] a[i+5] a[i+4] a[i+3] a[i+2] a[i+1] a[i] b[i+7] b[i+6] b[i+5] b[i+4] b[i+3] b[i+2] b[i+1] b[i] + c[i] c[i+7] c[i+6] c[i+5] c[i+4] c[i+3] c[i+2] c[i+1] c[i] 13

14 Why Mask Utilization Important? 3 elements suppressed for(i = 0; i <= MAX; i++) if (cond(i)) c[i] = a[i] + b[i]; SIMD Utilization = 5/8 cond[i] % a[i] + b[i] a[i+7] a[i+6] a[i+5] a[i+4] a[i+3] a[i+2] a[i+1] a[i] b[i+7] b[i+6] b[i+5] b[i+4] b[i+3] b[i+2] b[i+1] b[i] + c[i] c[i+7] c[i+6] c[i+5] c[i+4] c[i+3] c[i+2] c[i+1] c[i] 14

15 AVX-512 Mask Registers 8 Mask registers of size 64-bits k1-k7 can be used for predication k0 can be used as a destination or source for mask manipulation operations 4 different mask granularities. For instance, at 512b: Packed Integer Byte use mask bits [63:0] VPADDB zmm1 {k1}, zmm2, zmm3 Packed Integer Word use mask bits [31:0] VPADDW zmm1 {k1}, zmm2, zmm3 Packed IEEE FP32 and Integer Dword use mask bits [15:0] VADDPS zmm1 {k1}, zmm2, zmm3 Packed IEEE FP64 and Integer Qword use mask bits [7:0] VADDPD zmm1 {k1}, zmm2, zmm3 zmm1 zmm2 zmm3 k1 zmm1 element size VADDPD zmm1 {k1}, zmm2, zmm3 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c b7+c7 a6 b5+c5 b4+c4 b3+c3 b2+c2 a1 a0 Vector Length Byte Word Dw ord/sp Qw ord/dp 2 4 8

16 Survey+FLOPs Report on AVX-512: FLOP/s, Bytes and AI, Masks and Efficiency Intel Confidential 16

17 General efficiency (FLOPS) vs. VPU-centric efficiency (Vector Efficiency) High Vector Efficiency Low FLOPS Low Vector Efficiency High FLOPS Intel Confidential 17

18 Cache-Aware vs. Classic Roofline AI = # FLOP / # BYTE Classic Roofline: Intensity defined as # FLOP/ # BYTES (Cache DRAM) - DRAM traffic (or MCDRAM-traffic-based) - Variable for the same code/platform (varies with dataset size/trip count) - Can be measured relative to different memory hierarchy levels cache level, HBM, DRAM Cache-aware Roofline: Intensity defined as # FLOP / # BYTES (CPU Memory Sub-system) - Algorithmic, Cumulative (L1+L2+LLC+DRAM) traffic-based - Invariant for the given code / platform combination - Typically AI_CARM < AI_DRAM 18

19 Attainable Performance (Gflops/s) The Cache-Aware Roofline Model NERSC+Intel, Intel HPC Dev Conf 17 CPU Limit FMA+SIMD CPU Limit FMA CPU Limit Scalar Unroll CPU Limit Scalar Total volume of bytes transferred across all memory hierarchies to the core: Attainable perf Gflops/s = min Peak performace Gflops/s Bandwidths to Core Operational x Intensity Operational Intensity (flops/byte) Bandwidths to Core Bandwidth from L1 to Core Bandwidth from L2 to Core Bandwidth from L3 to Core Bandwidth from DRAM to Core [1] S. Williams et al. CACM (2009), crd.lbl.gov/departments/computer-science/par/research/roofline

20 Attainable Performance (Gflops/s) Attainable Performance (Gflops/s) Example 1: Effect of L2 Cache Optimization NERSC+Intel, Intel HPC Dev Conf 17 Classical roofline Cache-aware roofline FMA+SIMD FMA+SIMD FMA Scalar FMA Scalar Reducing dataset to fit into L2 Reducing dataset to fit into L2 Operational Intensity (flops/byte) We are L2 bandwidth bound, clearly shown by the cache-aware roofline Arithmetic/Operational Intensity (flops/byte)

21 Attainable Performance (Gflops/s) Attainable Performance (Gflops/s) Example 2: Compute Bound Application NERSC+Intel, Intel HPC Dev Conf 17 Classical roofline Cache-aware roofline FMA+SIMD FMA+SIMD FMA Scalar FMA Scalar Operational Intensity (flops/byte) Effect of vectorization/fma: vertical increase in both models Arithmetic/Operational Intensity (flops/byte)

22 Interpreting Roofline Data: advanced ROI analysis. Final Limits (assuming perfect optimization) Long-term ROI, optimization strategy Current Limits (what are my current bottlenecks) Next step, optimization tactics Finally memory-bound Invest more into effective cache utilization Finally compute-bound Invest more into effective CPU/VPU (SIMD) optimization Check your Advisor Survey and MAP results 22

23 Acknowledgments/References Roofline model proposed by Williams, Waterman, Patterson: Cache-aware Roofline model: Upgrading the loft (Ilic, Pratas, Sousa, INESC-ID/IST, Thec Uni of Lisbon) At Intel: Roman Belenov, Zakhar Matveev, Julia Fedorova SSG product teams, Hugh Caffey, in collaboration with Philippe Thierry 23

24 Roofline model: value proposition 1. Sense of absolute performance when optimizing applications: How do I know if my performance is good? Why am I not getting peak performance of the platform? 2. Choose optimization direction (ROI, where to invest first): How do I know which optimization to apply? What is the limiting factor? How do I know when to stop? 3. The language for Perf Experts and Domain Experts to talk to each other 4. Lightweight projection and co-design tool(this is where it originated from)

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