SBC-K7. Datasheet. AmpliconBenelux.com. Embedded PC for Instrumentation and Control with Kintex7 FPGA core and configurable FMC IO DESCRIPTION

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1 V 0.1 8/10/11 Embedded PC for Instrumentation and Control with Kintex7 FPGA core and configurable FMC IO FEATURES Embedded PC Runs Windows/Linux i7 CPU, 4 cores, 2.2 GHz, 8-16 GB or Atom CPU, 1 or 2 cores, 1.6GHz, 2GB USB/1000 Ethernet/SATA/IEEE1588 Touchscreen LCD and DisplayPort support Removable SDHC boot drive Small and Low Power 6U card 200x160x30mm < 30W (Atom), 70W (i7) excluding FMC Conduction or Air-cooled versions FMC I/O site Dual VITA 57 module sites with 80 LVDS pairs x8 lanes, 6.5 Gbps (x4 shared w/ Ethernet) FPGA Computing Core Xilinx Kintex7 K160T, K325T, or K410T 2 memory banks: up to 1GB LPDDR2 DRAM or 8MB QDRII SRAM each Communications ports 10Gb Ethernet with SFP+ fiber optic port Wire Speed rates support 1GB/s streaming Timing Features IEEE 1588 timing synchronization Optional GPS integration Clock and trigger I/O for system timing Environmental ratings for -40 to 85C and 5g vibe APPLICATIONS Embedded instrumentation and controls Distributed sensor processing and networks Remote data recording SOFTWARE MATLAB/VHDL FrameWork Logic Microsoft and QT Creator C++ Tools Win 7/ Linux / VxWorks 6.x DESCRIPTION The is an ideal platform for embedded instrumentation that combines an Atom PC running Windows/Linux/VxWorks with a Xilinx Kintex7 FPGA and an industrycompliant FMC IO site (HPC) plus a second FMC-compatble (LPC) site. The CPU is a COM Express module featuring a single or dual core Intel Atom processor that is a fully compatible PC. The COM Express is optimized for low power, consuming only 6W, yet has Ethernet, USB, SATA, DisplayPort, touchscreen LCD, and PCI Express connectivity. The COM Express module is industry-standard, multisourced with a range of performance/power choices. The FPGA computing core features the Xilinx Kintex 7 FPGA family, from K160T to K410T. The K410T provides 1540 DSP MAC elements operating at up to 500 MHz and 400K logic cells. The FPGA core has two memory banks, each of which is either up to 1GB LPDDR2 DRAM or 8MB QDRII SRAM. FMC I/O site0 has 80 LVDS pairs connected to the FPGA, plus clocks, controls, and up to x8 6.5 Gbps lanes. Timing features include clock and trigger I/O for multi-card synchronization. GPS, IEEE 1588 PTP and IRIG-B timing references are integrated with on-card timing features for system-level timing coordination. Innovative offers a full line of FMC analog and digital IO modules or can be readily adapted to custom modules. For system communications the includes two, 1Gb Ethernet and 4x USB ports. The 1G Ethernet and USB ports provide instant connectivity to host PCs and networks. A USB client port also allows operation as a USB device. 10 Gb communications can be implemented via an available FMC. The 10Gb Ethernet port connects directly to the FPGA, providing sustained wire speed rates of ~1GB/s over a fiber optic connection. The is rugged and low power. Power consumption is ~20W (K160T FPGA) excluding FMC and operates from a 9-32V input. Air and conduction cooled versions are available rated for -40 to +85C, with up to 5 g vibration. The FPGA logic can be fully customized using VHDL/Verilog or Matlab using the the Frame Work Logic toolset. Real-time hardware-in-the-loop development using the graphical Simulink block diagrams is supported. IP cores for signal processing applications such down-conversion, demodulation and FFT are also available. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrate card use and features. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 09/10/12 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily include testing of all parameters.

2 ORDERING INFORMATION Product Part Number Description <er> Embedded PC with FMC IO site and FPGA core; Adlink nanox-tc-e680-2g (Intel Atom E680 processor at 1.6GHz with PCH EG20T and 2GB), Xilinx K160T FPGA -1 speed grade; 2 banks DRAM 1GB per bank. No FMC, GPS, SFP or SDHC drive included. <ER> is environmental rating (see following table) ** For alternate FPGAs or speed grades (K325T, K410T, contact sales) <er> Embedded PC with FMC IO site and FPGA core; Kontron i7 quad-core IvyBridge CPU, Xilinx K160T FPGA -1 speed grade; 2 banks DRAM 8GB per bank. No FMC, GPS, SFP or SDHC drive included. <ER> is environmental rating (see following table) ** For alternate FPGAs or speed grades (K325T, K410T, contact sales) FrameWork Logic FrameWork Logic board support package for RTL and MATLAB. Includes technical support for one year. Check with sales for specific FMC support. Software Malibu software installation DVD including drivers for Windows and Linux.

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5 Operating Environment Ratings The and FMC modules are available for rugged applications. The cards are 100% tested for operation over the specified range. Environment Rating <ER> L0 L1 L2 L3 Environment Office, controlled lab Outdoor, stationary Industrial Vehicles Applications Lab instruments, research Outdoor monitoring and controls Industrial applications with moderate vibration Manned vehicles Cooling Forced Air Forced Air Conduction Conduction Operating Temperature 0 to +50C -40 to +85C -20 to +65C -40 to +70C Storage Temperature -20 to +90C -40 to +100C -40 to +100C -40 to +100C Vibration Sine - - 2g Hz Random g 2 /Hz Hz 5g Hz 0.1 g 2 /Hz Hz Shock g, 11 ms 30g, 11 ms Humidity 0 to 95%, non-condensing 0 to 100% 0 to 100% 0 to 100% Conformal coating Conformal coating Conformal coating, extended temperature range devices Conformal coating, extended temperature range devices, Thermal conduction assembly Testing Functional, Temperature cycling Functional, Temperature cycling, Wide temperature testing Functional, Temperature cycling, Wide temperature testing Vibration, Shock Functional, Temperature cycling, Wide temperature testing Vibration, Shock Minimum lot sizes and NRE charges may apply. Contact sales support for pricing and availability.

6 Standard Features FMC Site FPGA Memories 2 Banks Total: each configurable as DRAM or SRAM Specification High Speed Pairs VITA 57 FMC 4 or 8 lanes (Tx/Rx pair) 6.5 Gbps max rate 4 lanes are shared with 10G Ethernet port LPDDR2 DRAM LPDDR2: 64Mx32 (options to 256Mx32) 333 MHz clock rate (up to 500 MHz) 4 GB/s sustained transfer rate (sequential read/writes using 500 MHz clock) Signal Pairs IO Standards 80 pairs total LA: 34 pairs (Vcco = 2.5V, Vref from FMC) HA: 24 pairs (Vcco = 2.5V, Vref from FMC) HB: 22 pairs (Vcco and Vref from FMC) LA, HA : LVCMOS25, LVDS25, LVDCI2, SSTL25, HSTL25 HB: all Kintex7 IO standards supported QDRII+ SRAM FPGA IO Interfaces 2Mx18 (Options to 8Mx18) 333 MHz clock rate (standard device speed is rated for 400MHz, options up to 500 MHz) 4 GB/s sustained transfer rate (simultaneous read/writes using 500 MHz clock) Power (available to module) 3A 1A 3.3V 0.5A Vadj = 4A 10Gb Ethernet ~1GB/s transfer rates XAUI 3.125Gbps interface to FPGA SFP+ port supports fiber optic cable Loopback and BIST modes FPGA Device Xilinx Kintex 7 Speed Grades -1, -2 DIO Bits 32, arranged as 16 pairs LVCMOS (2.5V) LVDS25 Sizes Flip-Flops /Slices DSP48E1 elements/ BlockRAMs GTX Ports K160T = ~ 47.5M gates equivalent K325T = ~ 24M gates equivalent K410T = ~ 55M gates equivalent K160T: 202K /25K K325T: 407K /50K K410T: 508K /63K K160T: 600 K325T: 840 K410T: 1540 x8 lanes total: x4 lanes FMC or 10Gb Ethernet x4 6.5 Gbps to FMC Configuration JTAG or SelectMap load from CPU

7 COM Express CPU and Site Standards PCIMG COM.0 R2.0 COM Express Type 6 Size Verified Modules Supports 84 x 55 mm module (ultra size) CEQM77HDE Core i7-3612qe, 2.1 GHz, 4 Core, 6M Cache, HDG3000, TPM, ECC, -40c to +85C Adlink nanox-tc-e680-2g (L0 environment) Adlink nanox-tc-e680t-2g (L2-L3 environments) Sample Clocks and Triggering Clock Sources Trigger Sources Timing Synchronization 2 SMA for FMC clocks 1 SMA for clock to FPGA 2 LVDS outputs (SATA-style connector) 2 LVDS inputs (SATA-style connector) 2 multi-drop LVDS pairs 2 open-collector flags IDC10 connector, 2mm CPU Types COM Express Memory BIOS Intel i7 processor at 2.1 GHz (Highest Performance) Intel Atom E680 processor at 1.6GHz with PCH EG20T (Dual core CPU, medium performance) Intel Atom E620 processor at 600 MHz with PCH EG20T (Single core, lowest power/performance) 8 GB (Kontron), soldered down, 6M cache 2GB (ADLink), soldered down, 512KB Cache AMI UEFI GPS (option) IEEE 1588 PTP (option) 10MHz reference disciplined to GPS PPS timing reference input Position and UTC time reporting Support for Trimble Mini-T 10MHz disciplined to PTP reference PPS timing reference input Software stack runs on CPU Timing resolution to <100 ns PC Peripherals Power USB 2 host ports, USB client port, USB 2.0 Ethernet Two ports, 10/100/1000 IEEE 1588 Precision Timing Protocol on port 1 RJ-45 Cu interfaces Consumption Temperature Monitor 10W baseline power 200 MHz clock rate; LPDDR2 memory, no 10GbE interface) Software with programmable alarms Over-temperature protection SATA Video/Audio CAN 2 esata 3 Gbps Integrated graphics engine on Atom DisplayPort video port with HD audio AX/RX port Power Control Cooling LPDDR2 deep sleep mode QDR shutdown FMC power controls Conduction or air-cooled GPS Port UART to GPS Storage SDHC boot drive; removable Physicals Touchscreen (optional) Watchdog Timer Temperature Monitor LVDS panel support with I2C/USB touch controller Resolution up to 60Hz 18 or 24-bit pixel color depths Optionally resets CPU CPU monitor and independent system monitoring Over-temperature shutdown Form Factor Hazardous Materials 3U Eurocard 160 x 100 mm (4.92x3.94 in) 30mm height (1.18 in) (excludes LCD panel) Lead-free and RoHS compliant

8 Architecture and Features The is an embedded PC that integrates a Xilinx Kintex7 FPGA computing core with a pair of FMC IO modules on a 6U card. The embedded PC runs Windows, Linux or VxWorks, just like a desktop PC. The architecture tightly couples the FPGA to the FMC and enables the card to perform realtime signal processing with low latency and extremely high rates, while providing all the ease-of-use and convenience of a PC. For real-time communications, the card has a 10Gb Ethernet port that sustains transfer rates up to 1 GB/s. Embedded PC The has a Type 6 COM Express CPU module with Intel Atom processor. This industry-standard CPU module runs same applications as a desktop computer, and is completely PC compatible. The i7 version is quad core, 2.1 GHz with 8 GB RAM. The Atom is single or dual core, up to 1.6 GHz with 2 GB DRAM. The modularity of the COM Express module allows the to be configured for the performance and power that is right for the application. When newer processors are available or system requirements change, the COM Express module can be changed without changing the system architecture or software. Leveraging this industry standard also means that there are many vendors and varieties to choose from. The provides familiar PC interfaces for expansion and connectivity: Gigabit Ethernet, USB ports, and SATA HDD. An integrated SDHC Solid State Drive (SSD) provides rugged, low power storage for the boot image and is removable for secure applications. The may also be booted from USB or Ethernet. One of the USB ports is a client port, allowing the to act as a USB peripheral. Dual esata ports provide expansion to additional SSD or HDD for data storage. The operates either headless for embedded applications or supports a monitor, keyboard and mouse over the USB and DisplayPort. Support for touchscreen LCD panel makes standalone instruments easier to use while leveraging the PC development environment. The CPU core connects to the FPGA over a x8 PCI Express link. This link supports up to ~3200 MB/s sustained transfer rates and is used as the primary data path between the CPU and FPGA. Software and firmware support high speed DMA transfers to the CPU, enabling data logging and signal processing on the CPU. FMC Module COM Express Advantages - PC core on a 55x85 mm module - Runs Windows, Linux, VxWorks - Scalable performance - PCI Express, Gb Ethernet, USB 2.0, SATA ports - Upgradeable as requirements change and evolve - Low power: 3 to 5 W - Industry-standard, multi-vendor The FMC module is a VITA57-compliant site for IO or system expansion. The FMC directly connects to the FPGA with 80 pairs of LVDS (160 single-ended) and 4 lanes of high speed serial. The serial lanes connect to the FPGA GTX ports.

9 FMC modules are integrated with the by including application logic in the FPGA. The flexible nature of the FMC interface is also useful for custom application-specific where the pin use and interface are defined by the application logic. Clocks and Triggers Clock and trigger sharing features support integration with multiple cards for simultaneous or coordinated sampling. Simple inter-card connections support trigger sharing through two LVDS inputs and two LVDS outputs. These trigger signals are on SATA-style connectors and support speeds up to 1 GHz. Remote systems are coordinated and synchronized Example epc-k7 Architecture using either GPS or IEEE 1588 Precision Time Protocol (PTP) timing references. Both GPS and network PTP interfaces provide reference clocks so that on-card is synchronized with GPS or network time. The third 1Gb Ethernet port has special features for timing synchronization over Ethernet using IEEE 1588 PTP and a software stack on the CPU. The GPS port provides integration support for Trimble Mini-T and other GPS units, allowing sample clocks and timing to be referenced to GPS time. FPGA Core The family has a Kintex7 FPGA and memory at its core for DSP and control. The completely flexible architecture of FPGAs supports fully parallel processing, delivering DSP performance of over 1 Tera MACs using the K410T operating at 500 MHz. In addition to the raw processing power, the FPGA fabric integrates logic, memory and connectivity features that make the capable performing very demanding real-time signal processing. The FPGA has direct access to two memory banks, each of which is either LPDDR2 DRAM or QDRII+ SRAM. These memories allow the FPGA working space for computation, required by DSP functions like FFTs, and bulk data storage needed for system data buffering and algorithms like large FFTs. Memory controller cores implement queuing, pattern generation, or flexible interfaces that supports their use for system data buffering and algorithm memory. The SRAMs provide the fastest random access to data, supporting transfer rates up to 4GB/s. The uses the Kintex7 FPGA as a system-on-chip to integrate all the features for highest performance. As such, all IO, memory and host interfaces connect directly to the FPGA providing direct connection to the data and control for maximum flexibility and performance. Firmware for the FPGA completely defines the data flow, signal processing, controls and host interfaces, allowing complete customization of the functionality. 10Gb Ethernet Communications FMC Data flows between the IO and the host using a packet system Packetizer Timestamp Data Buffer 1GB Router The can utilize an FMC module in site 1 which features a 10Gb Ethernet port as a high speed data pipe. The port provides over 1 GB/S sustained data transfer rates over a fiber optic link, allowing the to integrate with high speed data networks for sensors and other instruments. A 10Gb Ethernet MAC interface using UDP protocol in the FPGA supports continuous line-rate transfers, streaming data to the network. Long or short reach fiber optic connections are supported through the SFP+ port. SFP+ module is sold separately. PCIe Intf 10Gb Ethernet Gb Ethernet COM Ex CPU SFP+

10 Ethernet ports on the are integrated with the Velocia packet system. The packet system provides a simple and efficient way to move real-time data. It is extensible in your design to to efficiently handle data transfers between multiple, independent data sources on the and other cards. Data is packetized, using packet sizes from 32 bytes to 64MB per packet, stamped with a packet ID and destination, and then routed to other devices in the system. The Velocia packet system is completely defined by the logic firmware, giving complete flexibility to create any packet routing necessary to meet system latency and transfer rate requirements. Real-time system architectures using Velocia packet system for data flow management Dev PDN=0 Router 10GbE Dev PDN=0 CPU GbE Dev PDN=0 Router 10GbE Dev PDN=0 CPU GbE A set of logic components for packets is provided in the FrameWork Logic including packetizer, depacketizer, router and buffer memory controls. Packetizing includes timestamping per VITA 49. Data within the packets may be any format. Card Management Features The has power and health monitoring to protect from failures. Independent monitoring of the FPGA die temperature can shut down the card to prevent damage from overheating. The COM Express CPU also has independent temperature monitoring. The FPGA also has watchdog timer functionality that may be used to prevent runaway operation. FPGA Configuration 1GbE Network Example System Topology: nodes on 10G and 1G Ethernet networks 10GbE Network The FPGA is configured by the CPU. The CPU can reprogram the FPGA at any time. Configuration depends on the FPGA size; configuration is ~1 second for the K160T. During development, the JTAG interface to the FPGA is used for development tools such as ChipScope and MATLAB. This allows the FPGA image to be downloaded over the cable for debugging and test. The FPGA JTAG connector is compatible with Xilinx Platform USB Cable. Software Tools Software development tools provide comprehensive support including device drivers, data buffering, card controls, and utilities that allow developers to be productive from the start. At the most fundamental level, the software tools deliver data buffers to your application without the burden of low-level real-time control of the cards. Software classes provide C++ developers a powerful, high-level interface to the card that makes real-time, high speed data acquisition easier to integrate into applications. Software for data logging and analysis are provided that log data to disk or system memory. These applications demonstrate use of the hardware and software. Triggering and sample rate controls allow you to assess the module's performance in your applications without ever writing code. Innovative software applets include Binview which provides data viewing, analysis and import to MATLAB for large data files. Support for the Microsoft, Embarcadero and GNU C++ toolchains is provided. Supported OSes include VxWorks,Windows and Linux. Download the software tools User Guide and on-line help for more information.

11 Logic Tools High speed DSP, analysis, customized triggering and other unique features may be added by modifying the logic. The FrameWork Logic tools provide support for RTL and MATLAB developments, providing the basic hardware interfaces, data paths and controls. The standard logic provides a hardware interface layer that allows designers to concentrate on the applicationspecific portions of the design. Designer can build upon the Innovative components for packet handling, hardware interfaces and system functions, the Xilinx IP core library, and third party IP. RTL source for the FrameWork Logic is provided for customization. Each design is provided as a Xilinx ISE project, with a ModelSim testbench illustrating logic functionality. Using MATLAB Simulink for Logic Design The MATLAB Board Support Package (BSP) allows logic development using Simulink and Xilinx System Generator. These tools provide a graphical design environment that integrates the logic into MATLAB Simulink for complete hardware-in-theloop testing and development. This is an extremely power design methodology, since MATLAB can be used to generate, analyze and display the signals in the logic real-time in the system. Once the development is complete, the logic can be embedded in the FrameWork logic using the RTL tools. IP for Kintex7 FPGA Innovative provides many IP cores for signal processing functions such as up/down-conversion, modulation/demodulation, OFDM receiver and transmit to name a few. The DDC channelizers are offered in channel densities from 4 to 256. The four channel DDC offers complete flexibility and independence in the channels, while the 128 and 256 channel cores offer higher density for uniform channel width applications. The DDC cores are highly configurable and include programmable channel filters, decimation rates, tuning and gain controls. An integrated power meter allows the DDC to measure any channel power for AGC controls. Multiple cores can be used for higher channel counts. Each IP core is provided with a MATLAB simulation model that shows bit-true, cycle-true functionality. Signal processing designers can then use this model for channel design and performance studies. Filter coefficients and other parameters from the MATLAB simulation can be directly loaded to the hardware for verification. Part Number IP Core Channels Tuning Decimation Max Bandwidth Channel Filter IP-MDDC4 4 Fs/2^32 16 to Fs/16 Programmable 100 tap filter IP-MDDC Fs/2^ to Fs/512 Programmable 100 tap filter IP-DDC Fs/2^ to Fs/512 Programmable 100 tap filter

12 Signal processing cores for communications applications: Part Number IP Core Features PSK Demodulation N=2,4,8,PI/4. Integrated carrier tracking and bit decision. Data rate to 160 Mbps PSK Modulator N=2,4,8,PI/4. Data rates up to 160 Mbps FSK Demodulation Coherent demodulation with carrier recovery, FSK Modulator FSK modulation/ QAM Modulator Quadrature Amplitude Modulator TinyDDS Tiny DDS, 1/3 to ½ size of Xilinx DDS with equal SFDR, clock rates to 400 MHz with flow control XLFFT IP core for 64K to 1M FFTs with windowing functions Windowing IP core for Hann, Blackman and uniform data windowing functions CORDIC IP core for sine/cosine generation using CORDIC method, resulting in 1/3 logic size of standard DDS cores MDUC channel digital upconverter DUC Up-conversion with interpolation rates from 2-32K, programmable filters and tuning OFDM and LTE Cores OFDM Transmitter OFDM transmit with IFFT, Windowing, Filtering, Cyclic Prefix and Upsample OFDM Receiver OFDM receiver with synchronization, downconversion and channel filtering LTE Downlink Transmitter LTE downlink transmitter core for FDD mode LTE Uplink Receiver LTE uplink receiver core for FDD mode includes 2K FFT, timing and frame synchronization using ML estimation method, decoding of SSS and PSS signals for cell ID and frame sync.

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