Analog & Digital I/O

Transcription

1 Analog & Digital I/O

2 ANALOG & DIGITAL I/O MODEL DESCRIPTION Cobalt GHz and D/A, Virtex-6 - XMC Cobalt GHz and D/A, Virtex-6 - x8 Cobalt GHz and D/A, Virtex-6-3U VPX - Format 1 Cobalt GHz and D/A, Virtex-6-3U VPX - Format 2 Cobalt & /2-Ch 1 GHz and 1-/2-Ch 1 GHz D/A, Virtex-6-6U VPX Cobalt 72630, 73630, /2-Ch 1 GHz and 1-/2-Ch 1 GHz D/A, Virtex-6-6U/3U cpci Cobalt GHz and D/A, Virtex-6 - AMC Cobalt Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit, Virtex-6 - XMC Cobalt Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit, Virtex-6 - x8 Cobalt Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit, Virtex-6-3U VPX - Format 1 Cobalt Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit, Virtex-6-3U VPX - Format 2 Cobalt & /2-Ch 3.6 GHz or 2-/4-Ch 1.8 GHz 12-bit, Virtex-6-6U VPX Cobalt 72640, 73640, /2-Ch 3.6 GHz or 2-/4-Ch 1.8 GHz 12-bit, Virtex-6-6U/3U cpci Cobalt Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit, Virtex-6 - AMC Cobalt Channel 200 MHz, -bit, Virtex-6 - XMC Cobalt Channel 200 MHz, -bit, Virtex-6 - x8 Cobalt Channel 200 MHz, -bit, Virtex-6-3U VPX - Format 1 Cobalt Channel 200 MHz, -bit, Virtex-6-3U VPX - Format 2 Cobalt & /8-Channel 200 MHz, -bit, Virtex-6-6U VPX Cobalt 72660, 73660, /8-Channel 200 MHz, -bit, Virtex-6-6U/3U cpci Cobalt Channel 200 MHz, -bit, Virtex-6 - AMC Cobalt GSM Channelizer with Quad - XMC Cobalt GSM Channelizer with Quad - x8 Cobalt GSM Channelizer with Quad - 3U VPX - Format 1 Cobalt GSM Channelizer with Quad - 3U VPX - Format 2 Cobalt & /2200 GSM Channelizer with Quad/Octal - 6U VPX Cobalt 72663, 73663, /2200 GSM Channelizer with Quad/Octal - 6U/3U cpci Cobalt GSM Channelizer with Quad - AMC Cobalt Channel 1.25 GHz D/A with DUC, Virtex-6 - XMC Cobalt Channel 1.25 GHz D/A with DUC, Virtex-6 - x8 Cobalt Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX - Format 1 Cobalt Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX - Format 2 Cobalt & /8-Channel 1.25 GHz D/A with DUC, Virtex-6-6U VPX Cobalt 72670, 73670, /8-Channel 1.25 GHz D/A with DUC, Virtex-6-6U/3U cpci Cobalt Channel 1.25 GHz D/A with DUC, Virtex-6 - AMC Cobalt 790 L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - XMC Cobalt L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - x8 Cobalt L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX - Format 1 Cobalt L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX - Format 2 Last updated: January 2017 More on next page

3 ANALOG & DIGITAL I/O MODEL DESCRIPTION Cobalt & /2-Ch L-Band Tuner, 2-/4-Ch 200 MHz, Virtex-6-6U VPX Cobalt 72690, 73690, /2-Ch L-Band Tuner, 2-/4-Ch 200 MHz, Virtex-6-6U/3U cpci Cobalt L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - AMC Onyx Channel 200 MHz, -bit, Virtex-7 - XMC Onyx Channel 200 MHz, -bit, Virtex-7 - x8 Onyx Channel 200 MHz, -bit, Virtex-7-3U VPX - Format 1 Onyx Channel 200 MHz, -bit, Virtex-7-3U VPX - Format 2 Onyx & /8-Channel 200 MHz, -bit, Virtex-7-6U VPX Onyx 72760, 73760, /8-Channel 200 MHz, -bit, Virtex-7-6U/3U cpci Onyx 56760Onyx Channel 200 MHz, -bit, Virtex-7 - AMC Onyx GHz and D/A, Virtex-7 - XMC Onyx GHz and D/A, Virtex-7 - x8 Onyx GHz and D/A, Virtex-7-3U VPX - Format 1 Onyx GHz and D/A, Virtex-7-3U VPX - Format 2 Onyx & /2-Ch 1 GHz and 1-/2-Ch 1 GHz D/A, Virtex-7 s - 6U VPX Onyx 72730, 73730, /2-Ch 1 GHz and 1-/2-Ch 1 GHz D/A, Virtex-7 s - 6U/3U cpci Onyx GHz and D/A, Virtex-7 - AMC Onyx Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, DDC,Virtex-7 - XMC Onyx Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, DDC,Virtex-7 - x8 Onyx Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, DDC,Virtex-7-3U VPX - Format 1 Onyx Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, DDC,Virtex-7-3U VPX - Format 2 Onyx & /2-Ch. 3.6 GHz or 2/4-Ch. 1.8 GHz, 12-bit, DDC,Virtex-7-6U VPX Onyx 72741, 73741, /2-Ch. 3.6 GHz or 2/4-Ch. 1.8 GHz, 12-bit, DDC,Virtex-7-6U/3U cpci Onyx Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, DDC,Virtex-7 - AMC Cobalt 710 LVDS Digital I/O with Virtex-6 - XMC Cobalt LVDS Digital I/O with Virtex-6 - x8 Cobalt LVDS Digital I/O with Virtex-6-3U VPX - Format 1 Cobalt LVDS Digital I/O with Virtex-6-3U VPX - Format 2 Cobalt & Single or Dual LVDS Digital I/O with Virtex-6 s - 6U VPX Cobalt 72610, 73610, Single or Dual LVDS Digital I/O with Virtex-6 s - 6U/3U cpci Cobalt LVDS Digital I/O with Virtex-6 - AMC Cobalt 7811 Quad Serial FPDP Interface with Virtex-6 - x8 Cobalt 711 Quad Serial FPDP Interface with Virtex-6 - XMC Cobalt Quad Serial FPDP Interface with Virtex-6 - x8 Cobalt Quad Serial FPDP Interface with Virtex-6-3U VPX - Format 1 Cobalt Quad Serial FPDP Interface with Virtex-6-3U VPX - Format 2 Cobalt & Quad or Octal Serial FPDP Interface with Virtex-6 s - 6U VPX Cobalt 72611, 73611, Quad or Octal Serial FPDP Interface with Virtex-6 s - 6U/3U cpci Cobalt Quad Serial FPDP Interface with Virtex-6 - AMC Last updated: January 2017 More on next page

4 ANALOG & DIGITAL I/O MODEL DESCRIPTION Flexor 5973 Virtex-7 Processor and FMC Carrier - 3U VPX Flexor 7070 Virtex-7 Processor and FMC Carrier - x8 Flexor Channel 250 MHz, -bit, 2-Channel 800 MHz, -bit D/A - FMC FlexorSet Channel 250 MHz -bit, 2-Channel800 MHz -bit D/A - 3U VPX FlexorSet Channel 250 MHz -bit, 2-Channel800 MHz -bit D/A - x8 Flexor 33 8-Channel 250 MHz, -bit - FMC FlexorSet Channel 250 MHz -bit with Virtex-7-3U VPX FlexorSet Channel 250 MHz -bit with Virtex-7 - x8 Flexor Channel 3.0 GHz, 2-Channel 2.8 GHz D/A wth Virtex-7 - FMC FlexorSet Channel 3.0 GHz, 2-Channel 2.8 GHz D/A wth Virtex-7-3U VPX FlexorSet Channel 3.0 GHz, 2-Channel 2.8 GHz D/A wth Virtex-7 - x8 Flexor Channel 500 MHz, -bit, 4-Channel 1.5 GHz, -bit D/A - FMC FlexorSet Channel 500 MHz, -bit, 4-Channel 1.5 GHz, -bit D/A - 3U VPX FlexorSet Channel 500 MHz, -bit, 4-Channel 1.5 GHz, -bit D/A - x8 Bandit 7120 Two-Channel Analog Wideband Downconverter - PMC/XMC Bandit 7820 Two-Channel Analog Wideband Downconverter - Bandit 5220 Two-Channel Analog Wideband Downconverter - 3U VPX Bandit 5720 & 5820 Two- or Four-Channel Analog Wideband Downconverter - 6U OpenVPX Bandit 7220, 7320, 7420 Two- or Four-Channel Analog Wideband Downconverter - 6U/3U cpci Bandit 5620 Two-Channel Analog Wideband Downconverter - AMC Bandit 8111 Modular Analog Slot Downconverter Series U OpenVPX Development System for Cobalt and Onyx Boards 8266 PC Development System for Cobalt and Onyx Boards U VPX Development System for Cobalt, Onyx and Flexor Boards Cusmer Information Last updated: January 2017

5 Model GHz and 1 GHz D/A, Virtex-6 - XMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One 1 GHz 12-bit One 1 GHz -bit D/A Up 2 GB of or MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model 730 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and D/A converters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 730 includes optional general purpose and gigabit serial card connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The 730 facry-installed functions include an acquisition and a D/A waveform playback IP module. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the 730 operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with one 8X or two 4X gigabit links the support serial procols. In 1 GHz 12-BIT 12 VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB Out 1 GHz -BIT D/A 8X 4X 4X LVDS 40 Banks 1 & 2 Banks 3 & 4 option 155 option 5 QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 x8 P15 XMC Gigabit Serial I/O (option 105) P XMC GPIO (option 104) P14 PMC

6 Model 730 Acquisition IP Module The 730 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model 730 facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1 GHz and 1 GHz D/A, Virtex-6 - XMC Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The 730 features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 730 µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The 730 architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

7 Model GHz and 1 GHz D/A, Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-6 - XMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions XMC Interface The Model 730 complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up a 6 GHz bit clock. With dual XMC connecrs, the 730 supports x8 on the first XMC connecr leaving the second connecr free support userinstalled transfer procols specific the target application. PCI Express Interface The Model 730 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in PC Development System See 8266 Datasheet for Options

8 Model GHz and 1 GHz D/A with Virtex-6 - x8 Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One 1 GHz 12-bit One 1 GHz -bit D/A Up 2 GB of or MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and 1 GHz D/A converters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes optional general-purpose and gigabit serial card connecrs for application specific I/O procols. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. In 1 GHz 12-BIT Banks 1&2 Banks 3&4 option 155 option 5 12 VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB Out 1 GHz -BIT D/A LVDS 40 8X 4X 4X Optional GPIO 68-pin Header x8 x8 PCI Express Optional Serial I/O Dual 4X Serial Conn

9 Model GHz and 1 GHz D/A with Virtex-6 - x8 Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

10 Model GHz and 1 GHz D/A with Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-6 - x8 Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

11 Model GHz and D/A, Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora One 1 GHz 12-bit One 1 GHz -bit D/A Up 2 GB of or MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 1 GHz 12-BIT 12 Banks 1 & 2 Banks 3 & 4 option 155 option 5 VPX BACKPLANE Config FLASH 64 MB Out 1 GHz -BIT D/A VIRTEX-6 LX130T, LX240T or SX315T LVDS 40 Option -104 I/O VPX-P2 8X x8 Option -105 Gigabit Serial I/O CROSSBAR SWITCH 4X 4X 4X Gbit Gbit Gbit Serial Serial Serial VPX-P1 4X 4X 4X Gbit Serial

12 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1 GHz and D/A, Virtex-6-3U VPX Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 5392 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

13 Model GHz and D/A, Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

14 Model GHz and D/A, Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora One 1 GHz 12-bit One 1 GHz -bit D/A Up 2 GB of or MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock/Sync/ Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 1 GHz 12-BIT 12 Banks 1&2 Banks 3&4 option 155 option 5 Config FLASH 64 MB Out 1 GHz -BIT D/A VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE LVDS 40 Option -104 I/O VPX-P2 4X x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

15 Model GHz and D/A, Virtex-6-3U VPX Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 5292 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO

16 Model GHz and D/A, Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No 8267 VPX Development System. See 8267 Datasheet for Options

17 New! New! New! New! New! Models & Features Model Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One or two 1 GHz 12-bit One or two 1 GHz -bit D/A Up 2 or 4 GB of ; or: MB or 32 MB of QDRII+ SRAM PCI Express (Gen. 1 & 2) interface up x8 Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Ruggedized and conductioncooled versions available 1- or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 730 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 730 module while the Model is a 6U board with two XMC modules rather than one. These models include one or two 1 GHz and D/A converters and four or eight banks of memory The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition and one or two D/A waveform playback IP modules. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 Banks1&2 and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57630; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57630; or one 4X link from each P2 and an additional 4X link between the s, Model VIRTEX-6 LX130T, LX240T or SX315T QDRII+ SRAM 8MB In 1 GHz 12-BIT 12 QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks3&4 VPX BACKPLANE Config FLASH 64 MB Option -104 I/O LVDS VPX-P3 Out 1GHz -BIT D/A 40 8X Gen. 2 x8 Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58630

18 Models & or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6-6U OpenVPX 4630 Converter Stage Acquisition IP Module These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board memory or offboard host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 or 128 individual link entries can be chained gether create complex waveforms with a minimum of programming. The front end accepts one or two analog HF or IF inputs on front panel SSMC connecrs with transformer coupling in one or two Texas Instruments ADS GHz, 12-bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The 730 features one or two TI DAC5681Z 1 GHz, -bit D/As. The converters have an input sample rate of 1 GSPS, allowing them acept full rate data from the. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connecrs. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 9192 Cobalt Synchronizer can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

19 Models & or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6-6U OpenVPX 4630 Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A with Virtex-6-6U VPX Two 1 GHz and D/A, with two Virtex-6 s - 6U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57630; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57630; gigabit links from each P2 connecr, Model Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Model 57630: 1, 1 D/A Model 58630: 2 s, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connecrs Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus (1 or 2): 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57630; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57630; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

20 Models 72630, and or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6 - cpci Model Model General Information Models 72630, and are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 730 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 730 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one or two 1 GHz and D/A converters and four or eight banks of memory The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition and one or two D/A waveform playback IP module. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable these modles operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73630; J3 connecr, Model 72630; J3 and J5 connecrs, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One or two 1 GHz 12-bit One or two 1 GHz -bit D/A Up 2 or 4 GB of ; or: MB or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus MODEL INTEACES ONLY VIRTEX-6 LVDS TIMING BUS Clock / Sync / Gate / PPS 40 Optional PCI I/O BRIDGE (Option -104) J2 VCXO PCI/PCI-X BUS 32-bit, 33/66 MHz Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 In 1 GHz 12-BIT 12 Banks 1 & 2 Banks 3 & 4 option 155 option 5 Config FLASH 64 MB Out 1 GHz -BIT D/A VIRTEX-6 LX130T, LX240T or SX315T LVDS J3 40 Optional I/O (Option -104) x4 4X PCI BRIDGE From/To Other XMC Module of MODEL PCI PCI BRIDGE PCI/PCI-X BUS 32/64-bit, 33/66 MHz

21 Models 72630, and Acquisition IP Module These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board memory or offboard host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 or 128 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1- or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6 - cpci Converter Stage The front end accepts one or two analog HF or IF input on front panel SSMC connecrs with transformer coupling in one or two Texas Instruments ADS GHz, 12-bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The 730 features one or two TI DAC5681Z 1 GHz, -bit D/As. The converters have an input sample rate of 1 GSPS, allowing them acept full rate data from the. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connecrs. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7292 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 4X 40 I/O

22 Models 72630, and or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-6 - cpci Ordering Information GHz and D/A, Virtex-6-6U cpci GHz and D/A, Virtex-6-3U cpci Two 1 GHz and D/A, Virtex-6-6U cpci Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73630; J3 connecr, Model 72630; J3 and J5 connecrs, Model Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73630: 32 bits only. Specifications Model or Model 73630: 1, 1 D/A Model 74630: 2 s, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connecrs Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73630; J3 connecr, Model 72630; J3 and J5 connecrs, Model Banks (1 or 2) Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73630: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

23 Model GHz and 1 GHz D/A, Virtex-6 - AMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One 1 GHz 12-bit One 1 GHz -bit D/A Up 2 GB of or MB of QDRII+ SRAM Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance AMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and D/A converters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module. In addition, IP modules for either or QDRII+ Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 In 1 GHz 12-BIT Banks 1 & 2 Banks 3 & 4 option 155 option 5 memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. 12 VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB x8 AMC Ports 4 11 Out 1 GHz -BIT D/A 8X IPMI LER RS-232 Front Panel LVDS 40 GPIO (option 104) Front Panel

24 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1 GHz and 1 GHz D/A, Virtex-6 - AMC Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-6 FLOW DETAIL Bank 4 Bank 3 Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 5692 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 40 GPIO

25 Model GHz and 1 GHz D/A, Virtex-6 - AMC Ordering Information GHz and D/A, Virtex-6 - AMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through front panel connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Contact Pentek for availability of rugged and conduction-cooled versions

26 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - XMC Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 wide Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model 740 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 740 includes optional general purpose and gigabit serial connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The 740 facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus and a interface complete the facryinstalled functions and enable the 740 operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support other serial procols. 32 In 32 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB 8X 4X 4X LVDS 40 Banks1&2 Banks3&4 x8 Gigabit Serial I/O (option 105) GPIO (option 104) P15 XMC P XMC P14 PMC

27 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - XMC Acquisition IP Module The 740 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 740 have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization The 740 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connecr allows multiple modules be synchronized, ideal for larger multichanel VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 740s can be synchronized using the Cobalt high speed sync module drive the sync bus. Resources The 740 architecture supports four independent memory banks of. Each bank is deep and is an integral part of the module s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. XMC Interface The Model 740 complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up a 5 GHz bit clock. With dual XMC connecrs, the 740 supports x8 on the first XMC connecr leaving the optional second connecr free support user-installed transfer procols specific the target application. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO TEST SIGNAL LER Bank 3 Bank 4

28 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. PCI Express Interface The Model 740 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - XMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options

29 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6 - x8 Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes optional general-purpose and gigabit serial connecrs for application-specific I/O procols. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. 32 In 32 Banks 1&2 Banks 3&4 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB LVDS 40 8X 4X 4X Optional GPIO x8 Optional Serial I/O 68-pin Header Dual 4X Serial Conn x8 PCI Express

30 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6 - x8 Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connecr allows multiple boards be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78640s can be synchronized using the Cobalt high speed sync board drive the sync bus. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers and from the board. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO TEST SIGNAL LER Bank 3 Bank 4

31 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 XC6VSX315T-2 Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - x8 Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required 8266 PC Development System See 8266 Datasheet for Options

32 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Model COTS (left) and rugged version Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The includes a 3.6 GHz, 12-bit converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus Banks1&2 The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides dual 4X gigabit links between the and the VPX P1 connecr support serial procols. 32 In 32 Banks3&4 In VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE Config FLASH 64 MB 40 Option -104 I/O VPX-P2 8X x8 4X 4X Gbit Gbit Serial Serial Option -105 Gigabit Serial I/O CROSSBAR SWITCH VPX-P1 4X 4X Gbit Serial 4X 4X Gbit Serial

33 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connecr allows multiple boards be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple s can be synchronized using the Cobalt high-speed sync board drive the sync bus. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers and from the board. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO TEST SIGNAL LER Bank 3 Bank 4

34 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options

35 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Model COTS (left) and rugged version Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The includes a 3.6 GHz, 12-bit converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides dual 4X gigabit links between the and the VPX P1 connecr support serial procols. 32 In 32 Banks 1&2 Banks 3&4 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB 40 Option -104 I/O 4X x4 4X 4X Option -105 Gigabit Serial I/O VPX BACKPLANE VPX-P2 VPX-P1

36 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization The accepts an 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connecr allows multiple boards be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple s can be synchronized using the Cobalt high-speed sync board drive the sync bus. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO TEST SIGNAL LER Bank 3 Bank 4

37 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, V-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm). VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options

38 New! New! New! New! New! Models & Model or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 740 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 740 module while the Model is a 6U board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit converters and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition IP modules. In addition, IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57640; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57640; or one 4X link from each P2 and an additional 4X link between the s, Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One or two 1-channel mode with 3.6 GHz, 12-bit s Two or four 2-channel mode with 1.8 GHz, 12-bit s 2 or 4 GB of PCI Express (Gen. 1 & 2) interface up x8 µsync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Ruggedized and conductioncooled versions available Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P Banks1&2 In 32 VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 In VPX BACKPLANE Config FLASH 64 MB Option -104 I/O LVDS VPX-P3 40 8X Gen. 2 x8 Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58640

39 Models & Acquisition IP Modules These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the s, or a test signal generar. The IP modules have associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6-6U OpenVPX Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connecrs. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connecr allows multiple boards be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board drive the sync bus. Resources The Cobalt architecture supports four or eight independent memory banks of. Each bank is deep and is an integral part of the board s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO TEST SIGNAL LER Bank 3 Bank 4

40 Models & or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6-6U VPX Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit with two Virtex-6 s - 6U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57640; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57640; gigabit links from each P2 connecr, Model * Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Specifications Model 57640: One Model 58640: Two s Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connecrs Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connecr Sync Bus (1 or 2) Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57640; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57640; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

41 Models 72640, and or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6 - cpci Model Model General Information Models 72640, and are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 740 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 740 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit converters and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition IP modules. In addition, IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73640; J3 connecr, Model 72640; J3 and J5 connecrs, Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One or two 1-channel mode with 3.6 GHz, 12-bit s Two or four 2-channel mode with 1.8 GHz, 12-bit s 2 or 4 GB of Sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-bit Ref Clk In Ref Clk Out Sync Bus MODEL INTEACES ONLY VIRTEX-6 LVDS 40 Optional PCI I/O BRIDGE (Option -104) J2 PCI/PCI-X BUS 32-bit, 33/66 MHz Banks1&2 32 In 32 Banks3&4 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB LVDS J3 40 x4 Optional I/O (Option -104) 4X PCI BRIDGE From/To Other XMC Module of MODEL PCI PCI BRIDGE PCI/PCI-X BUS 32/64-bit, 33/66 MHz

42 Models 72640, and Acquisition IP Modules These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the s, or a test signal generar. The IP modules have associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6 - cpci Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connecrs. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connecr allows multiple boards be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board drive the sync bus. Resources The Cobalt architecture supports four or eight independent memory banks of. Each bank is deep and is an integral part of the board s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73640: 32 bits only. from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 4X 40 I/O TEST SIGNAL LER Bank 3 Bank 4

43 Models 72640, and or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, Virtex-6 - cpci Specifications Model or Model 73640: One Model 74640: Two s Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connecrs Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connecr Sync Bus (1 or 2) Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73640; J3 connecr, Model 72640; J3 and J5 connecrs, Model Banks (1 or 2) Four memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73640: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6-6U cpci Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6-3U cpci Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit, Virtex-6-6U cpci Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73640; J3 connecr, Model 72640; J3 and J5 connecrs, Model * Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required

44 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - AMC Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sample clock synchronization an external system reference Sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus Banks1&2 controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. 32 In 32 Banks3&4 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB x8 8X IPMI LER RS-232 LVDS 40 GPIO (option 104) AMC Ports 4 11 Front Panel Front Panel

45 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - AMC Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connecr allows multiple modules be VIRTEX-6 FLOW DETAIL (Two channel mode shown) LER Bank 1 Bank 2 PACKING META INTEACE from ACQUISITION IP MODULE synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple s can be synchronized using the Cobalt high speed sync module drive the sync bus. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the module s DMA and data capture capabilities. Built-in memory functions include an data transient capture mode for taking snapshots of data for transfer a host computer. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). from INPUT MULTIPLEXER MEM PACKING META ACQUISITION IP MODULE (supports user installed IP) 8X 40 GPIO TEST SIGNAL LER Bank 3 Bank 4

46 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - AMC PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, Virtex-6 - AMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through front panel connecr -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Contact Pentek for availability of rugged and conduction-cooled versions

47 Model Channel 200 MHz, -bit with Virtex-6 - XMC General Information Model 760 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 760 includes general purpose and gigabit serial connecrs for application-specific I/O. generar, and a interface complete the facry-installed functions and enable the 760 operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 200 MHz -bit s Up 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The 760 facry-installed functions include four acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with one 8X or two 4X gigabit links the support serial procols. In 200 MHz -BIT In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB Config FLASH 64 MB In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T 8X In 200 MHz -BIT 4X 4X LVDS 40 QDRII+ option 150 option 155 QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 x8 P15 XMC Gigabit Serial I/O (option 105) P XMC GPIO (option 104) P14 PMC

48 Model Channel 200 MHz, -bit with Virtex-6 - XMC Acquisition IP Modules The 760 features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 760 s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Resources The 760 architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. XMC Interface The Model 760 complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up a 6 GHz bit clock. With dual XMC connecrs, the 760 INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

49 Model Channel 200 MHz, -bit with Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-6 - XMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) supports x8 on the first XMC connecr leaving the second connecr free support user-installed transfer procols specific the target application. PCI Express Interface The Model 760 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options

50 Model Channel 200 MHz, -bit with Virtex-6 - x8 Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 200 MHz -bit s Up 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes optional general-purpose and gigabit serial connecrs for applicationspecific I/O procols. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry- installed functions and enable the Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. In 200 MHz -BIT In 200 MHz -BIT In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T LVDS In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 Config FLASH 64 MB 40 8X 4X 4X Optional GPIO 68-pin Header x8 x8 PCI Express Optional Serial I/O Dual 4X Serial Conn

51 Model Channel 200 MHz, -bit with Virtex-6 - x8 Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

52 Model Channel 200 MHz, -bit with Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

53 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz -bit s Up 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution. The includes four s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 Banks1&2 the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 200 MHz -BIT In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks3&4 Config FLASH 64 MB In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE LVDS 40 Option -104 I/O VPX-P2 In 200 MHz -BIT 8X x8 4X 4X Gbit Gbit Serial Serial Option -105 Gigabit Serial I/O CROSSBAR SWITCH VPX-P1 4X 4X Gbit Serial 4X 4X Gbit Serial

54 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

55 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz, -bit with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr LVPECL bus includes, clock/sync/ gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No 8267 VPX Development System. See 8267 Datasheet for Options

56 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz -bit s Up 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution. The includes four s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 Banks1&2 In 200 MHz -BIT the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks3&4 Config FLASH 64 MB In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE LVDS 40 VPX-P2 Option -104 I/O In 200 MHz -BIT 4X x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

57 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

58 Model Channel 200 MHz, -bit with Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz, -bit with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr LVPECL bus includes, clock/sync/ gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options

59 New! New! New! New! New! Models & Model or 8-Channel 200 MHz, -bit with Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 760 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 760 module while the Model is a 6U board with two XMC modules rather than one. These models include four or eight s and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facryinstalled functions of these models include four or eight acquisition IP modules. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57660; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57660; or one 4X link from each P2 and an additional 4X link between the s, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four or eight 200 MHz -bit s Up 2 or 4 GB of ; or: 32 or 64 MB of QDRII+ SRAM PCI Express (Gen. 1 & 2) interface up x8 Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Ruggedized and conductioncooled versions available Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 In 200 MHz -BIT VPX BACKPLANE Config FLASH 64 MB Option -104 I/O In 200 MHz -BIT LVDS VPX-P3 40 8X Gen. 2 x8 In 200 MHz -BIT Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58660

60 Models & Acquisition IP Modules These models feature four or eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 4- or 8-Channel 200 MHz, -bit with Virtex-6-6U OpenVPX Converter Stages The front end accepts four or eight full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 s for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

61 Models & or 8-Channel 200 MHz, -bit with Virtex-6-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz -bit with Virtex-6-6U VPX Channel 200 MHz -bit with two Virtex-6 s - 6U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57660; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57660; gigabit links from each P2 connecr, Model Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Model 57660: 4 s Model 58660: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board clock synthesizers Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connecr; LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57660; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57660; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

62 Models 72660, and or 8-Channel 200 MHz, -bit with Virtex-6 - cpci Model Model General Information Models 72660, and are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 760 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 760 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include four or eight s and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facryinstalled functions of these models include four or eight acquisition IP modules. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73660; J3 connecr, Model 72660; J3 and J5 connecrs, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four or eight 200 MHz -bit s Up 2 or 4 GB of ; or: 32 or 64 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus MODEL INTEACES ONLY VIRTEX-6 LVDS 40 Optional PCI I/O BRIDGE (Option -104) TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 option 155 In 200 MHz -BIT In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 0 option 5 In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T LVDS In 200 MHz -BIT 40 4X Config FLASH 64 MB PCI BRIDGE Optional I/O (Option -104) From/To Other XMC Module of MODEL PCI PCI BRIDGE J2 PCI/PCI-X BUS 32-bit, 33/66 MHz Banks 1 & 2 Banks 3&4 J3 PCI/PCI-X BUS 32/64-bit, 33/66 MHz

63 Models 72660, and Acquisition IP Modules These models feature four or eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 4- or 8-Channel 200 MHz, -bit with Virtex-6 - cpci Converter Stage The front end accepts four or eight full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73660: 32 bits only. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 PACKING META ACQUISITION IP MODULE 4 (supports user installed IP) 4X 40 I/O

64 Models 72660, and or 8-Channel 200 MHz, -bit with Virtex-6 - cpci Ordering Information Channel 200 MHz -bit with Virtex-6-6U cpci Channel 200 MHz -bit with Virtex-6-3U cpci Channel 200 MHz -bit with two Virtex-6 s - 6U cpci Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73660; J3 connecr, Model 72660; J3 and J5 connecrs, Model Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Model or Model 73660: 4 s Model 74660: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board clock synthesizers Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connecr; LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73660; J3 connecr, Model 72660; J3 and J5 connecrs, Model Banks (1 or 2) Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73660: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

65 Model Channel 200 MHz, -bit with Virtex-6 - AMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 200 MHz -bit s Up 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus QDRII+ SRAM 8MB QDRII+ SRAM 8MB IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. In 200 MHz -BIT In 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ SRAM 8MB Config FLASH 64 MB In 200 MHz -BIT VIRTEX-6 LX130T, LX240T or SX315T 8X In 200 MHz -BIT IPMI LER LVDS 40 QDRII+ option 150 option 155 QDRII+ option 0 option 5 x8 AMC Ports 4 11 RS-232 Front Panel GPIO (option 104) Front Panel Banks1&2 Banks3&4

66 Model Channel 200 MHz, -bit with Virtex-6 - AMC Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM,, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 40 GPIO PACKING META ACQUISITION IP MODULE 4

67 Model Channel 200 MHz, -bit with Virtex-6 - AMC Ordering Information Channel 200 MHz with Virtex-6 - AMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through front panel connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Contact Pentek for availability of rugged and conduction-cooled versions

68 Model Channel GSM Channelizer with Quad - XMC Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express Gen. 2 x8 General Information Model 763 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6. This four-channel, high-speed converter with 1100 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. It includes four s and four banks of DDCs. Channelizer data and control signals flow across the PCI Express Gen. 2 native interface, providing peak rates of up 4 GB/sec. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four DMA controllers, interface, gating, and triggering. The 763 is a complete, full-featured subsystem, ready use with no additional develpment required. Converter Stage The front end accepts four analog IF inputs on front panel SSMC connecrs with transformer coupling in four Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar accepts an external 180 MHz sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 763 s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. GSM Channelizer Cores The 763 contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of the four GSM channelizers. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x8 INTEACE x4 or x8 Sample / Ref Clock In M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & Clock / Sync Bus Gate / Trigger / Sync / PPS CLOCK, SYNC & TRIGGER 180 MHz VCXO

69 Model Channel GSM Channelizer with Quad - XMC The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection the 763, these GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digitized by the 763 s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must ensure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, thereby producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x oversampling, and results in a reduction of the aggregate traffic by a facr of GB/sec, which is now well within the capability of the Gen 2 x8 interface. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bit I + 26-bit Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank contains only three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface The Model 763 includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x8, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the 763 and host.

70 Model Channel GSM Channelizer with Quad - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in. Ordering Information Channel GSM Channelizer with Quad - XMC Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options

71 Model Channel GSM Channelizer with Quad - x8 Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express Gen. 2 x8 General Information Model is a member of the Cobalt family of high-performance boards based on the Xilinx Virtex-6. This fourchannel, high-speed converter with 1100 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. It includes four s and four banks of DDCs. Channelizer data and control signals flow across the PCI Express Gen. 2 native interface, providing peak rates of up 4 GB/sec. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four DMA controllers, interface, gating, and triggering. The is a complete, full-featured subsystem, ready use with no additional develpment required. Converter Stage The front end accepts four analog IF inputs on front panel SSMC connecrs with transformer coupling in four Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar accepts an external 180 MHz sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. GSM Channelizer Cores The contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of the four GSM channelizers. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x8 INTEACE x4 or x8 Sample / Ref Clock In M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & Clock / Sync Bus Gate / Trigger / Sync / PPS CLOCK, SYNC & TRIGGER 180 MHz VCXO

72 Model Channel GSM Channelizer with Quad - x8 The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection the 78663, these GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digitized by the s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must ensure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, thereby producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x oversampling, and results in a reduction of the aggregate traffic by a facr of GB/sec, which is now well within the capability of the Gen 2 x8 interface. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bit I + 26-bit Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank contains only three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x8, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the and host.

73 Model Channel GSM Channelizer with Quad - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 x 7.13 in. Ordering Information Channel GSM Channelizer with Quad PC Development System See 8266 Datasheet for Options

74 Model Channel GSM Channelizer with Quad - VPX Model Commercial (left) and rugged version Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express Gen. 2 x8 3U VPX form facr provides a compact, rugged platform General Information Model is a member of the Cobalt family of high-performance VPX boards based on the Xilinx Virtex-6. This fourchannel, high-speed converter with 1100 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. It includes four s and four banks of DDCs. Channelizer data and control signals flow across the PCI Express Gen. 2 native interface, providing peak rates of up 4 GB/sec. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four DMA controllers, interface, gating, and triggering. The is a complete, full-featured subsystem, ready use with no additional develpment required. Converter Stage The front end accepts four analog IF inputs on front panel SSMC connecrs with transformer coupling in four Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar accepts an external 180 MHz sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. GSM Channelizer Cores The contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of the four GSM channelizers. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x8 INTEACE 8X Sample / Ref Clock In M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & x8 Clock / Sync Bus Gate / Trigger / Sync / PPS CLOCK, SYNC & TRIGGER 180 MHz VCXO VPX BACKPLANE 4X Gbit Serial CROSSBAR SWITCH 4X Gbit Serial VPX-P1 4X Gbit Serial 4X Gbit Serial

75 Model Channel GSM Channelizer with Quad - VPX The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection the 53663, these GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digitized by the s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must ensure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, thereby producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x oversampling, and results in a reduction of the aggregate traffic by a facr of GB/sec, which is now well within the capability of the Gen 2 x8 interface. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bit I + 26-bit Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank contains only three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x8, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the and host. Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).

76 Model Channel GSM Channelizer with Quad - VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Model Description Channel GSM Channelizer with Quad - VPX Contact Pentek for availability of rugged and conduction-cooled versions Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics: < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No 8267 VPX Development System. See 8267 Datasheet for Options

77 Model Channel GSM Channelizer with Quad - VPX Model Commercial (left) and rugged version Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express Gen. 2 x4 3U VPX form facr provides a compact, rugged platform General Information Model is a member of the Cobalt family of high-performance VPX boards based on the Xilinx Virtex-6. This fourchannel, high-speed converter with 1100 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. It includes four s and four banks of DDCs. Channelizer data and control signals flow across the PCI Express Gen. 2 native interface, providing peak rates of up 2 GB/sec. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four DMA controllers, interface, gating, and triggering. The is a complete, full-featured subsystem, ready use with no additional develpment required. Converter Stage The front end accepts four analog IF inputs on front panel SSMC connecrs with transformer coupling in four Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar accepts an external 180 MHz sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. GSM Channelizer Cores The contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of the four GSM channelizers. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x4 INTEACE 4X Sample / Ref Clock In M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & Clock / Sync Bus CLOCK, SYNC & TRIGGER 180 MHz VCXO x4 Gate / Trigger / Sync / PPS VPX BACKPLANE VPX-P1

78 Model Channel GSM Channelizer with Quad - VPX The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection the 52663, these GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digitized by the s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must ensure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, thereby producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 2 GB/sec peak rate of Gen 2 x4 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x oversampling, and results in a reduction of the aggregate traffic by a facr of GB/sec, which is slightly above the capability of the Gen 2 x4 interface. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bit I + 26-bit Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank contains only three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x4, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the and host.

79 Model Channel GSM Channelizer with Quad - VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Model Description Channel GSM Channelizer with Quad - VPX Contact Pentek for availability of rugged and conduction-cooled versions Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics: < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No 8267 VPX Development System. See 8267 Datasheet for Options

80 New! New! New! New! New! Models & Features Model Four or eight 180 MHz -bit s Two or four banks of 375 DDCs for upper GSM band Two or four banks of 175 DDCs for lower GSM band PCI Express (Gen. 1 & 2) interface up x4 LVPECL clock/sync bus for multiboard synchronization Ruggedized and conductioncooled versions available or 2200-Channel GSM Channelizer with Quad or Octal - 6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 763 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 763 module while the Model is a 6U board with two XMC modules rather than one. This quad or octal, high-speed converter with 1100 or 2200 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four or eight facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four or eight DMA controllers, interface, gating, and triggering. These models are complete, full-featured subsystems, ready use with no additional develpment required. Converter Stage The front end accepts four or eight analog IF inputs on front panel SSMC connecrs with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization The internal timing bus provides all timing and synchronization required by the converters. It includes clock, sync and gate or trigger signals. One or two on-board clock generars accept external 180 MHz sample clocks from the front panel SSMC connecrs. The clocks can be used directly by the s or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/ Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Ch A In Ch B In Ch C In Ch D In Sample / Ref Clock In Clock / Sync Bus Gate / Trigger / Sync / PPS 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT CLOCK, SYNC & TRIGGER 180 MHz VCXO M U X M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET PACKET Block Diagram, Model Model doubles all resources except the -- Switch FIFO & FIFO & FIFO & FIFO & GEN 2 x4 INTEACE Gen. 2 x4 VPX BACKPLANE 4X Gen. 2 x4 - SWITCH VPX-P1 From/To Other XMC Module of Model 58663

81 Models & or 2200-Channel GSM Channelizer with Quad or Octal - 6U OpenVPX GSM Channelizer Cores These models contain four or eight powerful GSM channelizer cores, two or four with 375 DDCs and two or four with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of four GSM channelizers. The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection these models, the GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digtitized by the four or eight s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must insure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x over sampling, and results in a reduction of the aggregate traffic by a facr of GB/sec. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bits I + 26-bits Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank only contains three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the PCI-X bus. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once compete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. The interface is also used as the programming interface for all status and control between these models and host. Converters (4 or 8)

82 Models & or 2200-Channel GSM Channelizer with Quad or Octal - 6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel GSM Channelizer with Quad - 6U VPX Channel GSM Channelizer with Octal - 6U VPX Specifications Model 57663: 4 s, 1100 Channels Model 58663: 8 s, 2200 Channels Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus (1 or 2): 26-pin front panel connecr; LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks (1 or 2) DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VSX315T PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

83 Models 72663, and or 2200-Channel GSM Channelizer with Quad or Octal - cpci Model Model Features Complete GSM channelizer with analog IF interface Four or eight 180 MHz -bit s Two or four banks of 375 DDCs for upper GSM band Two or four banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization General Information Models 72663, and are members of the Cobalt family of high-performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 763 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 763 XMC. Model is a 6U cpci board with two XMC modules rather than one. This quad or octal, high-speed converter with 1100 or 2200 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four or eight facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four or eight DMA controllers, interface, gating, and triggering. These models are complete, full-featured subsystems, ready use with no additional develpment required. Converter Stage The front end accepts four or eight analog IF inputs on front panel SSMC connecrs with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization The internal timing bus provides all timing and synchronization required by the converters. It includes clock, sync and gate or trigger signals. One or two on-board clock generars accept external 180 MHz sample clocks from the front panel SSMC connecrs. The clocks can be used directly by the s or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/ Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x4 INTEACE 4X Sample / Ref Clock In Clock / Sync Bus Gate / Trigger / Sync / PPS CLOCK, SYNC & TRIGGER 180 MHz VCXO M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET MODEL INTEACE ONLY GEN 2 x4 INTEACE FIFO & PCI BRIDGE From/To Other XMC Module of MODEL Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz PCI PCI BRIDGE PCI/PCI-X BUS 32/64-bit, 33/66 MHz

84 Models 72663, and or 2200-Channel GSM Channelizer with Quad or Octal - cpci GSM Channelizer Cores These models contain four or eight powerful GSM channelizer cores, two or four with 375 DDCs and two or four with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of four GSM channelizers. The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection these models, the GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digtitized by the four or eight s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must insure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x over sampling, and results in a reduction of the aggregate traffic by a facr of GB/sec. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bits I + 26-bits Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank only contains three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the PCI-X bus. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once compete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73663: 32 bits only. The PCI-X interface is also used as the programming interface for all status and control between these models and host.

85 Models 72663, and or 2200-Channel GSM Channelizer with Quad or Octal - cpci Specifications Model or Model 73663: 4 s Model 74663: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus (1 or 2): 26-pin front panel connecr; LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks (1 or 2) DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VSX315T PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73663: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board Ordering Information Channel GSM Channelizer with Quad - 6U cpci Channel GSM Channelizer with Quad - 3U cpci Channel GSM Channelizer with Octal - 6U cpci

86 Model Channel GSM Channelizer with Quad - AMC Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express Gen. 2 x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. This fourchannel, high-speed converter with 1100 GSM DDCs (digital downconverters) accepts IF signals from an tuner. It is ideal for capturing all transmit and receive signals in both upper and lower GSM bands. It includes four s and four banks of DDCs. Channelizer data and control signals flow across the PCI Express Gen. 2 native interface, providing peak rates of up 4 GB/sec. The Cobalt Architecture The Pentek Cobalt architecture connects all of the board s data converters, digital interfaces, clocks and timing signals the. Here, four facry-installed GSM channelizer IP cores are supported with additional functions including packet formation, four DMA controllers, interface, gating, and triggering. The is a complete, full-featured subsystem, ready use with no additional develpment required. Converter Stage The front end accepts four analog IF inputs on front panel SSMC connecrs with transformer coupling in four Texas Instruments ADS MHz, -bit converters clocked at 180 MHz. The digital outputs are delivered in the for GSM channelizer signal processing. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar accepts an external 180 MHz sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board 180 MHz voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a reference clock, typically 10 MHz, for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. GSM Channelizer Cores The contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, non-blocking assignment of any converter serve as the input source for any of the four GSM channelizers. Ch A In 180 MHz -BIT M U X GSM CHANNELIZER 375 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & Ch B In Ch C In Ch D In Sample / Ref Clock In Clock / Sync Bus Gate / Trigger / Sync / PPS 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT CLOCK, SYNC & TRIGGER 180 MHz VCXO M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & RS-232 Front Panel GEN 2 x8 INTEACE IPMI LER AMC Ports 411 x8

87 Model Channel GSM Channelizer with Quad - AMC The 375-channel cores are designed for the upper GSM bands which contain two 75 MHz bands, one for uplink and one for downlink. The 175-channel cores are designed for the lower GSM band and handle two 35 MHz bands, one for uplink and one for downlink. Before connection the 56663, these GSM bands must first be separately downconverted an IF frequency centered at 45 MHz, 135 MHz or 225 MHz using an external analog tuner. These IF signals are then digitized by the s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. In order prevent aliasing, careful filtering must ensure that no signals appear in adjacent Nyquist zones. Each of the channelizers is designed accept real digital samples of the IF signal from the converter. The first stage of the GSM channelizer is a complex mixer that shifts the center frequency of the IF signal (45, 135 or 225 MHz) 0 Hz, thereby producing complex I+Q samples. The DDCs split the IF input in either 175 or 375 parallel DDC baseband channels, equally spaced at 200 khz. The DDC output sample rate is resampled precisely 180 MHz*13/20, or approximately MHz. This is four times the GSM symbol rate of ksymbols/sec. The output passband of each DDC channel is nominally 0 khz, with filter characteristics fully defined in the channel response chart in the specifications. Channelizer Output Formatting All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, greatly exceeding the 4 GB/sec peak rate of Gen 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single superchannel. This is allowed because of the 4x oversampling, and results in a reduction of the aggregate traffic by a facr of GB/sec, which is now well within the capability of the Gen 2 x8 interface. During superchannel formation, the 24-bit I + 24-bit Q output samples from four DDCs are summed superchannel samples with 26-bit I + 26-bit Q. As a result, the two 375-channel banks each deliver 94 superchannels, while the two 175-channel banks each deliver 44 superchannels. The last superchannel in each bank contains only three DDC channels. A superchannel enable mask word containing one enable bit for each superchannel allows independent selection of which superchannel samples are delivered across the. There are four superchannel mask words, one for each bank. Superchannel Packets and Headers Superchannel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining superchannel data payload samples can be identified and recovered by the host. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x8, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the and host. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller).

88 Model Channel GSM Channelizer with Quad - AMC Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCs and two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- & 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Freqs: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Superchannels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Ordering Information Model Description Channel GSM Channelizer with Quad - AMC Contact Pentek for availability of rugged and conduction-cooled versions

89 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - XMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model 770 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 770 includes general purpose and gigabit serial connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The 770 facry-installed functions include four D/A waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, a controller for all data clocking and synchronization functions, Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER a test signal generar, and a interface complete the facry-installed functions and enable the 770 operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support serial procols. Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T 8X Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 4X 4X LVDS 40 Banks1&2 Banks3&4 x8 Gigabit Serial I/O (option 105) GPIO (option 104) P15 XMC P XMC P14 PMC

90 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - XMC D/A Waveform Playback IP Module The Model 770 facryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation the four D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by 2, 4, 8, or provide lower frequency D/A clocks. TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 7192 or 9192 Cobalt Synchronizers can drive multiple 770 µsync connecrs enabling large, multichannel synchronous configurations. Resources The 770 architecture supports four independent memory banks of. Each bank is deep and is an integral part of the module s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. XMC Interface The Model 770 complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up a GHz bit clock. With dual XMC connecrs, the 770 supports x8 on the first XMC connecr leaving the second connecr free support user-installed transfer procols specific the target application. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

91 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 1.25 GHz D/A with Virtex-6 - XMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required PCI Express Interface The Model 770 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the module. Specifications D/A Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as two 4X or one 8X gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options

92 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - x8 Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes optional general purpose and gigabit serial connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four D/A waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Banks 1&2 Banks 3&4 Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T LVDS Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 40 8X 4X 4X Optional GPIO x8 Optional Serial I/O 68-pin Header Dual 4X Serial Conn x8 PCI Express

93 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - x8 D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation the four D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 7892 or 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the board. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

94 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 1.25 GHz D/A with Virtex-6 - x8 Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Specifications D/A Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

95 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization User-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model includes general purpose and gigabit serial connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four D/A waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, a controller for all data clocking and synchronization functions, Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Banks1&2 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Banks3&4 Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T LVDS 40 Option -104 I/O VPX-P2 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 8X x8 Option -105 Gigabit Serial I/O CROSSBAR SWITCH 4X 4X 4X Gbit Gbit Gbit Serial Serial Serial VPX-P1 4X 4X 4X Gbit Serial

96 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation the four D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 5392 or 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the board. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

97 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 1.25 GHz D/A with Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Contact Pentek for availability of rugged and conduction-cooled versions Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Specifications D/A Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No 8267 VPX Development System. See 8267 Datasheet for Options

98 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization User-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model includes general purpose and gigabit serial connecrs for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four D/A waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, a controller for all data clocking and synchronization functions, Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Banks1&2 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Banks3&4 Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T LVDS 40 VPX-P2 Option -104 I/O Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 4X x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

99 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation the four D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 5292 or 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the board s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x4 lane interface includes multiple DMA controllers for efficient transfers and from the board. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

100 Model Channel 1.25 GHz D/A with DUC, Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 1.25 GHz D/A with Virtex-6-3U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Specifications D/A Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options

101 New! New! New! New! New! Models & Model Features Supports Xilinx Virtex-6 LXT and SXT s Four or eight 1.25 GHz -bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of PCI Express (Gen. 1 & 2) interface up x8 Sample clock synchronization an external system reference Dual-or Quad µsync clock/ sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Ruggedized and conductioncooled versions available 4- or 8-Channel 1.25 GHz D/A with DUC and Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 770 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 770 module while the Model is a 6U board with two XMC modules rather than one. These models include four or eight D/As, four or eight DUCs, and four or eight banks of memory. Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 Clock/Sync Bus A Clock/Sync Bus B GHz -BIT D/A DIGITAL UPCONVERTER 32 Out The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions in these models include four or eightd/a waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, controllers for all data clocking and synchronization functions, test signal generars, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57670; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57670; or one 4X link from each P2 and an additional 4X link between the s, Model Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 32 VIRTEX-6 LX240T or SX315T VPX BACKPLANE Config FLASH 64 MB Option -104 I/O Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER 32 Banks 1&2 Banks 3 & 4 LVDS VPX-P3 40 8X Gen. 2 x8 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58671

102 Models & or 8-Channel 1.25 GHz D/A with DUC and Virtex-6-6U OpenVPX D/A Waveform Playback IP Module The facry-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked list controllers support waveform generation the four or eight D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4, as well as the other four channels of Model Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 or 128 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four or eight front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 can be used directly or can be divided by 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Model 9192 Cobalt Synchronizer can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture of these models supports four or eight independent memory banks of. Each bank is deep and is an integral part of the board s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked-list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

103 Models & or 8-Channel 1.25 GHz D/A with DUC and Virtex-6-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 1.25 GHz D/A with Virtex-6-6U VPX Channel 1.25 GHz D/A with two Virtex-6 s - 6U VPX Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57670; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57670; gigabit links from each P2 connecr, Model * Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required Specifications Model 57670: 4-Channel DUC, 4-channel D/A Model 58670: 8-Channel DUC, 8-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin µsync bus connecr includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57670; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57670; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Four or eight memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

104 Models 72670, and or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 - cpci Model Model General Information Models 72670, and are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 770 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 770 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include four or eight D/As, four or eight DUCs, and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions in these models include four or eightd/a waveform playback IP modules, support waveform generation through the D/A converters. IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73670; J3 connecr, Model 72670; J3 and J5 connecrs, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four or eight 1.25 GHz -bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of Sample clock synchronization an external system reference Dual-or Quad µsync clock/ sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B MODEL INTEACES ONLY VIRTEX-6 LVDS 40 Optional PCI I/O BRIDGE (Option -104) TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Banks 1 & 2 Banks 3 & 4 Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T LVDS 40 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER x4 Optional I/O (Option -104) 4X PCI BRIDGE From/To Other XMC Module of Model PCI PCI BRIDGE J2 PCI/PCI-X BUS 32-bit, 33/66 MHz J3 PCI/PCI-X BUS 32/64-bit, 33/66 MHz

105 Models 72670, and or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 - cpci D/A Waveform Playback IP Module The facry-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked list controllers support waveform generation the four or eight D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4, as well as the other four channels of Model Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 or 128 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING VIRTEX-6 FLOW DETAIL Bank 3 INTERLEAVER Bank 2 Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 7292, 7392 and 7492 or the 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture of these models supports four or eight independent memory banks of. Each bank is deep and is an integral part of the board s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73670: 32 bits only. Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4 (supports user installed IP) 4X 40 I/O

106 Models 72670, and or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 - cpci Specifications Models and 73670: 4-Channel DUC, 4-channel D/A Model 74670: 8-Channel DUC, 4-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin µsync bus connecr includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73670; J3 connecr, Model 72670; J3 and J5 connecrs, Model Banks (1 or 2) Four or eight memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73670: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board Ordering Information Channel 1.25 GHz D/A with Virtex-6-6U cpci Channel 1.25 GHz D/A with Virtex-6-3U cpci Channel 1.25 GHz D/A with Virtex-6-6U cpci Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73670; J3 connecr, Model 72670; J3 and J5 connecrs, Model * Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required

107 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - AMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four D/A waveform playback IP modules, support waveform generation through the D/A converters. IP modules for Sample Clk / Reference Clk In Trigger In Gate In Sync In μsync Bus A Gate In Sync In μsync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Banks 1&2 Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER Banks3&4 Config FLASH 64 MB Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T x8 8X Out 1.25 GHz -BIT D/A DIGITAL UPCONVERTER IPMI LER RS-232 LVDS 40 GPIO (option 104) AMC Ports 4 11 Front Panel Front Panel

108 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - AMC D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation the four D/As from tables sred in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each D/A channel can be chained gether create complex waveforms with a minimum of programming. Digital Upconverter and D/A Stage Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit D/A converter. If translation is disabled, each D/A acts as an interpolating -bit D/A with output sampling rates up 1.25 GHz. In both modes, the D/A provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Clocking and Synchronization An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided by TEST SIGNAL Bank 1 Bank 1 D/A WAVEFORM PLAYBACK IP MODULE 1 Bank 2 UNPACKING Bank 3 INTERLEAVER Bank 2 VIRTEX-6 FLOW DETAIL Bank 4 D/ACh1&2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 2 2, 4, 8, or provide lower frequency D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and trigger/gate signals. The Pentek Models 5692 or 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Resources The architecture supports four independent memory banks of. Each bank is deep and is an integral part of the module s DMA and waveform playback capabilities. Waveform tables can be loaded in the memories with playback managed by the linked list controllers. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). Bank 3 INTEACE UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 3 INTERLEAVER Bank 4 D/ACh3&4 (supports user installed IP) 8X 40 GPIO UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4

109 Model Channel 1.25 GHz D/A with DUC, Virtex-6 - AMC Ordering Information Channel 1.25 GHz D/A with Virtex-6 - AMC Options: -002* -2 speed grade -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through front panel connecr -155* Two Banks (Banks 1 and 2) -5* Two Banks (Banks 3 and 4) * These options are always required PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers and from the module. Specifications D/A Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Contact Pentek for availability of rugged and conduction-cooled versions

110 Model 790 L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - XMC General Information Model 790 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A 2-Channel high-speed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 790 includes general purpose and gigabit serial connecrs for application-specific I/O. generar, and a interface complete the facry-installed functions and enable the 790 operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 60 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The 790 facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Ref In Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with one 8X or two 4X gigabit links the support serial procols. QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T Control 8X x8 P15 XMC 12-BIT D/A IC 2 2 4X 4X Gigabit Serial I/O (option 105) P XMC LVDS 40 GPIO (option 104) P14 PMC

111 Model 790 Acquisition IP Modules The 790 features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - XMC Tuner Stage A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the module. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave modules, supporting synchronous sampling and sync functions across all connected modules. Resources The 790 architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

112 Model 790 L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information 790 L-Band Tuner with 2-Channel 200 MHz and Virtex-6 - XMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. XMC Interface The Model 790 complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up a 6 GHz bit clock. With dual XMC connecrs, the 790 supports x8 on the first XMC connecr leaving the second connecr free support userinstalled transfer procols specific the target application. PCI Express Interface The Model 790 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

113 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - x8 Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 60 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. A 2-Channel high-speed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes optional general-purpose and gigabit serial connecrs for application-specific I/O procols. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Ref In Option operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1 & 2 Banks 3 & 4 I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T Control LVDS 12-BIT D/A IC X 4X 4X Optional GPIO 68-pin Header x8 x8 PCI Express Optional Serial I/O Dual 4X Serial Conn

114 Model Acquisition IP Modules The features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - x8 Tuner Stage A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the board. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave boards, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

115 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information L-Band Tuner with 2-Channel 200 MHz and Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

116 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX Model COTS (left) and rugged version Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB antenna signal levels with up 60 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference Clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A 2-Channel high-speed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The Model includes an L-Band tuner, two s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Banks1&2 Ref In facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides dual 4X gigabit links between the and the VPX P1 connecr support serial procols. QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks3&4 I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE LVDS Control 12-BIT D/A IC Option -104 I/O VPX-P2 8X x8 Option -105 Gigabit Serial I/O CROSSBAR SWITCH 4X 4X 4X Gbit Gbit Gbit Serial Serial Serial VPX-P1 4X 4X 4X Gbit Serial

117 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX Acquisition IP Modules The features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Tuner Stage A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IPMODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the board. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave boards, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IPMODULE 2 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

118 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX PCI Express Interface The Model includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information L-Band Tuner with 2-Channel 200 MHz and Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user IP within the. Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr for serial procols Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

119 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX Model COTS (left) and rugged version Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB antenna signal levels with up 60 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference Clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A 2-Channel high-speed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The Model includes an L-Band tuner, two s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Banks1&2 Ref In facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides dual 4X gigabit links between the and the VPX P1 connecr support serial procols. QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks3&4 I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T VPX BACKPLANE LVDS Control 40 VPX-P2 12-BIT D/A IC 2 Option -104 I/O 2 4X x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

120 Model Acquisition IP Modules The features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX Tuner Stage A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the board. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave boards, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO

121 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6-3U VPX PCI Express Interface The Model includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information L-Band Tuner with 2-Channel 200 MHz and Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System. See 8267 Datasheet for Options Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed Acquisition Modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

122 New! New! New! New! New! Models & Model Features One or two L-Band tuners accept signals from 925 MHz 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up 60 db gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 40 MHz Two or four 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s Up 2 or 4 GB of ; or: 32 MB or 64MB of QDRII+ SRAM PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Ruggedized and conductioncooled versions available One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 790 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 790 module while the Model is a 6U board with two XMC modules rather than one. These models include one ot two L-Band tuners, two or four s and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions in these models include two or four acquisition IP modules. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, test signal generars, and a interface complete the facry-installed functions and Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 Ref QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ SRAM 8MB QDRII+ option 150 QDRII+ option 0 option 155 option 5 Clock/Sync Banks1&2 Ref In Banks3&4 enable these models operate as complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57690; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57690; or one 4X link from each P2 and an additional 4X link between the s, Model MHz -BIT I In MAX2112 VPX BACKPLANE Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T Option -104 I/O LVDS VPX-P3 Control 12-BIT D/A IC X Gen. 2 x8 Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58690

123 Models & Acquisition IP Modules These models feature two or four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6-6U OpenVPX Tuner Stages One or two front panel SSMC connecrs accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals baseband using broadband I/Q downconverters. The devices include variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillars, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizers lock their VCOs the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNAs offer a programmable linear gain range of 60 db. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stages The analog baseband I and Q analog tuner outputs are then applied two or four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 s for signal processing, data capture or for routing other board resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the bosrd. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave bosrds, supporting synchronous sampling and sync functions across all connected boards. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

124 Models & One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information L-Band Tuner with 2-Channel 200 MHz and Virtex-6-6U VPX Dual L-Band Tuner with 4-Channel 200 MHz and two Virtex-6 s - 6U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57690; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57690; gigabit links from each P2 connecr, Model Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Model 57690: One tuner, two s Model 58690: Two tuners, four s Front Panel Analog Signal Inputs (1 or 2) Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board timing generar/synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Inputs (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus (1 or 2): 26-pin front panel connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57690; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57690; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) 8264 VPX Development System. See 8264 Datasheet for Options

125 Models 72690, and Model Model Features One or two L-Band tuners accept signals from 925 MHz 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up 60 db gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 40 MHz Two or four 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s Up 2 or 4 GB of ; or: 32 MB or 64MB of QDRII+ SRAM Clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-6 for cusm I/O One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6 - cpci General Information Models 72690, and are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 790 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 790 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one ot two L-Band tuners, two or four s and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions in these models include two or four acquisition IP modules. IP modules for either or QDRII+ memories, controllers for all data clocking and synchronization functions, a Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus MODEL INTEACES ONLY VIRTEX-6 LVDS 40 Optional PCI I/O BRIDGE (Option -104) J2 TIMING Clock / Sync / Gate / PPS VCXO PCI/PCI-X BUS 32-bit, 33/66 MHz Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Ref In QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1 & 2 Banks 3 & 4 test signal generar, and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73690; J3 connecr, Model 72690; J3 and J5 connecrs, Model I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T Control LVDS J3 12-BIT D/A 40 IC 2 2 x4 Optional I/O (Option -104) 4X PCI BRIDGE From/To Other XMC Module of MODEL PCI PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz

126 Models 72690, and Acquisition IP Modules These models feature two or four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6 - cpci Tuner Stage One or two front panel SSMC connecrs accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals baseband using broadband I/Q downconverters. The devices include variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillars, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizers lock their VCOs the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two or four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the bosrd. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave bosrds, supporting synchronous sampling and sync functions across all connected boards. Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 4X 40 I/O

127 Models 72690, and One or two L-Band Tuners, 2- or 4-Channel 200 MHz, Virtex-6 - cpci Ordering Information 790 L-Band Tuner with 2-Channel 200 MHz and Virtex-6 - XMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73690; J3 connecr, Model 72690; J3 and J5 connecrs, Model Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. PCI-X Interface The models include an industry-standard interface compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73690: 32 bits only. Specifications Model or Model 73690: 1 tuner, 2 s Model 74690: 2 tuners, four s Front Panel Analog Signal Inputs (1 or 2) Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources (1 or 2) On-board timing generar/synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Inputs (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus (1 or 2): 26-pin front panel connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73690; J3 connecr, Model 72690; J3 and J5 connecrs, Model Banks (1 or 2) Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73690: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

128 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - AMC Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 60 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ SRAM Sample clock synchronization an external system reference Clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface, up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. A 2-Channel high-speed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ SRAM 8MB Clock/Sync QDRII+ SRAM 8MB QDRII+ option 150 option 155 Ref In and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. QDRII+ SRAM 8MB 200 MHz -BIT QDRII+ SRAM 8MB QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T x8 AMC Ports411 Control 12-BIT D/A 8X IC 2 2 IPMI LER RS-232 Front Panel LVDS 40 GPIO (option 104) Front Panel

129 Model Acquisition IP Modules The features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - AMC Tuner Stage A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO the timing generar output, or an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable linear gain range of 60 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converter Stage The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. TEST SIGNAL Bank 1 Bank 2 Bank 1 Bank 3 PACKING META VIRTEX-6 FLOW DETAIL Bank 4 ACQUISITION IP MODULE 1 from (I) Clocking and Synchronization An internal timing generar provides all timing, gating, triggering and synchronization functions required by the converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillar). In this mode, the front panel SSMC clock input connecr accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generar uses a front panel LVPECL 26-pin clock/sync connecr for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the module. In the master mode, the LVPECL bus drives output timing signals synchronize multiple slave modules, supporting synchronous sampling and sync functions across all connected modules. Resources The architecture supports up four independent memory banks which can be configured with all QDRII+ SRAM, all, or as combination of two banks of each type of memory. INPUT MULTIPLEXER INTEACE Bank 2 from (Q) PACKING META ACQUISITION IP MODULE 2 (supports user installed IP) 8X 40 GPIO

130 Model L-Band Tuner, 2-Channel 200 MHz, Virtex-6 - AMC Ordering Information L-Band Tuner with 2-Channel 200 MHz and Virtex-6 - AMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through front panel connecr -150 Two 8 MB QDRII+ SRAM Banks (Banks 1 and 2) -0 Two 8 MB QDRII+ SRAM Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions Each QDRII+ SRAM bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. The facry-installed acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed support cusm user-installed IP within the. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 15 db, in 1 db steps* *Usable Full-Scale Input Range: 50 dbm +10 dbm Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz (up 800 MHz when Timing Generar divider is enabled) or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

131 Model Channel 200 MHz, -bit with Virtex-7 - XMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Advanced reconfigurability features VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O General Information Model is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes general-purpose and gigabitserial connecrs for application-specific I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules for simplifying data capture and data transfer. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connecr with 24 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support serial procols. In 200 MHz -BIT 4X 4X In 200 MHz -BIT Gigabit Serial I/O (option 105) P XMC VIRTEX-7 VX330T or VX690T LVDS GPIO (option 104) P14 PMC In 200 MHz -BIT In 200 MHz -BIT

132 Model Channel 200 MHz, -bit with Virtex-7 - XMC Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives an INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

133 Model Channel 200 MHz, -bit with Virtex-7 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-7 - XMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. XMC Interface The Model complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up 10 Gb/sec per lane. With dual XMC connecrs, the supports x8 on the first XMC connecr leaving the second connecr free support userinstalled transfer procols specific the target application. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 s Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

134 Model Channel 200 MHz, -bit with Virtex-7 - x8 Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O General Information Model is a member of the Onyx family of high-performance boards based on the Xilinx Virtex-7. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes optional general-purpose and gigabit-serial connecrs for applicationspecific I/O procols. The Onyx Architecture Based on the proven design of the Pentek Cobalt Family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules for simplifying data capture and data transfer. IP modules for memories, a controller for all data clocking Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus CONFIG BUS - CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 connects 24 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. In 200 MHz -BIT 4X 4X Gigabit Serial I/O (option 105) Dual 4X Serial Conn In 200 MHz -BIT VIRTEX-7 VX330T or VX690T LVDS 68-pin Header In 200 MHz -BIT GPIO (option 104) In 200 MHz -BIT x8 PCI Express

135 Model Channel 200 MHz, -bit with Virtex-7 - x8 Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives an INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

136 Model Channel 200 MHz, -bit with Virtex-7 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-7 - x8 Options: -073 XC7VX330T XC7VX690T LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Connects 24 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 s Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

137 Model Channel 200 MHz, -bit with Virtex-7-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The includes four s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Onyx Architecture Based on the proven design of the Pentek Cobalt Family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules for simplifying data capture and data transfer. IP modules for memories, a controller for all data clocking Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 200 MHz -BIT VPX BACKPLANE In 200 MHz -BIT VIRTEX-7 VX330T or VX690T LVDS 40 VPX-P2 CONFIG FLASH Option -104 I/O In 200 MHz -BIT Config Bus In 200 MHz -BIT GATEXPRESS CONFIGURATION MANAGER Gen. 2 x8 Gen. 2 x8 CROSSBAR SWITCH Option -105 Gigabit Serial I/O 4X 4X 4X Gbit Gbit Gbit Serial Serial Serial VPX-P1 4X 4X 4X Gbit Serial

138 Model Channel 200 MHz, -bit with Virtex-7-3U VPX Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

139 Model Channel 200 MHz, -bit with Virtex-7-3U VPX PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

140 Model Channel 200 MHz, -bit with Virtex-7-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. The includes four s and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Onyx Architecture Based on the proven design of the Pentek Cobalt Family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP modules for simplifying data capture and data transfer. IP modules for memories, a controller for all data clocking Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 200 MHz -BIT VPX BACKPLANE In 200 MHz -BIT VIRTEX-7 VX330T or VX690T LVDS 40 VPX-P2 CONFIG FLASH Option -104 I/O In 200 MHz -BIT Config Bus In 200 MHz -BIT Gen. 2 x4 GATEXPRESS CONFIGURATION MANAGER Gen. 2 x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

141 Model Channel 200 MHz, -bit with Virtex-7-3U VPX Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 4X 4X 4X 40 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

142 Model Channel 200 MHz, -bit with Virtex-7-3U VPX PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz with Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

143 New! New! New! New! New! Models & Model Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four or eight 200 MHz -bit s 4 or 8 GB of PCI Express (Gen. 1, 2 & 3) interface up x8 Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Ruggedized and conductioncooled versions available 4- or 8-Channel 200 MHz, -bit with Virtex-7-6U OpenVPX General Information Models and are members of the Onyx family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-7. They consist of one or two Model XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model module while the Model is a 6U board with two XMC modules rather than one. These models include four or eight s and four or eight banks of memory. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 24 LVDS pairs from the 2nd VPX-P5 Clock/Sync Bus In 200 MHz -BIT VPX BACKPLANE The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include four or eight acquisition IP modules for simplifying data capture and data transfer. IP modules for memories, controllers for all data clocking and synchronization functions, test signal generars, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 24 LVDS pairs between the and the VPX P3 connecr, Model 57760; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57760; or one 4X link from each P2 and an additional 4X link between the s, Model VIRTEX-7 VX330T or VX690T Option -104 I/O In 200 MHz -BIT LVDS 48 VPX-P3 CONFIG FLASH In 200 MHz -BIT Gen. 3 x8 Config Bus GATEXPRESS CONFIGURATION MANAGER - SWITCH In 200 MHz -BIT Gen. 3 x8 Gen. 3 x8 VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58760

144 Models & Acquisition IP Modules These models feature four or eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four s or the test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 4- or 8-Channel 200 MHz, -bit with Virtex-7-6U OpenVPX TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the s. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the s time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user. In this case, it s programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the s with new IP images. The first option is load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded as needed. The third option, typically used during development, allows the user directly load the s through JTAG using Xilinx impact. In all three -loading scenarios, GateXpress handles the hardware negotiation thereby simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without the need reset the host computer so it can rediscover the board. After the reload, the host computer simply continues see the board with the expected device ID. Converter Stages The front end accepts four or eight fullscale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 s for signal processing, data capture or for routing other board resources. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO PACKING META ACQUISITION IP MODULE 4

145 Models & or 8-Channel 200 MHz, -bit with Virtex-7-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 200 MHz -bit with Virtex-7-6U VPX Channel 200 MHz -bit with two Virtex-7 s - 6U VPX Options: -076 XC7VX690T LVDS I/O between the and P3 connecr, Model 57760; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57760; gigabit links from each P2 connecr, Model Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The Onyx architecture supports four or eight independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Model 57760: 4 s Model 58760: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus (1 or 2) 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/ trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 24 LVDS pairs between the and the VPX P3 connecr, Model 57760; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57760; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (4 or 8) Type: Size: 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm)

146 Models 72760, and or 8-Channel 200 MHz, -bit with Virtex-7 - cpci Model Model General Information Models 72760, and are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7. They consist of one or two Model XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include four or eight s and four or eight banks of memory. The Onyx Architecture The Pentek Onyx Architecture features Virtex-7 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include four or eight acquisition IP modules for simplifying data capture and data transfer. IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73760; J3 connecr, Model 72760; J3 and J5 connecrs, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across PCI/PCI-X bus Four or eight 200 MHz -bit s Four or eight GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B I/O (Option -104) Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Timing Bus VIRTEX-7 TIMING BUS Clock / Sync / Gate / PPS VCXO MODEL INTEACES ONLY LVDS J2 40 CONFIG FLASH Config Bus PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz GATEXPRESS CONFIGURATION MANAGER x4 x4 Clock/Sync Bus In 200 MHz -BIT In 200 MHz -BIT VIRTEX-7 VX330T or VX690T LVDS J3 40 In 200 MHz -BIT CONFIG FLASH Optional I/O (Option -104) In 200 MHz -BIT Config Bus PCI BRIDGE GATEXPRESS CONFIGURATION MANAGER x4 x4 PCI PCI BRIDGE From/To Other XMC Module of Model PCI/PCI-X BUS 32/64-bit, 33/66 MHz

147 Models 72760, and Acquisition IP Modules These models feature four or eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four s or the test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 4- or 8-Channel 200 MHz, -bit with Virtex-7 - cpci TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four or eight fullscale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four or eight Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 PACKING META ACQUISITION IP MODULE 4 (supports user installed IP) 4X 40 I/O

148 Models 72760, and or 8-Channel 200 MHz, -bit with Virtex-7 - cpci Ordering Information Channel 200 MHz -bit with Virtex-7-6U cpci Channel 200 MHz -bit with Virtex-7-3U cpci Channel 200 MHz -bit with two Virtex-7 s - 6U cpci Options: -073 XC7VX330T XC7VX690T LVDS I/O between the and J2 connecr, Model 73760; J3 connecr, Model 72760; J3 and J5 connecrs, Model Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generar receives an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Resources The Onyx architecture supports four or eight independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73760: 32 bits only. Specifications Model or Model 73760: 4 s Model 74760: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus (1 or 2) 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/ trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: provides 20 LVDS pairs between the and the J2 connecr, Model 73760; J3 connecr, Model 72760; J3 and J5 connecrs, Model Banks (1 or 2) Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73760: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

149 Model Channel 200 MHz, -bit with Virtex-7 - AMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-7 for cusm I/O General Information Model is a member of the Onyx family of high-performance AMC modules based on the Xilinx Virtex-7. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes a front panel general-purpose connecr for applicationspecific I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include four acquisition IP Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 In modules for simplifying data capture and data transfer. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. 200 MHz -BIT AMC Ports 4 11 In 200 MHz -BIT VIRTEX-7 VX330T or VX690T IPMI LER RS-232 Front Panel LVDS In 200 MHz -BIT GPIO (option 104) Front Panel In 200 MHz -BIT

150 Model Channel 200 MHz, -bit with Virtex-7 - AMC Acquisition IP Modules The features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of TEST SIGNAL Bank 1 Bank 1 PACKING META Bank 2 ACQUISITION IP MODULE 1 Bank 3 from Ch 1 Bank 2 VIRTEX-7 FLOW DETAIL Bank 4 PACKING META from Ch 2 ACQUISITION IP MODULE 2 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generar receives INPUT MULTIPLEXER Bank 3 INTEACE from Ch 3 PACKING META ACQUISITION IP MODULE 3 Bank 4 from Ch 4 (supports user installed IP) 8X 48 GPIO PACKING META ACQUISITION IP MODULE 4

151 Model Channel 200 MHz, -bit with Virtex-7 - AMC Ordering Information Channel 200 MHz with Virtex-7 - AMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through front panel connecr Contact Pentek for availability of rugged and conduction-cooled versions an external sample clock from the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple modules be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user- installed IP within the can take advantage of the memories for many other purposes. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 s AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

152 Model GHz and 1 GHz D/A, Virtex-7 - XMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit D/A 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O General Information Model is a member of the Onyx family of high performance XMC modules based on the Xilinx Virtex-7. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and D/A converters and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes optional general purpose and gigabit serial card connecrs for application-specific I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connecr with 24 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support serial procols. 4X In 1 GHz 12-BIT 4X 12 VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) P XMC LVDS GPIO (option 104) P14 PMC Out 1 GHz -BIT D/A

153 Model GHz and 1 GHz D/A, Virtex-7 - XMC Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GS/sec, allowing it accept full-rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO

154 Model GHz and 1 GHz D/A, Virtex-7 - XMC XMC Interface The Model complies with the VITA 42.0 XMC specification. Two connecrs each provide dual 4X links or a single 8X link with up 10 Gb/sec per lane. With dual XMC connecrs, the supports x8 on the first XMC connecr leaving the second connecr free support user-installed transfer procols specific the target application. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-7 - XMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 730 µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

155 Model GHz and 1 GHz D/A with Virtex-7 - x8 Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit D/A 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Onyx family of high-performance boards based on the Xilinx Virtex-7. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and 1 GHz D/A converters and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes optional general-purpose and gigabit serial card connecrs for application specific I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Config Bus GATEXPRESS CONFIGURATION MANAGER Gen.3x8 Gen.3x8 P15 XMC IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 connects 24 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. In 1 GHz 12-BIT 12 VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) Dual 4X Serial Conn LVDS 4X 4X 48 Out 1GHz -BIT D/A GPIO (option 104) 68-pin Header

156 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1 GHz and 1 GHz D/A with Virtex-7 - x8 GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other board resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO

157 Model GHz and 1 GHz D/A with Virtex-7 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-7 - x8 Options: -073 XC7VX330T XC7VX690T LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7892 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in.

158 Model GHz and D/A, Virtex-7-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit D/A 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional LVDS connections the Virtex-7 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Onyx family of high performance 3U VPX boards based on the Xilinx Virtex-7. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 1 GHz 12-BIT VPX BACKPLANE 12 VIRTEX-7 VX330T or VX690T LVDS 40 VPX-P2 CONFIG FLASH Option -104 I/O Out 1 GHz -BIT D/A Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 2 x8 Gen. 2 x8 CROSSBAR SWITCH Option -105 Gigabit Serial I/O 4X Gbit 4X Gbit 4X Gbit Serial Serial Serial VPX-P1 4X 4X 4X Gbit Serial

159 Model GHz and D/A, Virtex-7-3U VPX Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 40 Gigabit Serial I/O GPIO

160 Model GHz and D/A, Virtex-7-3U VPX Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 Two x4 or one x8 on VPX P1 Yes 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

161 Model GHz and D/A, Virtex-7-3U VPX Model COTS (left) and rugged version Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit D/A 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up x4 Optional LVDS connections the Virtex-7 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Onyx family of high performance 3U VPX boards based on the Xilinx Virtex-7. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes 1 GHz and D/A converters and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A waveform playback IP module for simplifying data capture and data transfer. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock/Sync/ Gate / PPS VCXO Clock/Sync Bus D/A Clock/Sync Bus IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 24 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In 1 GHz 12-BIT VPX BACKPLANE 12 VIRTEX-7 VX330T or VX690T LVDS 48 VPX-P2 CONFIG FLASH Option -104 I/O Out 1 GHz -BIT D/A Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 2 x4 Gen. 2 x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

162 Model GHz and D/A, Virtex-7-3U VPX Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. LER Bank 3 INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 4X 4X 4X 48 Gigabit Serial I/O GPIO

163 Model GHz and D/A, Virtex-7-3U VPX Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting links up x4, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A, Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 5292 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 24 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 Two x4 or one x8 on VPX P1 Yes 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

164 New! New! New! New! New! Models & Model or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7-6U OpenVPX General Information Models and are members of the Onyx family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-7. They consist of one or two Model XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model module while the Model is a 6U board with two XMC modules rather than one. These models include one or two 1 GHz and D/A converters and four or eight banks of memory The Onyx Architecture The Pentek Onyx Architecture features Virtex-7 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition and one or two D/A waveform playback IP modules for simplifying data capture and data transfer. IP modules for memories, controllers for all data clocking and synchronization functions, test signal generars, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 24 LVDS pairs between the and the VPX P3 connecr, Model 57730; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57730; or one 4X link from each P2 and an additional 4X link between the s, Model Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One or two 1 GHz 12-bit One or two 1 GHz -bit D/A 4 or 8 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Dual-µSync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Ruggedized and conductioncooled versions available Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Block Diagram, Model Model doubles all resources except the -- Switch and provides 24 LVDS pairs from the 2nd VPX-P5 Clock/Sync Bus D/A Clock/Sync Bus VPX BACKPLANE In 1 GHz 12-BIT 12 VIRTEX-7 VX330T or VX690T Option -104 I/O LVDS 48 VPX-P3 CONFIG FLASH Out 1 GHz -BIT D/A Gen. 3 x8 Config Bus GATEXPRESS CONFIGURATION MANAGER - SWITCH Gen. 3 x8 Gen. 3 x8 VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58730

165 Models & or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7-6U OpenVPX Acquisition IP Module These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board memory or offboard host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 or 128 individual link entries can be chained gether create complex waveforms with a minimum of programming. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the s. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the s time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user. In this case, it s programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the s with new IP images. The first option is load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 The third option, typically used during development, allows the user directly load the s through JTAG using Xilinx impact. In all three -loading scenarios, GateXpress handles the hardware negotiation thereby simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without the need reset the host computer so it can rediscover the board. After the reload, the host computer simply continues see the board with the expected device ID. Converter Stages The front end accepts one or two analog HF or IF inputs on front panel SSMC connecrs with transformer coupling in one or two Texas Instruments ADS GHz, 12-bit converters. The digital outputs are delivered in the Virtex-7 s for signal processing, data capture or for routing other board resources. D/A Converter Stages These models feature one or two TI DAC5681Z 1 GHz, -bit D/As. The converters have an input sample rate of 1 GSPS, allowing them acept full rate data from the. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2- or 1/4-rate input data. Analog output is through front panel SSMC connecrs. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 4X 4X 48 Gigabit Serial I/O GPIO

166 Models & or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7-6U OpenVPX PCI Express Interface These models include an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information GHz and D/A with Virtex-7-6U VPX Two 1 GHz s and D/As, with two Virtex-7 s - 6U VPX Options: -076 XC7VX690T LVDS I/O between the and P3 connecr, Model 57730; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57730; gigabit links from each P2 connecr, Model Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple boards be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 9192 Cobalt or Onyx Synchronizer can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The Onyx architecture supports four or eight independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Specifications Model 57730: 1, 1 D/A Model 58730: 2 s, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connecrs Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus (1 or 2): 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O (1 or 2) Option -104: Provides 24 LVDS pairs between the and the VPX P3 connecr, Model 57730; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57730; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (4 or 8) Type: Size: 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm)

167 Models 72730, and or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7 - cpci Model Model General Information Models 72730, and are members of the Onyx family of high performance CompactPCI boards based on the Xilinx Virtex-7. They consist of one or two Model XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one or two 1 GHz and D/A converters and four or eight banks of memory The Onyx Architecture The Pentek Onyx Architecture features Virtex-7 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include ne or two acquisition and one or two D/A waveform playback IP modules for simplifying data capture and data transfer. IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73730; J3 connecr, Model 72730; J3 and J5 connecrs, Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across PCI/PCI-X bus One or two 1 GHz 12-bit One or two 1 GHz -bit D/A Four or eight GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization Optional LVDS connections the Virtex-7 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus I/O (Option -104) MODEL INTEACES ONLY LVDS J2 40 VIRTEX-7 CONFIG FLASH TIMING BUS Clock / Sync / Gate / PPS Config Bus VCXO PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz GATEXPRESS CONFIGURATION MANAGER x4 x4 Clock/Sync Bus D/A Clock/Sync Bus In 1 GHz 12-BIT 12 VIRTEX-7 VX330T or VX690T LVDS J3 40 CONFIG FLASH Optional I/O (Option -104) Out 1 GHz -BIT D/A Config Bus PCI BRIDGE GATEXPRESS CONFIGURATION MANAGER x4 x4 PCI PCI BRIDGE From/To Other XMC Module of Model PCI/PCI-X BUS 32/64-bit, 33/66 MHz

168 Models 72730, and Acquisition IP Module These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board memory or offboard host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 or 128 individual link entries can be chained gether create complex waveforms with a minimum of programming. 1- or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7 - cpci GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts one or two analog HF or IF input on front panel SSMC connecrs with transformer coupling in one or two Texas Instruments ADS GHz, 12-bit converters. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. D/A Converter Stage These models feature one or two TI DAC5681Z 1 GHz, -bit D/As. The converters have an input sample rate of 1 GSPS, allowing them acept full rate data from the. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connecrs. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 4X 40 I/O

169 Models 72730, and or 2-Channel 1 GHz, 1- or 2-Channel 1 GHz D/A with Virtex-7 - cpci PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73730: 32 bits only. Ordering Information GHz and D/A, Virtex-7-6U cpci GHz and D/A, Virtex-7-3U cpci Two 1 GHz and D/A, Virtex-7-6U cpci Options: -073 XC7VX330T XC7VX690T LVDS I/O between the and J2 connecr, Model 73730; J3 connecr, Model 72730; J3 and J5 connecrs, Model Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 7192 and Model 9192 Cobalt Synchronizers can drive multiple 730 µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The Onyx architecture supports four or eight independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Specifications Model or Model 73730: 1, 1 D/A Model 74730: 2 s, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connecrs Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73730; J3 connecr, Model 72730; J3 and J5 connecrs, Model Banks (1 or 2) Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73730: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

170 Model GHz and 1 GHz D/A, Virtex-7 - AMC Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit D/A 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-7 for cusm I/O General Information Model is a member of the Onyx family of high performance AMC modules based on the Xilinx Virtex-7. A highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and D/A converters and four banks of memory. In addition supporting PCI Express Gen.3 as a native interface, the Model includes a front panel general-purpose connecr for application-specific I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition and a D/A wave- Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In D/A Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 AMC Ports 4 11 form playback IP module for simplifying data capture and data transfer. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs a front panel connecr with 24 pairs of LVDS connections the for cusm I/O. In 1 GHz 12-BIT 12 IPMI LER VIRTEX-7 VX330T or VX690T RS-232 Front Panel LVDS Out 1 GHz -BIT D/A GPIO (option 104) Front Panel

171 Model GHz and 1 GHz D/A, Virtex-7 - AMC Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The Model facryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. Bank 1 LER Bank 1 Bank 2 Bank 2 Bank 3 from D/A loopback INPUT MULTIPLEXER PACKING META ACQUISITION IP MODULE VIRTEX-7 FLOW DETAIL Bank 4 Bank 3 The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. D/A Converter Stage The features a TI DAC5681Z 1 GHz, -bit D/A. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connecr. LER INTEACE TEST SIGNAL Bank 4 D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE (supports user installed IP) 8X 48 GPIO

172 Model GHz and 1 GHz D/A, Virtex-7 - AMC AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Ordering Information GHz and D/A, Virtex-7 - AMC Options: -073 XC7VX330T XC7VX690T LVDS I/O front pannel connecr Clocking and Synchronization Two internal timing buses provide either a single clock or two different clock rates the and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives a sample clock either from the front panel SSMC connecr or from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this latter mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock phase-lock the VCXO. Either clock source (front panel or VCXO) can be used directly or can be divided independently by 2, 4, 8, or provide different lower frequency and D/A clocks. A pair of front panel µsync connecrs allows multiple modules be synchronized. They accept CML inputs that drive the board s sync and gate/trigger signals. The Pentek Model 5692 and Model 9192 Cobalt Synchronizers can drive multiple µsync connecrs enabling large, multichannel synchronous configurations. Also, an LVTTL external gate/trigger input is accepted on a front panel SSMC connecr. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an data transient capture mode and D/A waveform playback mode. In addition the facry-installed functions, cusm user- installed IP within the can take advantage of the memories for many other purposes. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phaselocked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and D/A clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs a front panel connecr with 24 LVDS pairs the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Contact Pentek for availability of rugged and conduction-cooled versions

173 Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC General Information Model is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In addition, IP modules for Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connecr with 24 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support serial procols. In In VIRTEX-7 VX330T or VX690T 4X 4X 48 Gigabit Serial I/O (option 105) P XMC LVDS GPIO (option 104) P14 PMC

174 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X Gigabit Serial I/O 4X 4X 48 GPIO Bank 3 Bank 4

175 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7 - XMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple modules be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 7192 highspeed sync module drive the sync bus. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

176 Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - x8 General Information Model is a member of the Onyx family of high-performance modules based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In addition, IP modules for memories, a controller for all data clocking Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 connects 24 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. In In VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) LVDS 4X 4X 48 Dual 4X Serial Conn GPIO (option 104) 68-pin Header

177 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - x8 DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X Gigabit Serial I/O 4X 4X 48 GPIO Bank 3 Bank 4

178 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - x8 Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming.. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards (Models 78xxx). It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7 - XMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple boards be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 7892 highspeed sync board drive the sync bus. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Connects 24 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in.

179 Model Model COTS (left) and rugged version Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX General Information Model is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In addition, IP modules for Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In VPX BACKPLANE In VIRTEX-7 VX330T or VX690T LVDS 40 VPX-P2 CONFIG FLASH Option -104 I/O Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 2 x8 Gen. 2 x8 CROSSBAR SWITCH Option -105 Gigabit Serial I/O 4X 4X 4X Gbit 4X Gbit 4X Gbit 4X Gbit Serial Serial Serial Serial VPX-P1

180 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X Gigabit Serial I/O 4X 4X 40 GPIO Bank 3 Bank 4

181 Model Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple boards be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 5392 highspeed sync board drive the sync bus. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel : 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 Two x4 or one x8 on VPX P1 Yes 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x4 or x8 Lowest Price 24 pairs on VPX P2 Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

182 Model Model COTS (left) and rugged version Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x4 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX General Information Model is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In addition, IP modules for Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. In VPX BACKPLANE In VIRTEX-7 VX330T or VX690T LVDS 40 VPX-P2 CONFIG FLASH Option -104 I/O Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 2 x4 Gen. 2 x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

183 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 4X Gigabit Serial I/O 4X 4X 40 GPIO Bank 3 Bank 4

184 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7-3U VPX Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7-3U VPX Options: -073 XC7VX330T XC7VX690T LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1 Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple boards be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 5292 highspeed sync board drive the sync bus. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

185 Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC General Information Model is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In addition, IP modules for Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connecr with 24 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with dual 4X gigabit links the support serial procols. In In VIRTEX-7 VX330T or VX690T 4X 4X 48 Gigabit Serial I/O (option 105) P XMC LVDS GPIO (option 104) P14 PMC

186 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X Gigabit Serial I/O 4X 4X 48 GPIO Bank 3 Bank 4

187 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - XMC Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7 - XMC Options: -073 XC7VX330T XC7VX690T LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the module. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple modules be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 7192 highspeed sync module drive the sync bus. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

188 Models 72741, and or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - cpci Model Model General Information Models 72741, and are members of the Onyx family of high performance CompactPCI boards based on the Xilinx Virtex-7. They consist of one or two Model XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit converters, four or eight banks of memory, and one or two wideband DDCs The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions of these models include one or two acquisition IP modules and one or two wideband DDCs. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73741; J3 connecr, Model 72741; J3 and J5 connecrs, Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDCs (Digital Downconverters) 4 or 8 GB of µsync clock/sync bus for multiboard synchronization Optional LVDS connections the Virtex-7 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus I/O (Option -104) MODEL INTEACES ONLY LVDS J2 40 VIRTEX-7 CONFIG FLASH Config Bus PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz GATEXPRESS CONFIGURATION MANAGER x4 x4 In In VIRTEX-7 VX330T or VX690T LVDS J3 40 CONFIG FLASH Optional I/O (Option -104) Config Bus PCI BRIDGE GATEXPRESS CONFIGURATION MANAGER x4 x4 PCI PCI BRIDGE From/To Other XMC Module of Model PCI/PCI-X BUS 32/64-bit, 33/66 MHz

189 Models 72741, and Acquisition IP Module These models feature one or two Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the, or a test signal generar. The IP modules have associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - cpci DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE Bank 1 Bank 2 4X GPIO 40 Bank 3 Bank 4

190 Models 72741, and or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - cpci Resources The Onyx architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73741: 32 bits only. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, with Wideband DDC, Virtex-7-6U cpci Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, with Wideband DDC, Virtex-7-3U cpci Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit, with Wideband DDC, Virtex-7 s - 6U cpci Options: -073 XC7VX330T XC7VX690T LVDS I/O between the and J2 connecr, Model 73741; J3 connecr, Model 72741; J3 and J5 connecrs, Model on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boards. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. Clocking and Synchronization These models accept a 1.8 GHz dualedge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple boards be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two boards can be synchronized with a simple cable. For larger systems, multiple boards can be synchronized using the Models 7292, 7392 or 7492 high-speed sync boards drive the sync bus. Specifications Model or Model 73741: One Model 74741: Two s Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connecrs Converters (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters (2 or 4) Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Sources (1 or 2) Front panel SSMC connecr Timing Bus (1 or 2) 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input (1 or2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Provides 20 LVDS pairs between the and the J2 connecr, Model 73741; J3 connecr, Model 72741; J3 and J5 connecrs, Model Banks (1 or 2) Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73741: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

191 Model Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or twochannel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional LVDS connections the Virtex-7 for cusm I/O 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - AMC General Information Model is a member of the Onyx family of high-performance AMC modules based on the Xilinx Virtex-7. A highspeed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional front-panel connection the Virtex-7 for cusm I/O. The Onyx Architecture Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 s from Xilinx. As the central feature of the board architecture, the has access all data and control paths, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. The facry-installed functions include an acquisition IP module and a programmable digital downconverter. In Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 AMC Ports 4 11 addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs a front panel connecr with 24 pairs of LVDS connections the for cusm I/O. In IPMI LER In VIRTEX-7 VX330T or VX690T RS-232 Front Panel LVDS GPIO (option 104) Front Panel

192 Model Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - AMC DDC IP Cores Within the is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. VIRTEX-7 FLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW from GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred from INPUT MULTIPLEXER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW TEST SIGNAL META MEM META LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X GPIO 48 Bank 3 Bank 4

193 Model Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit, w/ Wideband DDC, Virtex-7 - AMC Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel data capture, tagging and streaming. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Ordering Information Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit with Wideband DDC, Virtex-7 - AMC Options: -073 XC7VX330T XC7VX690T LVDS I/O front panel connecr Contact Pentek for availability of rugged and conduction-cooled versions on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple boardss. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other board resources. Clocking and Synchronization The accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connecr. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel µsync bus connecr allows multiple boards be synchronized, ideal for multichannel systems. The µsync bus includes gate, reset, and in and out reference clock signals. Two s can be synchronized with a simple cable. For larger systems, multiple s can be synchronized using the Model 5692 highspeed sync board drive the sync bus. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs a front panel connecr with 24 LVDS pairs the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in.

194 Model 710 LVDS Digital I/O with Virtex-6 - XMC Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board General Information Model 710 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6. This digital I/O module provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model 710 includes a general-purpose connecr for application-specific I/O Banks1& Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 Option 5 80-pin Front Panel Connecr LVDS Clock The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The 710 facry-installed functions include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, a controller for all data clocking, a test signal generar, and a interface complete the facry-installed functions and enable the 710 operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O the carrier board. Option -105 installs the P XMC connecr with one 8X or two 4X gigabit links the support serial procols. Config FLASH 64 MB Data Valid LVDS 40 8X 4X 4X Optional GPIO Data Suspend x8 Optional Gigabit Serial I/O PMC P14 XMC P15 XMC P

195 Model 710 LVDS Digital I/O with Virtex-6 - XMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information 710 LVDS Digital I/O with Virtex-6 - XMC Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through P14 connecr -105 Gigabit serial I/O through P connecr -155* Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions Acquisition IP Module The module can be configured for digital input mode by setting a jumper on the board. In this case, the module accepts input data Clock and input Data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The module can optionally generate a Data Suspend output signal indicating that the 710 is no longer capable of accepting data. The module accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module The module can be configured for digital output mode by setting a jumper on the board. In this case, the module generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The module can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. XMC Interface The Model 710 complies with the VITA 42.0 XMC specification. Each of two connecrs provides multilane gigabit serial interfaces with up a 6 GHz bit clock. With dual XMC connecrs, the 710 supports x4 or x8 on the primary P15 XMC connecr. The secondary P XMC connecr is used for dual 4X or single 8X user-installed gigabit serial interfaces, such as Aurora, and serial RapidIO. PCI Express Interface The Model 710 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers and from the module. Resources The 710 hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two 4X gigabit serial links the Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in PC Development System See 8266 Datasheet for Options

196 Model LVDS Digital I/O with Virtex-6 - x8 Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board General Information Model is a member of the Cobalt family of high-performance boards based on the Xilinx Virtex-6. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model includes a general-purpose connecr for application-specific I/O Banks1& Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 Option 5 80-pin Front Panel Connecr LVDS Clock The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, a controller for all data clocking, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board. Config FLASH 64 MB Data Valid LVDS Data Suspend 40 8X 4X 4X Optional GPIO x8 Optional Serial I/O 68-pin Header Dual 4X Serial Conn x8 PCI Express

197 Model LVDS Digital I/O with Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt and Onyx PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information LVDS Digital I/O with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -155* Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Acquisition IP Module The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the is no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module The board can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105: Connects two 4X gigabit serial links from the on XMC P two 4X gigabit serial connecrs along the p edge of the board Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in PC Development System See 8266 Datasheet for Options

198 Model LVDS Digital I/O with Virtex-6-3U VPX Model COTS (left) and rugged version Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model includes a general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, a controller for all data clocking, a test Banks1& Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 Option 5 80-pin Front Panel Connecr LVDS Clock VPX BACKPLANE signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Config FLASH 64 MB Data Valid LVDS 40 VPX-P2 Data Suspend Option -104 I/O 8X x8 4X Gbit Serial Option -105 Gigabit Serial I/O CROSSBAR SWITCH 4X Gbit Serial VPX-P1 4X 4X Gbit Serial 4X 4X Gbit Serial

199 Model LVDS Digital I/O with Virtex-6-3U VPX Fabric-Transparent Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output preemphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information LVDS Digital I/O with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Acquisition IP Module The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the is no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module The board can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 Two x4 or one x8 on VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

200 Model LVDS Digital I/O with Virtex-6-3U VPX Model COTS (left) and rugged version Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model includes a general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, a controller for all data clocking, a test Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks 1 & 2 Banks 3 & 4 Option 5 80-pin Front Panel Connecr LVDS Clock VPX BACKPLANE signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Config FLASH 64 MB Data Valid LVDS 40 VPX-P2 Data Suspend Option -104 I/O 4X x4 VPX-P1 4X 4X Option -105 Gigabit Serial I/O

201 Model LVDS Digital I/O with Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt and Onyx VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information LVDS Digital I/O with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O VPX P2-105 Gigabit serial I/O VPX P1-155* Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Acquisition IP Module The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the is no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module The board can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 connection, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105: Provides one 8X or two 4X gigabit links between the and the VPX P1 connecr support serial procols. Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

202 New! New! New! New! New! Models and Features Model or 64 bits of LVDS digital I/O One or two LVDS clocks One or two LVDS data valid One or two LVDS data suspend Supports LXT and SXT Virtex-6 S One or two DMA controllers move data and from system memory Up 2 or 4 GB of PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board Ruggedized and conductioncooled versions available Single or Dual LVDS Digital I/O with Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high-performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 710 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 710 module while the Model is a 6U board with two XMC modules rather than one. These models include one or two general-purpose connecrs for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions of these models include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, controllers for all data clocking, test signal generars, and a interface complete the facry-installed functions Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks 1&2 Banks 3&4 Option 5 Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 VPX BACKPLANE 80-pin Front Panel Connecr LVDS Clock and enable these models operate as complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57610; P3 and P5, Model Option -105 supports serial procalls by providing a 4X gigabit link between the and VPX P2, Model 57610; or one 4X link from each P2 and an additional 4X link between the s, Model Config FLASH 64 MB Option -104 I/O Data Valid LVDS VPX-P3 Data Suspend 40 8X Gen. 2 x8 Gen. 2 x8 - SWITCH VPX-P1 Option -105 Gigabit Serial I/O 4X VPX-P2 4X From/To Other XMC Module of Model 58610

203 Models and Single or Dual LVDS Digital I/O with Virtex-6-6U OpenVPX Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Single LVDS Digital I/O with Virtex-6-6U VPX Dual LVDS Digital I/O with two Virtex-6 s - 6U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and P3 connecr, Model 57610; P3 and P5 connecrs, Model Gigabit link between the and P2 connecr, Model 57610; gigabit links from each P2 connecr, Model * Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Acquisition IP Modules These models can be configured for digital input mode by the setting of one or two jumpers. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that these models are no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Modules These models can be configured for digital output mode by the setting of one or two jumpers. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. One or two linked-list controllers allow users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 or 128 individual link entries can be chained gether create complex output patterns with minimum programming. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The hardware architecture supports up four or eight independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 4 GB. Specifications Model 57610: Single LVDS Digital I/O Model 58610: Dual LVDS Digital I/O Front Panel Input/Output (1 or 2) Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57610; P3 and P5, Model Option -105: Supports serial procols by providing a 4X gigabit link between the and VPX P2, Model 57610; or one 4X link from each P2 and an additional 4X link between the s, Model Banks (1 or 2) Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options

204 Models 72610, and Single or Dual LVDS Digital I/O with Virtex-6 - cpci Model Model General Information Models 72610, and are members of the Cobalt family of high-performance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 710 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 710 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models include one or two general-purpose connecrs for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions of these models include 32-bit acquisition and generation IP modules, support either input or output functions, respectively. IP modules for memories, controllers for all data clocking, a test signal generar, and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73610; J3 connecr, Model 72610; J3 and J5 connecrs, Model Features 32 or 64 bits of LVDS digital I/O One or two LVDS clocks One or two LVDS data valid One or two LVDS data suspend Supports LXT and SXT Virtex-6 S One or two DMA controllers move data and from system memory Up 2 or 4 GB of Optional LVDS connections the Virtex-6 for cusm I/O the carrier board Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge MODEL INTEACES ONLY LVDS VIRTEX-6 40 Optional PCI I/O BRIDGE (Option -104) Banks1& Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 Option 5 80-pin Front Panel Connecr LVDS Clock Config FLASH 64 MB Data Valid LVDS Data Suspend 40 4X From/To Other x4 XMC Module of MODEL PCI BRIDGE Optional I/O (Option -104) PCI PCI BRIDGE J2 PCI/PCI-X BUS 32-bit, 33/66 MHz J3 PCI/PCI-X BUS 32/64-bit, 33/66 MHz

205 Models 72610, and Single or Dual LVDS Digital I/O with Virtex-6 - cpci Ordering Information Single LVDS Digital I/O with Virtex-6-6U cpci Single LVDS Digital I/O with Virtex-6-3U cpci Dual LVDS Digital I/O with Virtex-6 s - 6U cpci Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O between the and J2 connecr, Model 73610; J3 connecr, Model 72610; J3 and J5 connecrs, Model * Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Acquisition IP Module These models can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that these models are no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module These models can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73610: 32 bits only. Resources The hardware architecture supports up four or eight independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of for Models and or a tal of 4 GB for Model Specifications Model or Model 73610: Single LVDS Digital I/O Model 74610: Dual LVDS Digital I/O Front Panel Input/Output (1 or 2) Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73610; J3 connecr, Model 72610; J3 and J5 connecrs, Model Banks (1 or 2) Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73610: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board

206 Model LVDS Digital I/O with Virtex-6 - AMC Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional LVDS connections the Virtex-6 for cusm I/O the carrier board General Information Model is a member of the Cobalt family of high-performance AMC boards based on the Xilinx Virtex-6. This digital I/O board provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model includes a general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions for data flow and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an IP (intellectual property) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s interface. The facry-installed functions include 32-bit acquisition and generation IP modules, support either input or output functions, respectively Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks 1&2 Banks 3&4 Option 5 80-pin Front Panel Connecr LVDS Clock IP modules for memories, a controller for all data clocking, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T LX240T, or SX315T. The SXT part features up 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. Config FLASH 64 MB Data Valid x8 AMC Ports 4 11 Data Suspend 8X IPMI LER RS-232 Front Panel LVDS 40 GPIO (option 104) Front Panel

207 Model LVDS Digital I/O with Virtex-6 - AMC Ordering Information LVDS Digital I/O with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -104 LVDS I/O through 68-pin ribbon cable connecr -105 Gigabit serial I/O through two 4X p edge connecrs -155* Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) * This option is always required Acquisition IP Module The board can be configured for digital input mode by the setting of a jumper. In this case, the board accepts input data Clock and input data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The board can optionally generate a Data Suspend output signal indicating that the is no longer capable of accepting data. The board accepts 32 bits from the front panel connecr or from an on-board test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. banks are supported with DMA engines for easily moving input data through the interface. Generation IP Module The board can be configured for digital output mode by the setting of a jumper. In this case, the board generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The board can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Parameters including length of table, delay from software trigger, table repetition, etc. can be programmed for entry. Up 64 individual link entries can be chained gether create complex output patterns with minimum programming. AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facry-installed functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Contact Pentek for availability of rugged and conduction-cooled versions

208 Model 7811 Quad Serial FPDP Interface with Virtex-6 - General Information Model 7811 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The 7811 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 7811 serves as a flexible platform for developing and deploying cusm processing IP. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for data routing and flow control, CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable the 7811 operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 can be populated with two different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T or SX315T. The SX315T part features 1,344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LX130T can be installed. Features Complete Serial FPDP solution Fully compliant with VITA 17.1specification Fibre optic or copper serial interfaces PCI Express interface up x8 CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE VIRTEX-6 LX130T, LX240T or SX315T Config FLASH MB 8X x8

209 Model 7811 Quad Serial FPDP Interface with Virtex-6 - Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Serial FPDP Interface The 7811 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces or copper interfaces the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. PCI Express Interface The Model 7811 includes an industrystandard interface fully compliant with PCI Express bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the board. Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: SFP+ Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in. SERIALFPDPRX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO 32K x 32 FIFO Ordering Information 7811 Quad Serial FPDP Interface with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -280 Copper serial interfaces -281 Multi-mode optical serial interfaces CH 1 TX RX CH 2 TX RX CH 3 TX DISPARITY CALCULATE M U X SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO Copy mode data path K x 32 FIFO INTEACE 8X 8266 PC Development System See 8266 Datasheet for Options RX CH 4 TX SERIALFPDPCHANNEL4 VIRTEX-6 FLOW DETAIL

210 Model 711 Quad Serial FPDP Interface with Virtex-6 - XMC Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O General Information Model 711 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 711 serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express as a native interface, the Model 711 includes a general purpose connecr for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, VIRTEX-6 LX240T, SX315T or SX475T CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable the 711 operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE LVDS Banks 1&2 Banks 3&4 option 155 option 5 Config FLASH 64 MB 8X x8 40 GPIO (option -104) P15 XMC P14 PMC

211 Model 711 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information 711 Quad Serial FPDP Interface with Virtex-6 - XMC Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O through P14 connecr -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces Quad Serial FPDP Interface with Virtex-6 - XMC Serial FPDP Interface The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The 711 architecture supports up four independent memory banks of. Each memory is deep and an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model 711 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the module. CH 1 RX CH 1 TX RX CH 2 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in. optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 8X Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options RX CH 3 TX RX CH 4 TX SERIALFPDPCHANNEL3 SERIALFPDPCHANNEL4 optional buffer optional buffer VIRTEX-6 FLOW DETAIL

212 Model Quad Serial FPDP Interface with Virtex-6 - x8 General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express as a native interface, the Model includes a general purpose connecr for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE VIRTEX-6 LX240T, SX315T or SX475T LVDS FIBER OPTIC or COPPER INTEACE Banks 1&2 Banks 3&4 option 155 option 5 Config FLASH 64 MB 40 Optional GPIO 8X x8 68-pin Header x8 PCI Express

213 Model Quad Serial FPDP Interface with Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Serial FPDP Interface The is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the board. Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in. Ordering Information Quad Serial FPDP Interface with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O through 68-pin ribbon cable connecr -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces CH 1 RX CH 1 TX RX CH 2 TX RX CH 3 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 8X 8266 PC Development System See 8266 Datasheet for Options RX CH 4 TX SERIALFPDPCHANNEL4 optional buffer VIRTEX-6 FLOW DETAIL

214 Model Quad Serial FPDP Interface with Virtex-6 - x8 General Information Model is a member of the Cobalt family of high performance boards based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express as a native interface, the Model includes a general purpose connecr for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE VIRTEX-6 LX240T, SX315T or SX475T LVDS FIBER OPTIC or COPPER INTEACE Banks 1&2 Banks 3&4 option 155 option 5 Config FLASH 64 MB 40 Optional GPIO 8X x8 68-pin Header x8 PCI Express

215 Model Quad Serial FPDP Interface with Virtex-6 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Serial FPDP Interface The is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the board. Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Connects 20 pairs of LVDS signals from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half-length card, 4.38 in. x 7.13 in. Ordering Information Quad Serial FPDP Interface with Virtex-6 - Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O through 68-pin ribbon cable connecr -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces CH 1 RX CH 1 TX RX CH 2 TX RX CH 3 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 8X 8266 PC Development System See 8266 Datasheet for Options RX CH 4 TX SERIALFPDPCHANNEL4 optional buffer VIRTEX-6 FLOW DETAIL

216 Model Quad Serial FPDP Interface with Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express over the 3U VPX backplane, the Model includes a general purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and 32 VIRTEX-6 LX240T, SX315T or SX475T Config FLASH 64 MB a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE Banks 1&2 Banks 3&4 option 155 option 5 FIBER OPTIC or COPPER INTEACE LVDS 40 Option -104 I/O FIBER OPTIC or COPPER INTEACE 8X x8 CROSSBAR SWITCH VPX BACKPLANE VPX-P2 4X Gbit Serial 4X Gbit Serial VPX-P1 4X Gbit Serial 4X Gbit Serial

217 Model Quad Serial FPDP Interface with Virtex-6-3U VPX Serial FPDP Interface The is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the board. Crossbar Switch The features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). optional buffer SERIALFPDPRX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO 32K x 32 FIFO CH 1 TX DISPARITY CALCULATE M U X SERIALFPDPTX ENGINE OPTIONAL CRC 64 x 32 COPY MODE RX FIFO PACKET CONSTRUCT RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO Copy mode data path K x 32 FIFO SERIAL FPDP CHANNEL 1 optional buffer INTEACE 8X RX CH 2 TX SERIAL FPDP CHANNEL 2 optional buffer RX CH 3 TX SERIALFPDPCHANNEL3 optional buffer RX CH 4 TX SERIALFPDPCHANNEL4 VIRTEX-6 FLOW DETAIL

218 Model Quad Serial FPDP Interface with Virtex-6-3U VPX Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Quad Serial FPDP Interface with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O VPX P2-155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 53xxx and the 52xxx. For more information on a 52xxx product, please refer the product datasheet. The table below provides a comparison of their main features. Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power VPX Family Comparison 52xxx No VPX P1 Two x4 or one x8 on VPX P1 Yes 3U VPX One XMC 20 pairs on VPX P2 53xxx Yes VPX P1 or P2 width x4 x8 Lowest Price Yes Two x4 or one x8 on VPX P1 or P2 No No Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options

219 Model Quad Serial FPDP Interface with Virtex-6-3U VPX Model COTS (left) and rugged version Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x4 LVDS connections the Virtex-6 for cusm I/O 3U VPX form facr provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available General Information Model is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express over the 3U VPX backplane, the Model includes a general-purpose connecr for application-specific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and 32 VIRTEX-6 LX240T, SX315T or SX475T Config FLASH 64 MB a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE Banks 1&2 Banks 3 & 4 option 155 option 5 FIBER OPTIC or COPPER INTEACE LVDS 40 Option -104 I/O FIBER OPTIC or COPPER INTEACE 4X x4 VPX BACKPLANE VPX-P2 VPX-P1

220 Model PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x4, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the board. Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Quad Serial FPDP Interface with Virtex-6-3U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O VPX P2-155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Quad Serial FPDP Interface with Virtex-6-3U VPX Serial FPDP Interface The is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T CH 1 RX CH 1 TX RX CH 2 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIAL FPDP RX ENGINE OPTIONAL CRC CHECK SERIAL FPDP TX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 2K x 32 RX FIFO VIRTEX-6 FLOW DETAIL Cusm I/O Option -104: Provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) VPX Families Pentek offers two families of 3U VPX products: the 52xxx and the 53xxx. For more information on a 53xxx product, please refer the product datasheet. The table below provides a comparison of their main features. optional buffer RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer optional buffer RX CH 3 SERIAL FPDP CHANNEL 3 TX optional buffer RX CH 4 SERIAL FPDP CHANNEL 4 TX Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power Copy mode data path 32K x 32 FIFO K x 32 FIFO VPX Family Comparison 52xxx No VPX P1 3U VPX One XMC INTEACE 53xxx 4X Yes VPX P1 or P2 width x4 x8 Lowest Price Two x4 or one x8 on VPX P1 Yes Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

221 New! New! New! New! New! Models and Model Quad or Octal Serial FPDP Interface with Virtex-6-6U OpenVPX General Information Models and are members of the Cobalt family of high performance 6U OpenVPX boards based on the Xilinx Virtex-6. They consist of one or two Model 711 XMC modules mounted on a VPX carrier board. Model is a 6U board with one Model 711 module while the Model is a 6U board with two XMC modules rather than one. These models are fully compatible with the VITA 17.1 Serial FPDP specification. Their built-in data transfer features make them complete turnkey solutions. For users who require application-specific functions, they serve as flexible platforms for developing and deploying cusm processing IP. The Cobalt Architecture The Pentek Cobalt Architecture features one or two Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable these models operate as complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57611; P3 and P5, Model CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE Features Four or eight channels of Serial FPDP interface Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces One or two Virtex-6 s Up 2 or 4 GB of PCI Express interface up x8 Optional LVDS connections the Virtex-6 for cusm I/O Ruggedized and conductioncooled versions available 32 VIRTEX-6 LX240T, SX315T or SX475T Banks 1&2 Banks 3&4 option 155 option 5 Block Diagram, Model Model doubles all resources except the -- Switch and provides 20 LVDS pairs from the 2nd VPX-P5 Config FLASH 64 MB VPX BACKPLANE Option -104 I/O LVDS VPX-P3 40 8X Gen.2x8 - SWITCH VPX-P1 From/To Other XMC Module of Model 58611

222 Models and Model 8264 The Model 8264 is a fullyintegrated development system for Pentek Cobalt and Onyx 6U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Quad Serial FPDP Interface with Virtex-6-6U VPX Octal Serial FPDP Interface with two Virtex-6 s - 6U VPX Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O between the and P3 connecr, Model 57611; P3 and P5 connecrs, Model Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces Contact Pentek for availability of rugged and conduction-cooled versions 8264 VPX Development System. See 8264 Datasheet for Options Quad or Octal Serial FPDP Interface with Virtex-6-6U OpenVPX Serial FPDP Interface These models are fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the boards can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four or eight independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface These models include an industrystandard interface fully compliant with PCI Express Gen. 1 and 2 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. CH 1 RX CH 1 TX RX CH 2 TX RX CH 3 TX RX CH 4 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 SERIALFPDPCHANNEL4 optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer VIRTEX-6 FLOW DETAIL Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 or 8 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Arrays: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Provides 20 LVDS pairs between the and the VPX P3 connecr, Model 57611; P3 and P5, Model Option 155 or 5: Two memory banks, 400 MHz DDR PCI Express Interface PCI Express Bus: Gen. 1 or 2: x4 or x8 Environmental: Level L1 & L2 air-cooled; Level L3 ruggedized, conduction-cooled Size: in. x in. (100 mm x mm) optional buffer optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 8X

223 Models 72611, and Quad or Octal Serial FPDP Interface with Virtex-6 - cpci Model Model General Information Models 72611, and are members of the Cobalt family of highperformance CompactPCI boards based on the Xilinx Virtex-6. They consist of one or two Model 711 XMC modules mounted on a cpci carrier board. Model is a 6U cpci board while the Model is a 3U cpci board; both are equipped with one Model 711 XMC. Model is a 6U cpci board with two XMC modules rather than one. These models are fully compatible with the VITA 17.1 Serial FPDP specification. Their built-in data transfer features make them complete turnkey solutions. For users who require application-specific functions, they serve as flexible platforms for developing and deploying cusm processing IP. The Cobalt Architecture The Pentek Cobalt Architecture features one or two Virtex-6 s. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, CRC support, advanced DMA engines, and a cpci interface complete the facry-installed functions and enable these models operate as a complete turnkey solutions without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 provides 20 LVDS pairs between the and the J2 connecr, Model 73611; J3 connecr, Model 72611; J3 and J5 connecrs, Model Features Four or eight channels of Serial FPDP interface Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces One or two Virtex-6 s Up 2 or 4 GB of LVDS connections the Virtex-6 for cusm I/O Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge MODEL INTEACES ONLY LVDS J2 VIRTEX-6 40 Optional I/O (option 104) PCI BRIDGE PCI/PCI-X BUS 32-bit, 33/66 MHz 32 CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE VIRTEX-6 LX240T, SX315T or SX475T FIBER OPTIC or COPPER INTEACE Banks1&2 Banks3&4 option 155 option 5 Config FLASH 64 MB FIBER OPTIC or COPPER INTEACE LVDS 40 x4 FIBER OPTIC or COPPER INTEACE 4X PCI BRIDGE From/To Other XMC Module of MODEL PCI PCI BRIDGE J3 PCI/PCI-X BUS 32/64-bit, 33/66 MHz

224 Models 72611, and Ordering Information Quad Serial FPDP Interface with Virtex-6-6U cpci Quad Serial FPDP Interface with Virtex-6-3U cpci Octal Serial FPDP Interface with Virtex-6-6U cpci Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O between the and J2 connecr, Model 73611; J3 connecr, Model 72611; J3 and J5 connecrs, Model Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces Quad or Octal Serial FPDP Interface with Virtex-6 - cpci Serial FPDP Interface These models are fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the boards can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four or eight independent memory banks of. Each memory is deep and an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and from the board. Data widths of 32 or 64 bits (32 bits only, Model 73611) and data rates of 33 and 66 MHz are supported. CH 1 RX CH 1 TX RX CH 2 TX RX CH 3 TX RX CH 4 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 SERIALFPDPCHANNEL4 optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer VIRTEX-6 FLOW DETAIL Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 or 8 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: provides 20 LVDS pairs between the and the J2 connecr, Model 73611; J3 connecr, Model 72611; J3 and J5 connecrs, Model Option 155 or 5: Two memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32- or 64-bit at 33 or 66 MHz Model 73611: 32-bit at 33 or 66 MHz Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci board optional buffer optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 4X

225 Model Quad Serial FPDP Interface with Virtex-6 - AMC Features Complete Serial FPDP solution Fully compliant with VITA 17.1 specification Fiber optic or copper serial interfaces Up 2 GB of PCI Express interface up x8 AMC.1 compliant IPMI 2.0 compliant MMC (Module Management Controller) Optional front panel LVDS connections the Virtex-6 for cusm I/O General Information Model is a member of the Cobalt family of high-performance AMC modules based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing Serial FPDP data converter boards or as a chassis--chassis data link. The is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express Gen. 2 as a native interface, the Model includes a front panel general-purpose connecr for applicationspecific I/O. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6. All of the board s data and control paths are accessible by the, enabling facry-installed functions including data transfer and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. IP modules for memories, controllers for data routing and flow control, 32 VIRTEX-6 LX240T, SX315T or SX475T CRC support, advanced DMA engines, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 The Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX240T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lowercost LXT can be installed. Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O. CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE Config FLASH 64 MB FIBER OPTIC or COPPER INTEACE 8X IPMI LER FIBER OPTIC or COPPER INTEACE LVDS 40 Banks 1&2 Banks 3&4 option 155 option 5 x8 RS-232 GPIO (option 104) AMC Ports411 Front Panel Front Panel

226 Model Quad Serial FPDP Interface with Virtex-6 - AMC AMC Interface The Model complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). Serial FPDP Interface The is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multi-mode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Resources The architecture supports up four independent memory banks of. Each memory is deep and an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting links up x8, the interface includes eight DMA controllers. Each of the four Serial FPDP channels includes dedicated DMA engines for transmit and receive for efficient transfers and from the module. Specifications Front Panel Serial FPDP Inputs/Outputs Number of Connecrs: 4 Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs a front panel connecr with 20 LVDS pairs the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 AMC Interface Type: AMC.1 Module Management: IPMI Version 2.0 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Ordering Information Quad Serial FPDP Interface with Virtex-6 - AMC Options: -062 XC6VLX240T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O through front panel connecr -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) -280 Copper serial interfaces -281 Multi-mode optical serial interfaces CH 1 RX CH 1 TX RX CH 2 TX RX CH 3 TX PACKET DECONSTRUCT DISPARITY CALCULATE M U X SERIALFPDPRX ENGINE OPTIONAL CRC CHECK SERIALFPDPTX ENGINE 64 x 32 COPY MODE RX FIFO OPTIONAL CRC PACKET CONSTRUCT SERIAL FPDP CHANNEL 1 SERIAL FPDP CHANNEL 2 SERIALFPDPCHANNEL3 optional buffer 2K x 32 RX FIFO RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO optional buffer optional buffer optional buffer Copy mode data path 32K x 32 FIFO K x 32 FIFO INTEACE 8X Contact Pentek for availability of rugged and conduction-cooled versions RX CH 4 TX SERIALFPDPCHANNEL4 VIRTEX-6 FLOW DETAIL

227 New! New! New! New! New! Model 5973 Features VITA-57.1 FMC site offers access a wide range of possible I/O Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across 4 GB of PCI Express (Gen. 1, 2 and 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 3U OpenVPX Virtex-7 Processor and FMC Carrier General Information The Flexor Model 5973 is a high-performance 3U OpenVPX board based on the Xilinx Virtex-7. As a stand-alone processor board, it provides an ideal development and deployment platform for demanding signal-processing applications. The 5973 includes a VITA-57.1 FMC site providing access a wide range of I/O options. When combined with any of Pentek s analog interface FMCs, it becomes a complete multichannel data conversion and processing subsystem suitable for connection IF, HF or ports of a communications or radar system. The 5973 architecture includes an optional built-in gigabit serial optical interface. Up 12 high-speed duplex optical lanes are available on an MTP connecr. With the installation of a serial procol in the, this interface enables a high-bandwidth connection between 5973s mounted in the same chassis or even over extended distances between them. Board Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the main board and the FMC, enabling facry-installed functions That Include data multiplexing, channel selection, data packing, gating, triggering and memory control. CONFIG FLASH VPX-P0 Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 VPX-P1 4X Gigabit Serial I/O LVDS LVDS The architecture organizes the as a container for data-processing applications where each function exists as an intellectual property (IP) module. When integrated with a Pentek FMC, the 5973 is delivered with facry-installed applications ideally matched the board s analog or digital interfaces. These can include acquisition and D/A waveform playback engines for simplifying data capture and playback. Data tagging and metadata packet generation, in conjunction with powerful linked- list DMA engines, provide a streamlined interface for moving data on and off the board and identifying data packets with channel, timing and sample count information. IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the 5973 and its installed FMC operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. FMC CONNECTOR 0 VIRTEX-7 VX330T or VX690T pairs LVDS GPIO VPX-P2 (½) 10X VPX BACKPLANE 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

228 Model U OpenVPX Virtex-7 Processor and FMC Carrier Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. FMC Product Combinations If you wish purchase this FMC Carrier in combination with an FMC module, please see: FlexorSet Model FlexorSet Model FlexorSet Model FlexorSet Model Ordering Information U OpenVPX Virtex-7 Processor and FMC Carrier Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X optical interface Contact Pentek for availability of rugged and conduction-cooled versions Xilinx Virtex-7 The 5973 can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Sixteen pairs of LVDS connections are optionally provided between the and the VPX P2 connecr for cusm I/O. For applications requiring cusm gigabit links, a 4X connection is supported between the and the VPX P1 connecr support serial procols. The 5973 supports the emerging VITA standard, that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA interface enables gigabit backplane communications between boards independent of the interface. GateXpress for Configuration The 5973 architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most SBCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Specifications I/O Module Interface: VITA-57.1, High Pin Count FMC site Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm) 8267 VPX Development System See 8267 Datasheet for Options

229 New! New! New! New! New! Model 7070 Model 7070 shown with Model 3312 multichannel & D/A FMC module PCI Express Virtex-7 Processor and FMC Carrier - x8 General Information The Flexor Model 7070 is a high-performance board based on the Xilinx Virtex-7. As a stand-alone processor board, it provides an ideal development and deployment platform for demanding signal processing applications. The 7070 includes a VITA-57.1 FMC site providing access a wide range of I/O options. When combined with any of Pentek s analog interface FMCs, it becomes a complete multichannel data conversion and processing subsystem suitable for connection IF, HF or ports of a communications or radar system. The 7070 architecture includes an optional built-in gigabit serial optical interface. Up 12 high-speed duplex optical lanes are available on an MTP connecr. With the installation of a serial procol in the, this interface enables a high-bandwidth connection between 7070s mounted in the same chassis or even over extended distances between them. Board Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 retains all of the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the main board and the FMC module, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. When integrated with a Pentek FMC, the 7070 is delivered with facry-installed applications ideally matched the board s analog or digital interfaces. These can include acquisition and D/A waveform playback engines for simplifying data capture and playback. Data tagging and metadata packet generation, in conjunction with powerful linked-list DMA engines, provide a streamlined interface for moving data on and off the board and identifying data packets with channel, timing and sample -count information. IP modules for memories, controllers for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the 7070 and installed FMC operate as a complete turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Features VITA-57.1 FMC site offers access a wide range of possible I/O Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across 4 GB of PCI Express (Gen. 1, 2 and 3) interface up x8 Optional user-configurable 12X optical gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Commercial and extendedtemperature versions available CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen 3 x8 Gen. 3 x8 LVDS pairs LVDS GPIO LVDS FMC CONNECTOR 0 Card Edge Connecr 10X VIRTEX-7 VX330T or VX690T X Gigabit Serial I/O OPTICAL TRANSCEIVER (optional) MTP Connecr To Second Slot Front Panel

230 Model 7070 PCI Express Virtex-7 Processor and FMC Carrier - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. FMC Product Combinations If you wish purchase this FMC Carrier in combination with an FMC module, please see: FlexorSet Model FlexorSet Model FlexorSet Model FlexorSet Model Ordering Information 7070 PCI Express Virtex-7 Processor and FMC Carrier - x8 Options: -076 XC7VX690T pairs LVDS I/O x gigabit serial optical I/O Xilinx Virtex-7 The 7070 can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Sixteen pairs of LVDS connections are optionally provided between the and a card edge connecr for cusm I/O. For applications requiring cusm gigabit links, up 12 high-speed, full-duplex lanes driven via an optical transceiver support serial procols. A 12-lane MTP optical connecr is presented on a slot panel that can be installed in an empty, adjacent slot. When configured with a VX330T, four duplex lanes are available. GateXpress for Configuration The 7070 architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most SBCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Specifications I/O Module Interface: VITA-57.1, High Pin Count FMC site Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel, Option -104: pairs of LVDS connections between the and a card-edge connecr. Optical (Option -110): User-configurable 12X (VX690T) or 4X (VX 330T) optical gigabit serial interface, MTP connecr installed in an empty adjacent slot Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air cooled, Size: Half-length card Contact Pentek for availability of extended-temperature versions 8266 PC Development System See 8266 Datasheet for Options

231 New! New! New! New! New! Model 3312 Features Sold as the: FlexorSet Model FlexorSet Model Four 250 MHz -bit s One digital upconverter Two 800 MHz -bit D/As Sample clock synchronization an external system reference VITA 57 FMC compatible Complete radar or software radio interface solution when combined with the Model U OpenVPX or Model 7070 Virtex-7 FMC carriers Ruggedized and conductioncooled versions available 4-Ch. 250 MHz, -bit, 2-Ch. 800 MHz, -bit D/A - FMC General Information The Flexor Model 3312 is a multichannel, high-speed data converter FMC module. It is suitable for connection HF or IF ports of a communications or radar system. It includes four 250 MHz, -bit s, two 800 MHz, -bit D/As, programmable clocking, and multiboard synchronization for support of larger high-channelcount systems. The 3312 is sold as a complete turnkey data acquisition and signal generation solution as the FlexorSet TM U VPX or the FlexorSet board. For applications that require cusm processing, the FlexorSets are ideal for IP development and deployment. Converters The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 Dual 250 MHz, -bit converters. Performance of the Model 3312 The true performance of the 3312 can be unlocked only when used with the Pentek Model 5973 or Model 7070 FMC carriers. With facry-installed IP, the board-set provides a turnkey data acquisition subsystem eliminating the need create any IP. Installed features include flexible acquisition, programmable linked-list DMA engines, and a D/A waveform playback IP module. Acquisition IP Modules With the 3312 installed on either the 5973 or the 7070 carrier, the board-set features four acquisition IP modules for easily capturing and moving data. Each module can receive data from any of the four s, a test signal generar or from the D/A waveform playback IP module in loopback mode. Each IP module can have an associated memory bank on the FMC carrier for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the FMC carrier s interface. These powerful linked-list DMA engines are capable of a unique acquisition gatedriven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s task of identifying and executing on the data. D/A Waveform Playback IP Module With the 5973 or the 7070, the 3312 features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or offboard host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with minimum programming. In In In In Out Out Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS Clock/Sync Bus D/A Clock/Sync Bus Control & Status 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 800 MHz -BIT D/A DIGITAL UPCONVERTER VCXO FMC CONNECTOR

232 Model Ch. 250 MHz, -bit, 2-Ch. 800 MHz, -bit D/A - FMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 250 MHz, -bit, 2-Channel 800 MHz, -bit D/A - FMC Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options 8267 VPX Development System See 8267 Datasheet for Options Digital Upconverter and D/A Stage A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal allowing multiple modules be synchronized thereby creating larger multiboard systems. ReadyFlow Board Support Package When used with the 5973 or the 7070, Pentek s ReadyFlow BSP provides control of all the 3312 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a quickstart and powerful platform create cusm applications. ReadyFlow is compatible with Windows and Linux operating systems. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek s GateFlow Design Kits include all of the facryinstalled Virtex-7-based 5973/3312 or 7070/3312 IP modules as documented source code. Using Xilinx Vivado ols, developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek 5973/7070 IP with their own. FMC Interface The Model 3312 complies with the VITA 57 High Pin Count FMC specification. The interface provides all data, clocking, synchronization, control and status signals between the 3312 and the FMC carrier. Model 3312 Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz) or front panel external clock Synchronization: VCXO can be phaselocked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the or D/A clocks External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Environmental: Level L1 & L2 air cooled, Level L3 conduction-cooled, ruggedized I/O Module Interface: VITA-57.1, High-Pin Count FMC

233 New! New! New! New! New! FlexorSet Model Features Model Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 250 MHz -bit s One digital upconverter Two 800 MHz -bit D/As 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 4-Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX General Information Model is a member of the Flexor family of high-performance 3U VPX boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3312 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four 250 MHz, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 5973 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH VPX-P0 Clock/Sync Bus D/A Clock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 VPX-P1 In 250 MHz -BIT 4X Gigabit Serial I/O applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. In 250 MHz -BIT LVDS LVDS LVDS GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) In 250 MHz -BIT FMC CONNECTOR FMC CONNECTOR In 250 MHz -BIT VPX BACKPLANE Out 800 MHz -BIT D/A DIGITAL UPCONVERTER Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

234 FlexorSet Model Acquisition IP Modules The features four Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the four s, a test signal generar or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The facry-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. Option -104 provides pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit backplane communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving Bank 1 from Ch 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Acq Module 1 32 Bank 1 PACKING META ACQUISITION IP MODULE 1 Acq Module 2 32 Bank 2 Acq Module 3 32 Bank 3 from Ch 2 Acq Mod4& D/A Mod 32 Bank 4 from Ch 3 INPUT MULTIPLEXER ACQUISITION IP MODULES 2&3 the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. Bank 4 INTEACE from Ch 4 PACKING META ACQUISITION IP MODULE 4 D/A loopback TEST SIGNAL Bank 4 8X Gigabit 4X 32 Serial I/O GPIO D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE

235 FlexorSet Model Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 250 MHz, 2-Channel 800 MHz -bit D/A with Virtex-7-3U VPX Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X optical interface Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual 250 MHz, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm)

236 New! New! New! New! New! FlexorSet Model Model Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - x8 General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3312 FMC is facry-installed on the 7070 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four 250 MHz, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Features In In In In Out Out Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 250 MHz -bit s One digital upconverter Two 800 MHz -bit D/As 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 7070 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 Gen. 3 x8 250 MHz -BIT 250 MHz -BIT LVDS pairs LVDS GPIO Card Edge Connecr FMC CONNECTOR FMC CONNECTOR LVDS MHz -BIT 10X VIRTEX-7 VX330T or VX690T 250 MHz -BIT MHz -BIT D/A DIGITAL UPCONVERTER 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

237 FlexorSet Model Acquisition IP Modules The features four Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the four s, a test signal generar or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The facry-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - x8 Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides pairs of LVDS connections between the and a cardedge connecr for cusm I/O. Option -110: For applications requiring optical gigabit links, up 12 high-speed, full-duplex lanes driven via an optical transceiver support serial procols. A 12-lane MTPoptical connecr is presented on the slot panel. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. Bank 1 from Ch 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Acq Module 1 32 Bank 1 PACKING META ACQUISITION IP MODULE 1 Acq Module 2 32 Bank 2 Acq Module 3 32 Bank 3 from Ch 2 Acq Mod4& D/A Mod 32 Bank 4 from Ch 3 INPUT MULTIPLEXER ACQUISITION IP MODULES 2&3 The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the Bank 4 INTEACE from Ch 4 PACKING META ACQUISITION IP MODULE 4 D/A loopback TEST SIGNAL Bank 4 8X 32 GPIO D/A UNPACKING D/A WAVEFORM PLAYBACK IP MODULE

238 FlexorSet Model Ch. 250 MHz -bit, 2-Ch. 800 MHz -bit D/A - x8 PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 250 MHz, 2-Channel 800 MHz - bit D/A with Virtex-7 - x8 Options: -076 XC7VX690T LVDS I/O cardedge connecr x gigabit serial optical I/O with XC7VX690T, 4x w. XC7VX330T 8266 PC Development System See 8266 Datasheet for Options loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual 250 MHz, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of LVDS connections between the and a card-edge connecr for cusm I/O Optical (Option -110): 12x gigabit serial optical I/O with XC7VX690T, 4x with XC7VX330T Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Size: in. x in. (100 mm x mm)

239 New! New! New! New! New! Model 33 Features Sold as the: FlexorSet Model FlexorSet Model Eight 250 MHz, -bit s On-board timing bus generar with multiboard synchronization Sample clock synchronization an external system reference VITA 57 FMC compatible Complete radar or software radio interface solution when combined with the Model U OpenVPX or Model 7070 Virtex-7 FMC carrier Ruggedized and conductioncooled versions available 8-Channel 250 MHz, -bit - FMC General Information The Flexor Model 33 is a multichannel, high-speed data converter FMC module. It is suitable for connection HF or IF ports of a communications or radar system. It includes eight 250 MHz, -bit s, programmable clocking, and multiboard synchronization for support of larger high-channelcount systems. The 33 is sold as a complete turnkey data acquisition solution as the FlexorSet TM U VPX or the FlexorSet board. For applications that require cusm processing, the FlexorSets are ideal for IP development and deployment. Converters The front end accepts eight analog HF or IF inputs on front-panel connecrs with transformer-coupling in four Texas Instruments ADS42LB69 Dual 250 MHz, -bit converters. Performance of the Model 33 The true performance of the 33 can be unlocked only when used with the Pentek Model 5973 or Model 7070 FMC carriers. With facry-installed IP, the board-set provides a turnkey data acquisition subsystem eliminating the need create any IP. Installed features include flexible acquisition, programmable linked-list DMA engines, and a metadata packet crear. Acquisition IP Modules With the 33 installed on either the 5973 or the 7070 FMC carrier, the board-set features eight Acquisition IP modules for easily capturing and moving data. Each module can receive data from any of the eight s, or a test signal generar. Each IP module can have an associated memory bank on the Pentek FMC carrier for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the FMC carrier s interface. These powerful linked-list DMA engines are capable of a unique acquisition gate driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data-length information. These actions simplify the host processor s task of identifying and executing on the data. In In In In In In In In Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS Clock/Sync Bus 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT 250 MHz -BIT Control & Status VCXO FMC CONNECTOR

240 Model 33 8-Channel 250 MHz, -bit - FMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information 33 8-Channel 250 MHz, -bit - FMC Contact Pentek for availability of rugged and conduction-cooled versions Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. Included are a clock, sync and gate or trigger signals. An on-board clock generar can receive an external sample clock from the front-panel coaxial connecr. This clock can be used directly by the section or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage- Controlled Crystal Oscillar). In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel Gate/Trigger/PPS connecr can receive an external timing signal allowing multiple modules be synchronized create larger multiboard systems. ReadyFlow Board Support Package When used with the 5973 or the 7070, Pentek s ReadyFlow BSP provides control of all the 33 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a quickstart and powerful platform create cusm applications. ReadyFlow is compatible with Windows and Linux operating systems. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek s GateFlow Design Kits include all of the facryinstalled Virtex-7-based 5973/33 or 7070/33 IP modules as documented source code. Using Xilinx Vivado ols, developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek 5973/7070 IP with their own. FMC Interface The Model 33 complies with the VITA 57 High Pin Count FMC specification. The interface provides all data, clocking, synchronization, control and status signals between the 33 and the FMC carrier. Model 33 Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits Sample Clock Source: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz) or front-panel external clock Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized I/O Module Interface: VITA-57.1, High-Pin Count FMC 8266 PC Development System See 8266 Datasheet for Options 8267 VPX Development System See 8267 Datasheet for Options

241 New! New! New! New! New! FlexorSet Model Features Model Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Eight 250 MHz -bit s 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 8-Channel 250 MHz with Virtex-7-3U VPX General Information Model is a member of the Flexor family of high-performance 3U VPX boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 33 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes eight s and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include eight Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 33 FMC Model 5973 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus VPX-P0 Control & Status Config Bus In 250 MHz -BIT GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 VPX-P1 In 250 MHz -BIT 4X Gigabit Serial I/O acquisition IP modules for simplifying data capture and data transfer. Each of the eight acquisition IP modules contains IP modules for memories. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. In 250 MHz -BIT LVDS LVDS LVDS GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) In 250 MHz -BIT FMC CONNECTOR FMC CONNECTOR In 250 MHz -BIT VPX BACKPLANE In 250 MHz -BIT In 250 MHz -BIT In 250 MHz -BIT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

242 FlexorSet Model Acquisition IP Modules The features eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the eight s or a test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 8-Channel 250 MHz with Virtex-7-3U VPX Option -104 provides pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit backplane communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from TEST SIGNAL Bank 1 Acq Mod1&2 32 Bank 1 PACKING META ACQUISITION IP MODULE 1 Acq Mod3&4 32 Bank 2 from Ch 1 Acq Mod5&6 32 Bank 3 from Ch 2 Bank 1 32 Bank 4 from Ch 3 PACKING META ACQUISITION IP MODULE 2 FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts eight analog HF or IF inputs on front-panel connecrs with transformer-coupling in four Texas Instruments ADS42LB69 dual 250 MHz, -bit converters. from Ch 4 INPUT MULTIPLEXER from Ch 5 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Acq Mod7&8 from Ch 6 GPIO from Ch 7 Bank 4 32 from Ch 8 PACKING ACQUISITION IP MODULES 3-7 Gigabit Serial I/O 4X META ACQUISITION IP MODULE 8 INTEACE 8X

243 FlexorSet Model Channel 250 MHz with Virtex-7-3U VPX Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 250 MHz with Virtex-7-3U VPX Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X optical interface Contact Pentek for availability of rugged and conduction-cooled versions Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. Included are a clock, sync and gate or trigger signals. An on-board clock generar can receive an external sample clock from the front-panel coaxial connecr. This clock can be used directly by the section or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage- Controlled Crystal Oscillar). In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel Gate/Trigger/PPS connecr can receive an external timing signal allowing multiple boards be synchronized create larger multiboard systems. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm) 8267 VPX Development System See 8267 Datasheet for Options

244 New! New! New! New! New! FlexorSet Model Model Channel 250 MHz with Virtex-7 - x8 General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 33 FMC is facry-installed on the 7070 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes eight s and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include eight acquisition IP modules for simplifying data capture and data transfer. Each of the eight acquisition IP modules contains IP modules for memories. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. In In In In In In In In Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Eight 250 MHz -bit s 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 33 FMC Model 7070 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus Control & Status 250 MHz -BIT Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 Gen. 3 x8 250 MHz -BIT 250 MHz -BIT LVDS pairs LVDS GPIO Card Edge Connecr LVDS 250 MHz -BIT 0 FMC CONNECTOR FMC CONNECTOR 10X VIRTEX-7 VX330T or VX690T 250 MHz -BIT MHz -BIT 250 MHz -BIT 250 MHz -BIT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

245 FlexorSet Model Acquisition IP Modules The features eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the eight s or a test signal generar. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. 8-Channel 250 MHz with Virtex-7 - x8 Option -104 provides pairs of LVDS connections between the and a cardedge connecr for cusm I/O. Option -110: For applications requiring optical gigabit links, up 12 high-speed, full-duplex lanes driven via an optical transceiver support serial procols. A 12-lane MTPoptical connecr is presented on the slot panel. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user TEST SIGNAL Bank 1 Acq Mod1&2 32 Bank 1 PACKING META ACQUISITION IP MODULE 1 Acq Mod3&4 32 Bank 2 from Ch 1 Acq Mod5&6 32 Bank 3 from Ch 2 Bank 1 Acq Mod7&8 32 Bank 4 from Ch 3 PACKING META ACQUISITION IP MODULE 2 selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts eight analog HF or IF inputs on front-panel connecrs with transformer-coupling in four Texas Instruments ADS42LB69 dual 250 MHz, -bit converters. from Ch 4 INPUT MULTIPLEXER from Ch 5 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL from Ch 6 GPIO from Ch 7 32 Bank 4 from Ch 8 PACKING ACQUISITION IP MODULES 3-7 META ACQUISITION IP MODULE 8 INTEACE 8X

246 FlexorSet Model Channel 250 MHz with Virtex-7 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 250 MHz with Virtex-7 - x8 Options: -076 XC7VX690T LVDS I/O cardedge connecr x gigabit serial optical I/O with XC7VX690T, 4x w. XC7VX330T Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. Included are a clock, sync and gate or trigger signals. An on-board clock generar can receive an external sample clock from the front-panel coaxial connecr. This clock can be used directly by the section or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage- Controlled Crystal Oscillar). In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel Gate/Trigger/PPS connecr can receive an external timing signal allowing multiple boards be synchronized create larger multiboard systems. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz 250 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of LVDS connections between the and the card-edge connecr for cusm I/O Optical (Option -110): 12x gigabit serial optical I/O with XC7VX690T, 4x with XC7VX330T Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Size: in. x in. (100 mm x mm) 8266 PC Development System See 8266 Datasheet for Options

247 New! New! New! New! New! Model 3320 Features Sold as the: FlexorSet Model FlexorSet Model Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Two 3.0 GHz* s Two 2.8 GHz* D/As Two digital downconverters Two digital upconverters 4 GB of Sample clock synchronization an external system reference VITA 57 FMC compatible Ruggedized and conductioncooled versions available 2-Channel 3.0 GHz, 2-Channel 2.8 GHz D/A - FMC General Information The Flexor TM Model 3320 is a multichannel, high-speed data converter FMC. It is suitable for connection or IF ports of a communications or radar system. It includes two 3.0 GHz s, two 2.8 GHz D/As, programmable clocking and multiboard synchronization for support of larger highchannel-count systems. The 3320 is sold as a complete turnkey data acquisition and signal generation solution as the FlexorSet TM U VPX or the FlexorSet board. For applications that require cusm processing, the FlexorSets are ideal for IP development and deployment. Performance of the Model 3320 The true performance of the 3320 can be unlocked only when used with the Pentek Model 5973 or Model 7070 FMC carriers. With facry-installed IP, the board-set provides a turnkey data acquisition subsystem eliminating the need create any IP. Installed features include flexible acquisition, programmable linked-list DMA engines, and D/A waveform playback IP modules. Designed allow users optimize data conversion rates and modes for specific application requirements, the FlexorSet provides preconfigured conversion profiles. Users can use these profiles which include: digital downconverter and digital upconverter modes, conversion resolution and and D/A sample rates, or program their own profiles. In addition supporting Gen. 3 as a native interface, the FlexorSet includes optional copper and optical connections the Virtex-7 for cusm I/O. and Digital Downconverter Stage The front end accepts two analog or IF inputs on front-panel connecrs with transformer-coupling in a Texas Instruments ADC3245 dual channel. With dual built-in digital downconverters and programmable decimations, the converter serves as an ideal interface for a range of radar, signal intelligence and electronic countermeasures applications. The ADC3245 can operate within a range of different conversion speeds and resolutions. See the table on the last page for supported modes. Acquisition IP Modules With the 3320 installed on either the 5973 or the 7070 carrier, the board-set features two Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two s, a test signal generar or from the two D/A waveform playback IP modules in loopback mode. Each IP module can have an associated memory bank on the FMC carrier for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the FMC carrier s interface. These powerful linked-list DMA engines are capable of a unique acquisition gatedriven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data-length information. These actions simplify the host processor s job of identifying and executing on the data. In In Out Out Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS Clock/Sync Bus D/A Clock/Sync Bus Control & Status * 3.0 GHz 14-BIT DIGITAL DOWNCONVERT * 3.0 GHz 14-BIT DIGITAL DOWNCONVERT 2.8 GHz* -BIT D/A DIGITAL UPCONVERT 2.8 GHz* -BIT D/A DIGITAL UPCONVERT VCXO FMC CONNECTOR * See last page for configuration profiles

248 Model Channel 3.0 GHz, 2-Channel 2.8 GHz D/A - FMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt, Onyx and Flexor VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Digital Upconverter and D/A Stage Two Texas Instruments DAC39J84 D/As accept two baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the dual -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2.8 GHz. In both modes the D/As provide interpolation facrs from 1x x. D/A Waveform Playback IP Modules A Texas Instruments DAC39J84 D/A accepts two baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the dual -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2.8 GHz. In both modes the D/As provide programmable interpolation. Clocking and Synchronization The 3320 architecture includes a timing bus generar, responsible for providing clocking the data converters, and all synchronization circuits. When paired with the 5973 or the 7070, the FlexorSet s built-in functions include setup and support of the timing generar produce the predefined data conversion profiles. This simplifies operation by allowing users easily change profiles through software. The timing bus generar has a built-in frequency synthesizer that allows the board operate without the need for an external sample clock. If users prefer, an external clock can be accepted on a front panel coax connecr. In addition, the connecr can be programmed accept a 10 MHz system reference, locking the on-board clock the reference that enables synchronization across multiple boards. A front panel LVTTL Gate/Trigger/Sync connecr is also included on the board. Users can program the connecr s function operate in one of three modes match the application requirements. ReadyFlow Board Support Package When used with the 5973 or the 7070, Pentek s ReadyFlow BSP provides control of all the 3320 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a quick-start and powerful platform create cusm applications. ReadyFlow is compatible with Windows and Linux operating systems. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek s GateFlow Design Kits include all of the facryinstalled Virtex-7-based 5973/320 or 7070/320 modules as documented source code. Using Xilinx Vivado ols, developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek 5973/7070 IP with their own. FMC Interface The Model 3320 complies with the VITA 57 High-Pin Count FMC specification. The interface provides all data, clocking, synchronization, control and status signals between the 3320 and the FMC carrier.

249 Model Channel 3.0 GHz, 2-Channel 2.8 GHz D/A - FMC Ordering Information Channel 3.0 GHz, 2-Channel 2.8 GHz D/A with Virtex-7-3U VPX Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X (with VX690T), 4X (with VX330T) optical interface Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options Channel 3.0 GHz, 2-Channel 2.8 GHz D/A with Virtex-7 - x8 Options: -076 XC7VX690T LVDS I/O cardedge connecr -110 VITA X (with VX690T), 4X (with VX330T) optical interface Model 3320 Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Mini-Circuits TC1-1-13M Full Scale Input: +6.6 dbm in 50 ohms 3 db Passband: MHz Converters Type: Texas Instruments ADC3245 Sampling Rate and Resolution: See table below Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Coil Craft WBC4-14L Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 1.5 MHz 1200 MHz D/A Converters Type: Texas Instruments DAC39J84 Sampling Rate and Resolution: See table below Converter Sample Rate Output Resolution Decimation Sample Clock Sources: Timing bus generar provides and D/A clocks Timing Bus Generar Clock Source: Selectable from on-board frequency synthesizer or front panel external clock Synchronization: Frequency synthesizer can be locked an external 10 MHz PLL system reference External Clock Type: Front panel SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms External Trigger Input Type: Front panel SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm) Pre-configured Conversion Profiles* Converter D/A Converter Output Data Rate** Real / Complex Interpolation Input Data Rate** Real / Complex 3.0 GHz bit GB/sec complex n/a n/a n/a 2.8 GHz bit GB/sec complex GB/sec complex 2.8 GHz bit GB/sec complex GB/sec complex 2.5 GHz 12 bit bypass 5.0 GB/sec real n/a n/a n/a 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec complex 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec real 1.0 GHz 14 bit bypass 2.0 GB/sec real GB/sec real * Other modes can be cusm-configured by the user ** Per channel, output data rates are subject maximum bus speeds of the host computer 8266 PC Development System See 8266 Datasheet for Options

250 New! New! New! New! New! FlexorSet Model Features Model Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Two 3.0 GHz* s Two 2.8 GHz* D/As Two digital downconverters Two digital upconverters 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 2-Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A wth Virtex-7-3U VPX General Information Model is a member of the Flexor family of high-performance 3U VPX boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3320 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. Designed allow users optimize data conversion rates and modes for specific application requirements, the FlexorSet provides preconfigured conversion profiles. Users can use these profiles which include: digital downconverter and digital upconverter modes, conversion resolution and and D/A sample rates, or program their own profiles. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3320 FMC TIMING BUS Clock / Sync / Gate / PPS VCXO Model 5973 FMC Carrier CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus VPX-P0 Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 3.0 GHz* 14-BIT DIGITAL DOWNCONVERT Gen.3x8 VPX-P1 In 4X Gigabit Serial I/O In 3.0 GHz* 14-BIT DIGITAL DOWNCONVERT LVDS LVDS LVDS GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) FMC CONNECTOR FMC CONNECTOR * See last page for configuration profiles The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include two acquisition IP modules for simplifying data capture and data transfer. Each of the acquisition IP modules contains IP modules for memories. The features two sophisticated D/A waveform playback IP modules. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Out 2.8 GHz* -BIT D/A DIGITAL UPCONVERT VPX BACKPLANE Out 2.8 GHz* -BIT D/A DIGITAL UPCONVERT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

251 FlexorSet Model Acquisition IP Modules The features two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the two s, a test signal generar or from the two D/A Waveform Playback IP modules in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the two D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries per module can be chained gether create complex waveforms with a minimum of programming. 2-Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A wth Virtex-7-3U VPX In each playback module, up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. Bank PACKING META From Ch 1 ACQUISITION IP MODULE 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL From Ch 2 INPUT MULTIPLEXER Bank PACKING META ACQUISITION IP MODULE 2 GPIO Option -104 provides pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides up 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. Bank INTEACE D/A loopback To D/A Ch 1 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 1 D/A loopback TEST SIGNAL Bank ToAcquisition / Playback Module To D/A Ch 2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE X 4X Gigabit Serial I/O Banks 1 & 2 Banks 3 & 4 ToAcquisition / Playback Module

252 FlexorSet Model Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A wth Virtex-7-3U VPX Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s waveform playback capabilities, providing local srage for user waveforms. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Converter and Digital Downconverter Stage The front end accepts two analog or IF inputs on front-panel connecrs with transformer-coupling in a Texas Instruments ADC3245 dual channel. With dual built-in digital downconverters and programmable decimations, the converter serves as an ideal interface for a range of radar, signal intelligence and electronic countermeasures applications. The ADC3245 can operate within a range of different conversion speeds and resolutions. See the table on next page for supported modes. Digital Upconverter and D/A Stage A Texas Instruments DAC39J84 D/A accepts two baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the dual -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2.8 GHz. In both modes the D/As provide programmable interpolation. Clocking and Synchronization The 3320 architecture includes a timing bus generar, responsible for providing clocking the data converters, and all synchronization circuits. When paired with the 7070, the FlexorSet s built-in functions include setup and support of the timing generar produce the predefined data conversion profiles. This simplifies operation by allowing users easily change profiles through software. The timing bus generar has a built in frequency synthesizer that allows the board operate without the need of an external sample clock. If users prefer, an external clock can be accepted on a front panel coax connecr. In addition, the connecr can be programmed accept a 10 MHz system reference, locking the on-board clock the reference that enables synchronization across multiple boards. A front panel LVTTL Gate/Trigger/Sync connecr is also included on the board. Users can program the connecr s function operate in one of three modes match the application requirements.

253 FlexorSet Model Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A wth Virtex-7-3U VPX Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Mini-Circuits TC1-1-13M Full Scale Input: +6.6 dbm in 50 ohms 3 db Passband: MHz Converters Type: Texas Instruments ADC3245 Sampling Rate and Resolution: See table below Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Coil Craft WBC4-14L Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 1.5 MHz 1200 MHz D/A Converters Type: Texas Instruments DAC39J84 Sampling Rate and Resolution: See table below Sample Clock Sources: Timing bus generar provides and D/A clocks Timing Bus Generar Clock Source: Selectable from on-board frequency synthesizer or front panel external clock Synchronization: Frequency synthesizer can be locked an external 10 MHz PLL system reference External Clock Type: Front panel SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms External Trigger Input Type: Front panel SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): User configurable VITA-66.4, 12X (with VX690T) or 4X (with VX330T) duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm) Ordering Information Channel 3.0 GHz, 2-Channel 2.8 GHz D/A with Virtex-7-3U VPX Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X (with VX690T), 4X (with VX330T) optical interface Contact Pentek for availability of rugged and conduction-cooled versions Converter Sample Rate Output Resolution Pre-configured Conversion Profiles* Converter D/A Converter Decimation Output Data Rate** Real / Complex Interpolation Input Data Rate** Real / Complex 3.0 GHz bit GB/sec complex n/a n/a n/a 2.8 GHz bit GB/sec complex GB/sec complex 2.8 GHz bit GB/sec complex GB/sec complex 2.5 GHz 12 bit bypass 5.0 GB/sec real n/a n/a n/a 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec complex 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec real 1.0 GHz 14 bit bypass 2.0 GB/sec real GB/sec real * Other modes can be cusm-configured by the user ** Per channel, output data rates are subject maximum bus speeds of the host computer 8267 VPX Development System See 8267 Datasheet for Options

254 New! New! New! New! New! FlexorSet Model Model Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A with Virtex-7 - x8 General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3320 FMC is facry-installed on the 7070 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. Designed allow users optimize data conversion rates and modes for specific application requirements, the FlexorSet provides preconfigured conversion profiles. Users can use these profiles which include: digital downconverter and digital upconverter modes, conversion resolution and and D/A sample rates, or program their own profiles. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include two acquisition IP modules for simplifying data capture and data transfer. Each of the acquisition IP modules contains IP modules for memories. The features two sophisticated D/A waveform playback IP modules. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. In In Out Out Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Two 3.0 GHz* s Two 2.8 GHz* D/As Two digital downconverters Two digital upconverters 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3320 FMC TIMING BUS Clock / Sync / Gate / PPS VCXO Model 7070 FMC Carrier CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 3.0 GHz* 14-BIT DIGITAL DOWNCONVERT Gen. 3 x8 LVDS 3.0 GHz* 14-BIT DIGITAL DOWNCONVERT pairs LVDS GPIO Card Edge Connecr FMC CONNECTOR FMC CONNECTOR LVDS 0 10X VIRTEX-7 VX330T or VX690T * See last page for configuration profiles 2.8 GHz* -BIT D/A DIGITAL UPCONVERT 2.8 GHz* -BIT D/A DIGITAL UPCONVERT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

255 FlexorSet Model Acquisition IP Modules The features two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the two s, a test signal generar or from the two D/A Waveform Playback IP modules in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules The facry-installed functions include two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the two D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries per module can be chained gether create complex waveforms with a minimum of programming. 2-Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A with Virtex-7 - x8 In each playback module, up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Bank PACKING META From Ch 1 ACQUISITION IP MODULE 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL From Ch 2 INPUT MULTIPLEXER Bank PACKING META ACQUISITION IP MODULE 2 GPIO Option -104 provides pairs of LVDS connections between the and a card-edge connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides up 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. Bank INTEACE D/A loopback To D/A Ch 1 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 1 D/A loopback TEST SIGNAL Bank ToAcquisition / Playback Module To D/A Ch 2 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE X Banks 1 & 2 Banks 3 & 4 ToAcquisition / Playback Module

256 FlexorSet Model Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A with Virtex-7 - x8 The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s waveform playback capabilities, providing local srage for user waveforms. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Converter and Digital Downconverter Stage The front end accepts two analog or IF inputs on front-panel connecrs with transformer-coupling in a Texas Instruments ADC3245 dual channel. With dual built-in digital downconverters and programmable decimations, the converter serves as an ideal interface for a range of radar, signal intelligence and electronic countermeasures applications. The ADC3245 can operate within a range of different conversion speeds and resolutions. See the table on next page for supported modes. Digital Upconverter and D/A Stage A Texas Instruments DAC39J84 D/A accepts two baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the dual -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2.8 GHz. In both modes the D/As provide programmable interpolation. Clocking and Synchronization The 3320 architecture includes a timing bus generar, responsible for providing clocking the data converters, and all synchronization circuits. When paired with the 7070, the FlexorSet s built-in functions include setup and support of the timing generar produce the predefined data conversion profiles. This simplifies operation by allowing users easily change profiles through software. The timing bus generar has a built in frequency synthesizer that allows the board operate without the need of an external sample clock. If users prefer, an external clock can be accepted on a front panel coax connecr. In addition, the connecr can be programmed accept a 10 MHz system reference, locking the on-board clock the reference that enables synchronization across multiple boards. A front panel LVTTL Gate/Trigger/Sync connecr is also included on the board. Users can program the connecr s function operate in one of three modes match the application requirements.

257 FlexorSet Model Ch. 3.0 GHz, 2-Ch. 2.8 GHz D/A with Virtex-7 - x8 Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Mini-Circuits TC1-1-13M Full Scale Input: +6.6 dbm in 50 ohms 3 db Passband: MHz Converters Type: Texas Instruments ADC3245 Sampling Rate and Resolution: See table below Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel SSMC connecrs Transformer Type: Coil Craft WBC4-14L Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 1.5 MHz 1200 MHz D/A Converters Type: Texas Instruments DAC39J84 Sampling Rate and Resolution: See table below Sample Clock Sources: Timing bus generar provides and D/A clocks Timing Bus Generar Clock Source: Selectable from on-board frequency synthesizer or front panel external clock Synchronization: Frequency synthesizer can be locked an external 10 MHz PLL system reference External Clock Type: Front panel SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms External Trigger Input Type: Front panel SSMC connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of LVDS connections between the and a card-edge connecr for cusm I/O Optical (Option -110): User configurable VITA-66.4, 12X (with VX690T) or 4X (with VX330T) duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled Size: in. x in. (100 mm x mm) Ordering Information Channel 3.0 GHz, 2-Channel 2.8 GHz D/A with Virtex-7 - x8 Options: -076 XC7VX690T LVDS I/O cardedge connecr -110 VITA X (with VX690T), 4X (with VX330T) optical interface Converter Sample Rate Output Resolution Pre-configured Conversion Profiles* Converter D/A Converter Decimation Output Data Rate** Real / Complex Interpolation Input Data Rate** Real / Complex 3.0 GHz bit GB/sec complex n/a n/a n/a 2.8 GHz bit GB/sec complex GB/sec complex 2.8 GHz bit GB/sec complex GB/sec complex 2.5 GHz 12 bit bypass 5.0 GB/sec real n/a n/a n/a 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec complex 2.0 GHz 14 bit bypass 4.0 GB/sec real GB/sec real 1.0 GHz 14 bit bypass 2.0 GB/sec real GB/sec real * Other modes can be cusm-configured by the user ** Per channel, output data rates are subject maximum bus speeds of the host computer 8266 PC Development System See 8266 Datasheet for Options

258 New! New! New! New! New! Model 3324 Features Sold as the: FlexorSet Model FlexorSet Model Four 500 MHz, -bit s Four digital upconverters Four 2 GHz, -bit D/As (500 MHz input data rate, 2 GHz output sample rate with interpolation) On-board timing bus generar with multiboard synchronization Sample clock synchronization an external system reference VITA 57 FMC compatible Complete radar or software radio interface solution when combined with the Model U OpenVPX or Model 7070 Virtex-7 FMC carrier Ruggedized and conductioncooled versions available 4-Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A-FMC General Information The Flexor TM Model 3324 is a multichannel, high-speed data converter FMC. It is suitable for connection HF or IF ports of a communications or radar system. It includes four 500 MHz, -bit s, four 2 GHz, -bit D/As, programmable clocking, and multiboard synchronization for support of larger high-channelcount systems. The 3324 is sold as a complete turnkey data acquisition and signal generation solution as the FlexorSet TM U VPX or the FlexorSet board. For applications that require cusm processing, the FlexorSets are ideal for IP development and deployment. Converters The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in four 500 MHz, -bit converters. Performance of the Model 3324 The true performance of the 3324 can be unlocked only when used with the Pentek Model 5973 or Model 7070 FMC carriers. With facry-installed IP, the board-set provides a turnkey data acquisition subsystem eliminating the need create any IP. Installed features include flexible acquisition, programmable linked-list DMA engines, and a D/A waveform playback IP module. Acquisition IP Modules With the 3324 installed on either the 5973 or the 7070 carrier, the board-set features four Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the four s, a test signal generar or from the D/A waveform playback IP module in loopback mode. Each IP module can have an associated memory bank on the FMC carrier for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the FMC carrier s interface. These powerful linked-list DMA engines are capable of a unique acquisition gatedriven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data-length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Modules Whith the 5973 or the 7070, the 3324 features four sophisticated D/A waveform playback IP modules. A linked-list controller allows users easily play back via the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries per module can be chained gether create complex waveforms with a minimum of programming. In In In In Out Out Out Out Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS Clock/Sync Bus D/A Clock/Sync Bus Control & Status 500 MHz -BIT 500 MHz -BIT 500 MHz -BIT 500 MHz -BIT 2 GHz -BIT D/A DIGITAL UPCONVERT 2 GHz -BIT D/A DIGITAL UPCONVERT 2 GHz -BIT D/A DIGITAL UPCONVERT 2 GHz -BIT D/A DIGITAL UPCONVERT VCXO FMC CONNECTOR

259 Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A-FMC Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Model 8267 The Model 8267 is a fullyintegrated VPX development system for Pentek Cobalt, Onyx and Flexor VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 500 MHz -bit, 4-Channel 2 GHz -bit D/A - FMC Contact Pentek for availability of rugged and conduction-cooled versions 8266 PC Development System See 8266 Datasheet for Options 8267 VPX Development System See 8267 Datasheet for Options Digital Upconverters and D/As Four D/As accept baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 1.5 GHz. In both modes the D/As provide interpolation facrs of 2x, 4x, 8x and x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel Gate/Trigger/PPS connecr can receive an external timing signal allowing multiple modules be synchronized and create larger multiboard systems. ReadyFlow Board Support Package When used with the 5973 or the 7070, Pentek s ReadyFlow BSP provides control of all the 3324 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a quick-start and powerful platform create cusm applications. ReadyFlow is compatible with Windows and Linux operating systems. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek s GateFlow Design Kits include all of the facryinstalled Virtex-7-based 5973/3324 or 7070/3324 modules as documented source code. Using Xilinx Vivado ols, developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek 5973/7070 IP with their own. FMC Interface The Model 3324 complies with the VITA 57 High-Pin Count FMC specification. The interface provides all data, clocking, synchronization, control and status signals between the 3324 and the FMC carrier. Model 3324 Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC1-1TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 250 khz 750 MHz Converters Type: Texas Instruments ADS54J60 Sampling Rate: up 500 MHz Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz D/A Converters Type: Texas Instruments DAC38J84 Input Data Rate: Up 500 MHz Output Sample Rate: Up 2 GHz (with interpolation) Resolution: bits Sample Clock Source: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz) or front-panel external clock Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the and D/A clocks External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized I/O Module Interface: VITA-57.1, High-pincount FMC

260 New! New! New! New! New! FlexorSet Model Features Model Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 500 MHz -bit s Four digital upconverters Four 2 GHz -bit D/As (500 MHz input sample rate, 2 GHz output sample rate with interpolation) 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 4-Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - 3U VPX General Information Model is a member of the Flexor family of high-performance 3U VPX boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3324 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four 500 MHz, -bit s, four digital upconverters, four 2 GHz, - bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS VCXO Model 3324 FMC Model 5973 FMC Carrier CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus VPX-P0 Control & Status 500 MHz -BIT Config Bus In GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen.3x8 VPX-P1 In 500 MHz -BIT 4X In 500 MHz -BIT Gigabit Serial I/O LVDS board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features four sophisticated D/A waveform playback IP modules. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. In each playback module, up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. In LVDS LVDS GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) 500 MHz -BIT FMC CONNECTOR FMC CONNECTOR Out 2 GHz -BIT D/A DIGITAL UPCONVERT Out 2 GHz -BIT D/A DIGITAL UPCONVERT VPX BACKPLANE Out 2 GHz -BIT D/A DIGITAL UPCONVERT Out 2 GHz -BIT D/A DIGITAL UPCONVERT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

261 FlexorSet Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - 3U VPX Acquisition IP Modules The features four Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the four s, a test signal generar or from the four D/A Waveform Playback IP modules in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. Option -104 provides pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. D/A Waveform Playback IP Modules The facry-installed functions include four sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the four D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries per module can be chained gether create complex waveforms with a minimum of programming. Bank 1 From Ch 1 PACKING META ACQUISITION IP MODULE 1 From Ch 2 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL To Acq Modules 1 & 2 32 Bank 1 From Ch 3 INPUT MULTIPLEXER ACQUISITION IP MODULES 2&3 2 goes Bank 1 3 goes Bank 2 To Acq Modules 3 & 4 32 Bank 2 Bank 2 GPIO From Ch 4 PACKING META ACQUISITION IP MODULE 4 32 INTEACE D/A loopback Bank 3 8X To D/A Ch 1 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 1 Gigabit Serial I/O To D/A Ch 2 4X D/A WAFEFORM PLAYBACK IP MODULES 2&3 2 goes Bank 3 3 goes Bank 4 To D/A Ch3 D/A loopback TEST SIGNAL Bank 4 To D/APlayback Modules 1 & 2 32 Bank 3 To D/A Ch 4 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4 To D/APlayback Modules 3 & 4 32 Bank 4

262 FlexorSet Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - 3U VPX PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Model 8267 The Model 8267 is a fullyintegrated development system for Pentek Cobalt, Onyx and Flexor 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 500 MHz -bit, 4-Channel 2 GHz -bit D/A with Virtex-7-3U VPX Options: -076 XC7VX690T LVDS I/O VPX P2-110 VITA X optical interface Contact Pentek for availability of rugged and conduction-cooled versions 8267 VPX Development System See 8267 Datasheet for Options In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in 500 MHz, -bit converters. Digital Upconverter and D/A Stage Four D/As accept baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2 GHz. In both modes the D/As provide interpolation facrs of 2x, 4x, 8x and x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC1-1TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 750 MHz Converters Type: Texas Instruments ADS54J60 Sampling Rate: Up 500 MHz Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz D/A Converters Type: Texas Instruments DAC38J84 Input Data Rate: Up 500 MHz Output Sample Rate: Up 2 GHz (with interpolation) Resolution: bits Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the and D/A clocks External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm)

263 New! New! New! New! New! FlexorSet Model Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - x8 General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3324 FMC is facry-installed on the 7070 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four 500 MHz, -bit s, four digital upconverters, four 2 GHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facryinstalled functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features four sophisticated D/A waveform playback IP modules. A linked-list controller allows users easily play back the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. In each playback module, up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their cusm Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 500 MHz -bit s Four digital upconverters Four 2 GHz -bit D/As (500 MHz input data rate, 2 GHz output sample rate with interpolation) 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS Clock / Sync / Gate / PPS VCXO Model 3324 FMC Model 7070 FMC Carrier CONFIG FLASH Clock/Sync Bus D/A Clock/Sync Bus Control & Status In 500 MHz -BIT Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 In 500 MHz -BIT Gen. 3 x8 In 500 MHz -BIT LVDS pairs LVDS GPIO Card Edge Connecr In 500 MHz -BIT FMC CONNECTOR FMC CONNECTOR LVDS 0 Out 2 GHz -BIT D/A DIGITAL UPCONVERT 10X VIRTEX-7 VX330T or VX690T Out 2 GHz -BIT D/A DIGITAL UPCONVERT Out 2 GHz -BIT D/A DIGITAL UPCONVERT Out 2 GHz -BIT D/A DIGITAL UPCONVERT 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

264 FlexorSet Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - x8 Acquisition IP Modules The features four Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from any of the four s, a test signal generar or from the D/A Waveform Playback IP Modules in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. IP for data processing. Pentek Gate- Flow Design Kits include all of the facry-installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides pairs of LVDS connections between the and a cardedge connecr for cusm I/O. Option -110: For applications requiring optical gigabit links, up 12 high-speed, full-duplex lanes driven via an optical transceiver support serial procols. A 12-lane MTPoptical connecr is presented on the slot panel. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space D/A Waveform Playback IP Modules The facry-installed functions include four sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the four D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries per module can be chained gether create complex waveforms with a minimum of programming. Bank 1 From Ch 1 PACKING META ACQUISITION IP MODULE 1 From Ch 2 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL To Acq Modules 1 & 2 32 Bank 1 From Ch 3 INPUT MULTIPLEXER ACQUISITION IP MODULES 2&3 2 goes Bank 1 3 goes Bank 2 To Acq Modules 3 & 4 32 Bank 2 Bank 2 GPIO From Ch 4 PACKING META ACQUISITION IP MODULE 4 32 INTEACE D/A loopback Bank 3 8X To D/A Ch 1 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 1 To D/A Ch 2 D/A WAFEFORM PLAYBACK IP MODULES 2&3 2 goes Bank 3 3 goes Bank 4 To D/A Ch3 D/A loopback TEST SIGNAL Bank 4 To D/APlayback Modules 1 & 2 32 Bank 3 To D/A Ch 4 UNPACKING D/A WAVEFORM PLAYBACK IP MODULE 4 To D/APlayback Modules 3 & 4 32 Bank 4

265 FlexorSet Model Ch. 500 MHz -bit, 4-Ch. 2 GHz -bit D/A - x8 PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and from the board. Resources The architecture supports four independent memory banks. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Model 8266 The Model 8266 is a fullyintegrated PC development system for Pentek Cobalt, Onyx and Flexor PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel 500 MHz -bit, 4-Channel 2 GHz -bit D/A with Virtex-7 - x8 Options: -076 XC7VX690T LVDS I/O cardedge connecr x gigabit serial optical I/O with XC7VX690T, 4x w. XC7VX330T 8266 PC Development System See 8266 Datasheet for Options allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in 500 MHz, -bit converters. Digital Upconverter and D/A Stage Four D/As accept baseband real or complex data streams from the. Each stream then passes through the upconvert, interpolate and D/A stages of the converter. When operating as DUCs (digital upconverters), the converters interpolate and translate real or complex baseband input signals a programmable IF center frequency. The data is then delivered the -bit D/A converter stages. Analog outputs are through front panel connecrs. If translation is disabled, the D/As act as interpolating -bit D/As with output sampling rates up 2 GHz. In both modes the D/As provide interpolation facrs of 2x, 4x, 8x and x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock from the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC1-1TLB Full-Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 750 MHz Converters Type: Texas Instruments ADS54J60 Sampling Rate: Up 500 MHz Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full-Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz D/A Converters Type: Texas Instruments DAC38J84 Input Data Rate: Up 500 MHz Output Sample Rate: Up 2 GHz (with interpolation) Resolution: bits Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the and D/A clocks External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of LVDS connections between the and a card-edge connecr for cusm I/O Optical (Option -110): 12x gigabit serial optical I/O with XC7VX690T, 4x with XC7VX330T Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm)

266 Model 7120 Bandit Two-Channel Analog Wideband Downconverter - PMC/XMC Features Accepts signals from 400 MHz 4000 MHz Accepts input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference General Information The Bandit Model 7120 is a two-channel, high-performance, stand-alone analog wideband downconverter. Packaged in a small, shielded PMC/XMC module with front-panel connecrs for easy integration in systems, the module offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, the 7120 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The 7120 accepts signals on two front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Higher level signals can be attenuated prior input. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers The 7120 features a pair of Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy The 7120 uses an Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, the 7120 includes an on-board 10 MHz crystal oscillar which can be used as the reference lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Output is provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Tuning Control Gain 1 Control Gain 2 Control SYNTHESIZER In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional)

267 Model 7120 Bandit Two-Channel Analog Wideband Downconverter - PMC/XMC Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PMC/XMC Interface: Power only on PMC P11 (option -104) or XMC P15 (option -105) Size: Standard PMC module, 2.91 in. x 5.87 in. Ordering Information 7120 Bandit Two-Channel Analog Wideband Downconverter - PMC/XMC Option Description -015 Oven Controlled Refernece Oscillar -104 PMC P11 Power -105 XMC P15 Power pin connecr (Power only) GHz lowpass input filter GHz lowpass input filter

268 Model 7820 Bandit Two-Channel Analog Wideband Downconverter - Features Accepts signals from 400 MHz 4000 MHz Accepts input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference General Information The Bandit Model 7820 is a two-channel, high-performance, stand-alone analog wideband downconverter. Packaged in a small, shielded board with front-panel connecrs for easy integration in systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, the 7820 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The 7820 accepts signals on two front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Higher level signals can be attenuated prior input. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers The 7820 features a pair of Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy The 7820 uses an Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, the 7820 includes an on-board 10 MHz crystal oscillar which can be used as the reference lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Output is provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Tuning Control Gain 1 Control Gain 2 Control SYNTHESIZER In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional)

269 Model 7820 Bandit Two-Channel Analog Wideband Downconverter - Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI-Express Interface PCI Express Bus: x4 or x8, power only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Half length card, 4.38 in. x 7.13 in. Ordering Information 7820 Bandit Two-Channel Analog Wideband Downconverter - Option Description -015 Oven Controlled Reference Oscillar GHz lowpass input filter GHz lowpass input filter

270 Model 5220 Bandit Two-Channel Analog Wideband Downconverter - 3U VPX Model 5220 COTS (left) and rugged version Features Accepts signals from 400 MHz 4000 MHz Accepts input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference General Information The Bandit Model 5220 is a two-channel, high-performance, stand-alone analog wideband downconverter. Packaged in a small, shielded 3U VPX board with front-panel connecrs for easy integration in systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, the 5220 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The 5220 accepts signals on two front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Higher level signals can be attenuated prior input. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers The 5220 features a pair of Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy The 5220 uses an Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, the 5220 includes an on-board 10 MHz crystal oscillar which can be used as the reference lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Output is provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Tuning Control Gain 1 Control Gain 2 Control SYNTHESIZER In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional)

271 Model 5220 Bandit Two-Channel Analog Wideband Downconverter - 3U VPX Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI Express Interface Bus: x4, power only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: in. x in. (100 mm x mm) Ordering Information 5220 Bandit Two-Channel Analog Wideband Downconverter - 3U VPX Option Description -015 Oven Controlled Reference Oscillar GHz lowpass input filter GHz lowpass input filter

272 New! New! New! New! New! Models 5720 & 5820 Model 5820 Features Accept signals from 400 MHz 4000 MHz Accept input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference Bandit Two- or Four-Channel Analog Wideband Downconverter - 6U OpenVPX General Information These Bandit models are two- or four-channel, high-performance, stand-alone analog wideband downconverters. Packaged in small, shielded 6U VPX boards with front-panel connecrs for easy integration in systems, they offer programmable gain, high dynamic range and a low noise figure. Model 5720 is a 6U VPX board that provides two channels, while Model 5820 is a double-density 6U VPX board that provides four channels. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, these models are ideal solutions for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The models accept signals on two or four front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers These models feature Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy These models use the Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, these models include on-board 10 MHz crystal oscillars which can be used as the reference lock the internal LO frequency synthesizers. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Outputs are provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IFIOut IFQOut (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Gain 1 Control Gain 2 Control Tuning Control SYNTHESIZER Model 5720 Block Diagram Model 5820 Doubles all Resources. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IFIOut IFQOut (optional)

273 Models 5720 & 5820 Bandit Two- or Four-Channel Analog Wideband Downconverter - 6U OpenVPX Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI Express Interface PCI Bus: x4 or x8, power only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: 233 mm x 0 mm (9.173 in. x in.) Ordering Information 5720 Bandit Two-Channel Analog Wideband Downconverter - 6U VPX Single Density 5820 Bandit Four-Channel Analog Wideband Downconverter - 6U VPX Double Density Option Description -015 Oven Controlled Reference Oscillar GHz lowpass input filter GHz lowpass input filter

274 Models 7220, 7420 and 7320 Bandit Two- or Four-Channel Analog Wideband Downconverter - 6U/3U cpci Model 7420 Model 7320 Features Accept signals from 400 MHz 4000 MHz Accept input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference General Information These Bandit models are two- or four-channel, high-performance, stand-alone analog wideband downconverters. Packaged in small, shielded cpci boards with frontpanel connecrs for easy integration in systems, they offer programmable gain, high dynamic range and a low noise figure. Model 7320 is a 3U cpci booard while Model 7220 is a 6U cpci board; both provide two channels, while Model 7420 is a doubledensity 6U cpci board that provides four channels. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, these models are ideal solutions for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The models accept signals on two or four front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers These models feature Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy These models use the Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, these models include on-board 10 MHz crystal oscillars which can be used as the reference lock the internal LO frequency synthesizers. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Outputs are provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IFIOut IFQOut (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Tuning Control Gain 1 Control Gain 2 Control SYNTHESIZER In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IFIOut IFQOut (optional)

275 Models 7220, 7420 and 7320 Bandit Two- or Four-Channel Analog Wideband Downconverter - 6U/3U cpci Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI Interface PCI Bus: 32-bit, 66 MHz (supports 33 MHz), power only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 3U or 6U cpci board Ordering Information 7220 Bandit Two-Channel Analog Wideband Downconverter - 6U cpci 7320 Bandit Two-Channel Analog Wideband Downconverter - 3U cpci 7420 Bandit Four-Channel Analog Wideband Downconverter - 6U cpci Option Description -015 Oven Controlled Reference Oscillar GHz lowpass input filter GHz lowpass input filter

276 Model 5620 Bandit Two-Channel Analog Wideband Downconverter - AMC Features Accepts signals from 400 MHz 4000 MHz Accepts input levels from -60 dbm -20 dbm Baseband IF output with up 390 MHz bandwidth Internal OCXO or external 10 MHz frequency reference General Information The Bandit Model 5620 is a two-channel, high-performance, stand-alone analog wideband downconverter. Packaged in a small, shielded AMC board with front-panel connecrs for easy integration in systems, the board offers programmable gain, high dynamic range and a low noise figure. With an input frequency range from MHz and a wide IF bandwidth of up 390 MHz, the 5620 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The 5620 accepts signals on two front-panel SSMC connecrs. LNAs (Low Noise Amplifiers) are provided, along with two programmable attenuars allowing downconversion of input signals ranging from 60 dbm 20 dbm in steps of 0.5 db. Higher level signals can be attenuated prior input. Input Filter Options An optional five-stage lowpass or bandpass input filter can be included with several available frequency and attenuation characteristics for image rejection and harmonic suppression. Quadrature Mixers The 5620 features a pair of Analog Devices ADL5380 quadrature mixers. The ADL5380 s are capable of excellent accuracy with amplitude and phase balances of ~0.07 db and ~0.2, respectively. Tuning Accuracy The 5620 uses an Analog Devices ADF4351 low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy with a fractional-n phase-locked loop, its frequency is programmable across the 400 the 4000 MHz band with a tuning resolution of better than 100 khz. On-board Reference Clock In addition accepting a 10 MHz reference signal on the front panel, the 5620 includes an on-board 10 MHz crystal oscillar which can be used as the reference lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Wideband Output Output is provided as baseband I and Q signals at bandwidths up 390 MHz. Alternatively, either I or Q output can be used at some intermediate offset frequency convenient the application. User-provided in-line output IF filters allow cusmizing the output bandwidth and offset frequency the specific application requirements. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional) Gain 1 Control Gain 2 Control SYNTHESIZER Tuning Control Ref In USB USB INTEACE Gain 1 Control Gain 2 Control Tuning Control OVEN LED REFERENCE OSCILLATOR (option 015) Ref Out Tuning Control Gain 1 Control Gain 2 Control SYNTHESIZER In LOW NOISE AMP LOWPASS OR BANDPASS FILTER LOW NOISE AMP I/Q DOWNCONVERTER I Q LOW NOISE AMP IF I Out IF Q Out (optional)

277 Model 5620 Bandit Two-Channel Analog Wideband Doanconverter - AMC Specifications Input Connecr Type: SSMC Input Impedance: 50 ohms Input Level Range: 60 dbm 20 dbm Flatness: ±2 db from 400 MHz 1 GHz, ±3 db from 1 GHz 3 GHz, ±5 db from 3 GHz 4 GHz Attenuar: Programmable from 0 63 db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, Resolution: < 10 khz Tuning Speed: < 500 µsec Phase-Locked Loop Bandwidth: 100 khz Phase Noise 1 khz: 90 dbc/hz 100 khz: 110 dbc/hz 1 MHz: 130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference Input/Output Connecr Type: SSMC Input/Output Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm, sine wave Reference Output Signal Frequency: 10 MHz Level: 0 dbm, sine wave OCXO Reference Center Frequency: 10 MHz Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: 67 dbc/hz 10 Hz Offset: 100 dbc/hz 100 Hz Offset: 130 dbc/hz 1 KHz Offset: 148 dbc/hz 10 KHz Offset: 154 dbc/hz 100 KHz Offset: 155 dbc/hz IF Output Connecr Type: SSMC Output Impedance: 50 ohms Center Frequency: User definable Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext Reference Select, LO Synthesizer Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12 VDC Current: 1.5 A PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8, power only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Single-width, full-height AMC module, 2.89 in. x 7.11 in. Ordering Information 5620 Bandit Two-Channel Analog Wideband Downconverter - AMC Option Description -015 Oven Controlled Reference Oscillar GHz lowpass input filter GHz lowpass input filter

278 Model 8111 Bandit Modular Analog Slot Downconverter Series Features Accepts signals from 800 MHz GHz in seven different models Accepts input levels from dbm 225 MHz IF output with 80 MHz output bandwidth Internal OCXO or external 10 MHz frequency reference General Information The Bandit Model 8111 provides a series of high-performance, stand-alone analog slot downconverter modules. Packaged in a small, shielded enclosure with connecrs for easy integration in systems, the modules offer programmable gain, high dynamic range and a low noise figure. With input options cover specific frequency bands of the spectrum, and an IF output optimized for converters, the 8111 is an ideal solution for amplifying and downconverting antenna signals for communications, radar and signal intelligence systems. Programmable Input Level The 8111 accepts signals on a front panel SMA connecr. An LNA (Low Noisefigure Amplifier) is provided along with two programmable attenuars allowing downconversion of input signals ranging from -60 dbm -20 dbm in steps of 0.5 db. Higher level signals can be attenuated prior input. Preselecr Options Seven different input-frequency band options are offered, each tunable across a 400 MHz band, with an overlap of 100 MHz between adjacent bands. As a group, these seven options accommodate input signals from 800 MHz GHz as follows: Option Frequency Band MHz MHz MHz MHz MHz MHz MHz Tuning Accuracy The 8111 uses a low-noise, on-board frequency synthesizer as the LO (Local Oscillar). Locked an external input reference for accuracy, its frequency is programmable across the 400 MHz band with a tuning resolution of 1 MHz. Alternatively, for applications demanding cusm local oscillar characteristics, an external LO input signal can be accepted on a front panel connecr and used instead of the on-board frequency synthesizer. On-board Reference Clock In addition accepting a reference signal on the front panel, the 8111 includes an on-board 10 MHz crystal oscillar which can be used as the reference lock the internal LO frequency synthesizer. This reference is an OCXO (Oven Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. IF Output An 80 MHz-wide IF output is provided at a 225 MHz center frequency. This output is suitable for conversion using Pentek high-performance signal acquisition products, such as those in the Cobalt and Onyx families. In LOW NOISE AMP BANDPASS FILTER STEP ATTENUATOR GAIN BLOCK MIXER GAIN BLOCK IF FILTER STEP ATTENUATOR GAIN BLOCK IF Out Control In USB INTEACE Attenuation IF Attenuation LO Select LO Synthesizer Tuning Frequency GAIN BLOCK SWITCH LO OVEN LED CRYSTAL OSCILLATOR Ref In Ext LO In Ref Out

279 Model 8111 Bandit Modular Analog Slot Downconverter Series Specifications Input Connecr Type: SMA Input Impedance: 50 ohms Input Level Range: -60 dbm -20 dbm Flatness: ±1 db typical over each 400 MHz range Attenuar: Programmable from db in 0.5 db steps LO Synthesizer Tuning Frequency range: MHz, across seven different options Resolution: 1 MHz Tuning Speed: < 500 µsec PLL Loop Bandwidth: 100 khz Phase Noise 1 khz: -90 dbc/hz 100 khz: -110 dbc/hz 1 MHz: -130 dbc/hz Noise Figure (referred input) 60 db gain: 2.6 db Inband Output IP3 20 db gain: +10 dbm 60 db gain: +42 dbm Reference / External LO Input Connecr Type: SMA Input Impedence: 50 ohms Reference Input Signal Frequency: 10 MHz Level: 0 dbm +20 dbm, sinewave External LO Input Signal Frequency: ƒ IN +225 MHz, where ƒ IN = input signal frequency Level: 0 dbm ±2 dbm OCXO Reference Output Connecr Type: SMA Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dbm, nominal, sine wave Frequency Stability vs. Change in Temperature: ±50.0 ppb Frequency Calibration: ±1.0 ppm Aging Daily: ±10 ppb/day First Year: ±300 ppb Total Frequency Tolerance (20 years): ±4.60 ppm Phase Noise 1 Hz Offset: -67 dbc/hz 10 Hz Offset: -100 dbc/hz 100 Hz Offset: -130 dbc/hz 1 KHz Offset: -148 dbc/hz 10 KHz Offset: -154 dbc/hz 100 KHz Offset: -155 dbc/hz IF Attenuar: Programmable from db in 0.5 db steps IF Output Connecr Type: SMA Output Impedance: 50 ohms Center Frequency: 225 MHz Output Level: 0 dbm, nominal Programming Functions: Atten, IF Atten, Int/Ext LO Select, LO Synthezier Frequency Interface: USB Connecr Type: MicroUSB Power Voltage: +12VDC Current: 1.5 A Connecr Type: Micro DB-9, female Size: Module, 3.75 in x 7.5 in x 0.7 in Ordering Information 8111 Bandit Modular Analog Slot Downconverter Option Input Frequency Band MHz MHz MHz MHz MHz MHz MHz

280 New! New! New! New! New! Features Model U 19-inch rackmount, 9-slot, -inch deep chassis which houses 6U VPX boards 64-bit Windows 7 Professional or Linux workstation Intel Core TM i7 3.6 GHz processor GB ReadyFlow drivers and board support libraries installed Out-of-the-box ready--run examples 6U OpenVPX Development System for Cobalt and Onyx Boards General Information The Model 8264 is a fully-integrated, 6U VPX development system for Pentek Cobalt and Onyx software radio, data acquisition, and I/O boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. A fully-integrated system-level solution, the 8264 provides the user with a streamlined out-of-the-box experience. It comes preconfigured with Pentek hardware, drivers and software examples installed and tested allow development engineers run example applications out of the box. ReadyFlow Software Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the ReadyFlow includes example applications with full source code, a command line interface for cusm control over hardware, and Pentek s Signal Analyzer, a full-featured analysis ol that continuously displays live signals in both time and frequency domains. System Implementation Built on a professional 9U rackmount workstation, the 8264 is equipped with the latest Intel i7 processor, and a high-performance single-board computer. These features accelerate application code development and provide unhindered access the high-bandwidth data available with Cobalt and Onyx analog and digital interfaces. The 8264 can be configured with 64-bit Windows or Linux operating systems. The 8264 uses a 19 9U rackmount chassis that is deep. Nine VPX slots provide ample space for an SBC, a switch card and multiple Pentek boards. Enhanced forcedair ventilation assures adequate cooling for all boards and dual 500-W power supplies gurantee more than adequate power for all installed boards. Mounting provisions for two 3.5 in. drives with front-accessible trays allow for easy removable srage. Front-panel access USB, display, Ethernet and RS-232 ports simplifies development; an optional rear transition module supplements the frontpanel connections with SATA, audio, a second video interface, and additional USB ports. Configuration All 8264 systems come with software and hardware installed and tested. Up seven Pentek boards in the 8264 can be supported. Please contact Pentek configure a system that matches your specific requirements. Options Available options include high-end multicore CPUs and choice of Windows or Linux. Specifications Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz : GB Dimensions: 6U Chassis, 19" W x " D x 10.5" H Weight: 50 lb, approx. Operating Temp: C Srage Temp: C Relative Humidity: 5 95%, non-condensing Power Requirements: VAC, Hz, 1000 W max. Ordering Information U VPX Development System for Cobalt and Onyx Boards Options: bit Linux OS bit Windows 7 OS The addition of third-party VPX boards may affect system performance. Please consult with us before doing so.

281 Model 8266 PC Development System for Cobalt, Onyx and Flexor Boards Features 4U 19-inch rackmount PC server chassis, 21-inch deep 64-bit Windows 7 Professional or Linux workstation Intel Core TM i7 3.6 GHz processor 8 GB ReadyFlow drivers and board support libraries installed Out-of-the-box test examples General Information The Model 8266 is a fully-integrated PC development system for Pentek Cobalt, Onyx and Flexor TM PCI Express software radio, data acquisition, and I/O boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. A fully-integrated system-level solution, the 8266 provides the user with a streamlined out-of-the-box experience. It comes preconfigured with Pentek hardware, drivers and software examples installed and tested allow development engineers run example applications out of the box. ReadyFlow Software Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the ReadyFlow includes example applications with full source code, a command line interface for cusm control over hardware, and Pentek s Signal Analyzer, a full-featured analysis ol that continuously displays live signals in both time and frequency domains. System Implementation Built on a professional 4U rackmount workstation, the 8266 is equipped with the latest Intel processor, and a high-performance motherboard. These features accelerate application code development and provide unhindered access the high-bandwidth data available with Cobalt, Onyx and Flexor analog and digital interfaces. The 8266 can be configured with 64-bit Windows or Linux operating systems. The 8266 uses a 19 4U rackmount chassis that is 21 deep. Enhanced forcedair ventilation assures adequate cooling for Pentek Cobalt, Onyx and Flexor boards. The chassis is designed draw cool air from the front and push warm air out the back. A 1000 W, 80+ Gold Power Supply guarantees more than enough power for additional boards. Configuration Pentek uses a variety of motherboards provide the flexibility for operation and cooling of each system. Up four Pentek Cobalt, Onyx or Flexor boards in the 8266 can be supported. Please contact Pentek configure a system that requires additional slots for 3rd party hardware. Options Options for high-end multicore CPUs and extended memory support applications that require additional horsepower are available. Specifications Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz : 8 GB Dimensions: 4U Chassis, 19" W x 21" D x 7" H Weight: 35 lb, approx. Operating Temp: C Srage Temp: C Relative Humidity: 5 95%, non-condensing Power Requirements: VAC, Hz, 1000 W max. Ordering Information 8266 PC Development System for Cobalt, Onyx and Flexor Boards Options: bit Linux OS bit Windows 7 OS -101 Upgrade 64 GB The addition of third-party cards may affect system performance. Please consult with us before doing so.

282 New! New! New! New! New! Features Model slot, 4U 19-inch rackmount, 12-inch deep chassis which houses 3U VPX boards 64-bit Windows 7 Professional or Linux workstation Intel Core TM i7 3.6 GHz processor 8 GB ReadyFlow drivers and board support libraries installed Out-of-the-box ready--run examples 3U VPX Development System for Cobalt, Onyx and Flexor Boards General Information The Model 8267 is a fully-integrated, 3U VPX development system for Pentek Cobalt, Onyx and Flexor TM software radio, data acquisition, and I/O boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. A fully-integrated system-level solution, the 8267 provides the user with a streamlined out-of-the-box experience. It comes preconfigured with Pentek hardware, drivers and software examples installed and tested allow development engineers run example applications out of the box. ReadyFlow Software Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the ReadyFlow includes example applications with full source code, a command line interface for cusm control over hardware, and Pentek s Signal Analyzer, a full-featured analysis ol that continuously displays live signals in both time and frequency domains. System Implementation Built on a professional 4U rackmount workstation, the 8267 is equipped with the latest Intel i7 processor, and a high-performance single-board computer. These features accelerate application code development and provide unhindered access the high-bandwidth data available with Cobalt, Onyx and Flexor analog and digital interfaces. The 8267 can be configured with 64-bit Windows or Linux operating systems. The 8267 uses a 19 4U rackmount chassis that is 12 deep. Nine VPX slots provide ample space for an SBC, a switch card and multiple Pentek boards. Enhanced forcedair ventilation assures adequate cooling for all boards and dual 250-W power supplies gurantee more than adequate power for all installed boards. Mounting provisions for two 3.5 in. drives with front-accessible trays allow for easy removable srage. Front-panel access USB, display, Ethernet and RS-232 ports simplifies development; an optional rear transition module supplements the frontpanel connections with SATA, audio, a second video interface, and additional USB ports. Configuration All 8267 systems come with software and hardware installed and tested. Up seven Pentek boards in the 8267 can be supported. Please contact Pentek configure a system that matches your specific requirements. Options Available options include high-end multicore CPUs and extended memory support. Specifications Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz : 8 GB standard, GB optional Dimensions: 4U Chassis, 19" W x 12" D x 7" H Weight: 35 lb, approx. Operating Temp: C Srage Temp: C Relative Humidity: 5 95%, non-condensing Power Requirements: VAC, Hz, 1000 W max. Ordering Information U VPX Development System for Cobalt, Onyx and Flexor Boards Options: bit Linux OS bit Windows 7 OS -101 Upgrade GB The addition of third-party VPX boards may affect system performance. Please consult with us before doing so.