Signal Conversion in a Modular Open Standard Form Factor. CASPER Workshop August 2017 Saeed Karamooz, VadaTech

Transcription

1 Signal Conversion in a Modular Open Standard Form Factor CASPER Workshop August 2017 Saeed Karamooz, VadaTech

2 At VadaTech we are technology leaders First-to-market silicon Continuous innovation Open systems expertise commit to our customers Partnerships power innovation Collaborative approach Mutual success deliver complexity End-to-end processing System management Configurable solutions manufacture in-house Agile production Accelerated deployment AS9100 Accredited 2

3 High-Speed Backplane External Memory ANALOG ANALOG Need an FPGA For highly flexible and high-bandwidth I/O interfacing For in-circuit/real-time DSP capabilities Analog to Digital Converter (ADC) Digital to Analog Converter (DAC) May need high-speed external memory DDR-4 QDR SRAM Signal Conversion Requirements ADC DAC FPGA 3

4 High-end FPGA Xilinx Altera High-end ADC/DAC (sampling greater than 3GSPS) Texas Instrument Analog Devices E2V Technologies Ultra High-end (sampling higher than 14GSPS) Fujitsu Keysight FPGA and ADC/DAC Suppliers 4

5 ADC/DAC Interface to FPGA Lower sampling rates LVDS More Lanes Lower Latency Higher Sampling rates JESD204B SERDES Less Lanes Higher Latency License from the FPGA Suppliers 5

6 FPGA Technology is Moving Fast Die shrink has helped to bring out higher density devices Reduced power Increase in fabric speed Higher speed SERDES (Serializer and Deserializer) communications Faster memory interfaces Bring down the cost 6

7 Xilinx Virtex-4 Virtex-5 Virtex-6 Virtex-7 Virtex UltraScale Virtex UltraScale+ Altera Stratix-IV Stratix-V Stratix-10 (Altera is now Intel Programmable Solutions Group) SOC FPGAs incorporate multiple ARM processor cores/peripherals in addition to fabric Xilinx Zynq-7000 SOC Zynq UltraScale+ MPSoC Altera Arria-V SOC Arria-10 SOC FPGA Technology Progression 7

8 Constant Innovation from High-Speed to Ultra High-Speed ADC High speed [MHz]: High-density, lower analog BW, highest resolution Innovative flexibility, lower cost per channel Very High speed [GHz]: Low-mid density, higher analog BW, high resolution Large combination of AD/DA, higher cost per channel Ultra High Speed [>14GHz]: Low-mid density, widest analog BW, lower resolution Innovative integration, highest cost per channel 8

9 High Speed ADC - Support for Multiple Sensor Types Analog front end depends on the application (sensor/measurement). VadaTech s innovative design maximizes flexibility, adjusting the product to the application requirements. DAQ523 includes XC7K410T FPGA and twelve 16-bit with mezzanine on the rear transition module. Available with: Passive mezzanine (MZ523A) for lowest input noise Programmable gain/coupling mezzanine (MZ523B) to fit multiple sensors with one board Optical detector mezzanine (MZ523C) for 1310 to 1650 nm with programmable gain Published specification for customer to design their own custom front end as required MRT523 MRT523 with MZ523B MRT523 with MZ523C 9

10 Very High Speed ADC & DAC Sampling signals with analog BW up to 9 GHz Mixed A/D and D/A channels on-board JESD204B reduces space needed by about 25% Management of heat density (thermal analysis, cooling, IPMI) Typically AC coupled, single-ended e.g. AMC599 Dual 6.4 GSPS and Dual 12 GSPS 10

11 Ultra High Speed ADC 8-bit ADC with dual 56 GSPS or quad 26 GSPS, generating 896 Gb/s data stream AMC594 with Xilinx UltraScale XCVU190 FPGA: 60 GTH 16.3Gb/s Transceivers and 60 GTY 30.5Gb/s Transceiver for data transfer 2,350k system logic cells and 1,800 DSP slices for heavy processing High-speed Zone 3 connector supports over 500 Gb/s off-board data routing via dedicated Zone 3 PCB Highest analog bandwidth (-3 db analog input bandwidth nominally >15GHz) AMC594 Two AMC594 assembled with Zone 3 PCB VT815 11

12 FPGA Product Range: FMC carriers AMC502 Kintex-7 XCK7420T Dual FMC Carrier AMC515 Virtex-7 XC7V2000T FMC Carrier AMC516 Virtex-7 XC7VX690T FMC Carrier AMC517 Kintex-7 XCK7410T FMC Carrier AMC518 Zynq-7000 XC7C100 FMC Carrier AMC519 Artix-7 XC7A200T FMC Carrier AMC525 Virtex-7 XC7VX690T Dual FMC Carrier AMC527 Virtex-7 XC7VX690T FMC Carrier AMC580 Zynq UltraScale+ XCZU19EG Dual FMC Carrier AMC581 Zynq UltraScale+ XCZU15EG FMC Carrier AMC582 Zynq UltraScale+ XCZU19EG FMC Carrier AMC583 Kintex UltraScale XCKU115 Dual FMC+ Carrier AMC592 Kintex UltraScale XCKU115 FMC Carrier AMC593 Kintex UltraScale XCKU115 Dual FMC Carrier AMC595 Virtex UltraScale XCVU440 FMC Carrier AMC596 Virtex UltraScale XCVU440 FPGA Processor Virtex-6 and earlier as well as Altera-based excluded for brevity 12

13 FPGA Product Range: Dedicated ADC / DAC / Digital I/O AMC521 Virtex-7 XC7VX690T ADC AMC522 Kintex-7 XC7K420T ADC/DAC AMC523 Kintex-7 XCK7410T ADC/DAC AMC524 Artix-7 XC7A200T ADC/DAC AMC526 Virtex-7 XC7VX690T ADC AMC529 Virtex-7 XC7VX690T DAC AMC540 Virtex-7 XC7VX690T Dual DSP AMC590 Kintex UltraScale XCKU115 ADC AMC591 Virtex UltraScale XCVU190 ADC AMC594 Virtex UltraScale XCVU190 ADC AMC597 Kintex UltraScale XCKU115 MIMO txcvr AMC599 Kintex UltraScale XCKU115 ADC/DAC CM045 Kintex-7 XC7K420T Digital I/O Virtex-6 and earlier as well as Altera-based excluded for brevity 13

14 FPGA Processing Performance Xilinx 7-series, UltraScale, and UltraScale+ modules Altera (Intel PSG) Arria-10, Stratix-V First-to-market AMC582 with multiprocessor system-on-chip (MPSoC) XCZU7EV and AMC580 dual FMC HPC XCZU19EG MTCA.4 AMC582 AMC580 14

15 Integration of Analog Front End on Standard Form Factor Analog signal conditioning integrated into MTCA or ATCA Analog signals connected to AMC902 inputs for signal conditioning (programmable filtering and gain). AMC902 outputs are connected to the ADC board inputs installed in another slot of the chassis. Gain and Filtering control is performed via GbE standard port 0. AMC902 15

16 Clocks and Trigger Designed for external or internal trigger (radial only for utca.0, radial and bused for utca.4) Designed for internal clock generation or external clock sourcing Standard architecture with configurable clocking switch and internal clock distribution from/to all slots Easy integration with existing external clock systems Multi-channel / multi-board synchronization FMC154 Local Oscillator module Third party clocking system in VT812, clocking diagram of VT811 16

17 DAQ Series Software for High-Speed and Very High-Speed Acquisition Solution Complete solution: IP development & integration, clocking setup, DMA, data display, monitoring Open architecture (EPICS, Qt) Compatibility with market leader tools MATLAB/Simulink/Vivado Customizable Full source provided High performance Advanced DMA engine Real-time full acquisition chain testing and monitoring Consistent across hardware platforms (FMC, AMC, VPX, PCIe) DAQ Series GUI real time display and configuration 17

18 Platform level solution 16 channel 8-bit ADC with synchronous capture and precision TDC calibration capabilities All ADC channels route through Xilinx Virtex-7 XC7VX485T FPGA On-board NVidia Jetson TX2 System-on-Module for signal analysis Desktop or 19 rack mount, fully integrated solution 18

19 MCH Fabric Options 10GbE/40GbE/SRIO/PCIe/CBS backplane fabrics available across the MCH range UTC004 PCIe ExpressFabric option PEX9765 supports efficient CPU-to-CPU DMA and multiple hosts per end point UTC006 FPGA-based Fabric option Virtex-7 690T in place of fabric switch supports lowlatency Aurora and complex scatter/gather directly to the AMCs from the central MCH slot UTC004 and UTC006 19

20 Configurable Crossbar Switch at Oak Ridge National Laboratory To mitigate risks associated with hazards, the accelerator utilizes a Machine Protection System (MPS). The MPS monitors more than 1,000 sensors throughout the accelerator complex for potential problems. When such problems are detected, the MPS must terminate beam production within 20 microseconds to protect accelerator components. VadaTech overcomes the limitation of non-deterministic non-low-latency protocols by offering complete flexibility in both interface protocol and the routing of information between blades with a Configurable Crossbar Switch. Oak Ridge National Laboratory s Spallation Neutron Source Uses a Linear Accelerator and Accumulator Ring to Generate a 1.4MW pulsed proton beam. Illustration of Typical MPS Hierarchical Topology 20

21 Any Questions? 21