Preliminary W78E51B 8-BIT MTP MICROCONTROLLER GENERAL DESCRIPTION FEATURES

Transcription

1 reliminary W78E5B 8-BIT MT MICROCONTROER GENER ESCRITION The W78E5B is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption The instruction set for the W78E5B is fully compatible with the standard 85 The W78E5B contains an K bytes MT ROM (Multiple-Time rogrammable ROM); a 8 bytes RM; four 8-bit bi-directional and bit-addressable I/O ports; an additional -bit I/O port ; two 6-bit timer/counters; a hardware watchdog timer and a serial port These peripherals are supported by seven sources two-level interrupt capability To facilitate programming and verification the MT- ROM inside the W78E5B allows the program memory to be programmed and read electronically Once the code is confirmed the user can protect the code for security The W78E5B microcontroller has two power reduction modes idle mode and power-down mode both of which are software selectable The idle mode turns off the processor clock but allows for continued peripheral operation The power-down mode stops the crystal oscillator for minimum power consumption The external clock can be stopped at any time and in any state without affecting the processor FETURES Fully static design 8-bit CMOS microcontroller Wide supply voltage of 5V to 55V 8 bytes of on-chip scratchpad RM KB electrically erasable/programmable MT-ROM 6 KB program memory address space 6 KB data memory address space Four 8-bit bi-directional ports One extra -bit bit-addressable I/O port additional INT / INT (available on -pin CC/QF package) Two 6-bit timer/counters One full duplex serial port(urt) Watchdog Timer seven sources two-level interrupt capability EMI reduction mode Built-in power management Code protection mechanism ackages: I : W78E5B-/ CC : W78E5B-/ QF : W78E5BF-/ ublication Release ate: ecember Revision

2 reliminary W78E5B IN CONFIGURTIONS -in I (W78E5B) RST RX TX INT INT T T 5 WR 6 R 7 XT XT VSS V E E SEN in CC (W78E5B) / I N T V -in QF (W78E5BF) / I N T V RST RX INT TX INT INT T T E E SEN RST RX INT TX INT INT T T E E SEN / W R 7 / R X T X T V S S / W R 7 / R X T X T V S S

3 reliminary W78E5B IN ESCRITION SYMBO E ESCRITIONS EXTERN CCESS ENBE: This pin forces the processor to execute out of external ROM It should be kept high to access internal ROM The ROM address and data will not be presented on the bus if E pin is high and the program counter is within on-chip ROM area SEN ROGRM STORE ENBE: SEN enables the external ROM data onto the ort address/ data bus during fetch and MOVC operations When internal ROM access is performed no SEN strobe signal outputs from this pin E RST XT XT VSS V RESS TCH ENBE: E is used to enable the address latch that separates the address from the data on ort RESET: high on this pin for two machine cycles while the oscillator is running resets the device CRYST: This is the crystal oscillator input This pin may be driven by an external clock CRYST: This is the crystal oscillator output It is the inversion of XT GROUN: Ground potential OWER SUY: Supply voltage for operation ORT : ort is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory The pins of ort can be individually configured to open-drain or standard port with internal pull-ups ORT : ort is a bi-directional I/O port with internal pull-ups The bits have alternate functions which are described below: T(): Timer/Counter external count input TEX(): Timer/Counter Reload/Capture control ORT : ort is a bi-directional I/O port with internal pull-ups This port also provides the upper address bits for accesses to external memory ORT : ort is a bi-directional I/O port with internal pull-ups ll bits have alternate functions which are described below: RX() : Serial ort receiver input TX() : Serial ort transmitter output INT () : External Interrupt INT() : External Interrupt T() : Timer External Input T(5) : Timer External Input WR (6) : External ata Memory Write Strobe R (7) : External ata Memory Read Strobe ORT : nother bit-addressable bidirectional I/O port and are alternative function pins It can be used as general I/O port or external interrupt input sources (INT /INT ) ublication Release ate: ecember Revision

4 reliminary W78E5B BOCK IGRM ~ 7 ort ort atch INT INT Interrupt CC T T B ort atch ort ~ 7 URT Timer Timer SW U Stack ointer TR Temp Reg C Incrementor ddr Reg ~ 7 ~ ort ort ort atch ort atch Instruction ecoder & Sequencer Bus & Clock Controller SFR RM ddress 8 bytes RM & SFR ROM Watchdog Timer ort atch ort ~ 7 Oscillator Reset Block ower control XT XT E SEN RST Vcc Vss FUNCTION ESCRITION The W78E5B architecture consists of a core controller surrounded by various registers five general purpose I/O ports 8 bytes of RM two timer/counters and a serial port The processor supports different opcodes and references both a 6K program address space and a 6K data storage space New efined eripheral In order to be more suitable for I/O an extra -bit bit-addressable port and two external interrupt INT INT has been added to either the CC or QF pin package nd description follows: - -

5 reliminary W78E5B INT / INT Two additional external interrupts INT and INT whose functions are similar to those of external interrupt and in the standard 8C5 The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register The XICON register is bit-addressable but is not a standard register in the standard 8C5 Its address is at CH To set/clear bits in the XICON register one can use the "SETB (/CR) bit" instruction For example "SETB CH" sets the EX bit of XICON XICON - external interrupt control (CH) X EX IE IT X EX IE IT X: External interrupt priority high if set EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software X: External interrupt priority high if set EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INTERRUT SOURCE VECTOR RESS OING SEQUENCE WITHIN RIORITY EVE ENBE REQUIRE SETTINGS INTERRUT TYE EGE/EVE External Interrupt H (highest) IE TCON Timer/Counter BH IE - External Interrupt H IE TCON Timer/Counter BH IE - Serial ort H IE - External Interrupt H 5 XICON XICON External Interrupt BH 6 (lowest) XICON6 XICON ORT nother bit-addressable port is also available and only bits (<:>) can be used This port address is located at 8H with the same function as that of port except the and are alternative function pins It can be used as general I/O pins or external interrupt input sources (INT INT ) Example: REG 8H MOV #H ; Output data "" through MOV ; Read status to ccumulator SETB ; Set bit CR ; Clear bit ublication Release ate: ecember Revision

6 reliminary W78E5B Reduce EMI Emission Because of on-chip MT-ROM when a program is running in internal ROM space the E will be unused The transition of E will cause noise so it can be turned off to reduce the EMI emission if it is useless Turning off the E signal transition only requires setting the bit of the UXR SFR which is located at 8Eh When E is turned off it will be reactivated when the program accesses external ROM/RM data or jumps to execute an external ROM code The E signal will turn off again after it has been completely accessed or the program returns to internal ROM code space The O bit in the UXR register when set disables the E output In order to reduce EMI emission from oscillation circuitry W78E5B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register Once B7 is set to a half of gain will be decreased Care must be taken if user attempts to diminish the gain of oscillator amplifier reducing a half of gain may effect to external crystal operating improperly at high frequency above MHz The value of R and CC may need adjustment while running at lower gain ***UXR - uxiliary register (8EH) O O: Turn off E output ower-off Flag ***CON - ower control (87H) OF GF GF I OF: ower off flag Bit is set by hardware when power on reset It can be cleared by software to determine chip reset is a warm boot or cold boot GF GF: These two bits are general-purpose flag bits for the user : ower down mode bit Set it to enter power down mode I: Idle mode bit Set it to enter idle mode The power-off flag is located at CON This bit is set when V has been applied to the part It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor a time-base generator or an event timer It is basically a set of dividers that divide the system clock The divider output is selectable and determines the time-out interval When the time-out occurs a system reset can also be caused if it is enabled The main use of the Watchdog timer is as a system monitor This is important in real-time control applications In case of power glitches or electro-magnetic interference the processor may begin to execute errant code If this is left unchecked the entire system may crash The watchdog time-out selection will result in different time-out values depending on the clock speed The Watchdog timer will de disabled on reset In general software should restart the Watchdog timer to put it into a known state The control bits that support the Watchdog timer are discussed below - 6 -

7 reliminary W78E5B Watchdog Timer Control Register Bit: ENW CRW WI - - S S S Mnemonic: WTC ddress: 8FH ENW : Enable watch-dog if set CRW: Clear watch-dog timer and prescaler if set This flag will be cleared automatically WI : If this bit is set watch-dog is enabled under IE mode If cleared watch-dog is disabled under IE mode efault is cleared S S S: Watch-dog prescaler timer select rescaler is selected when set S~ as follows: S S S RESCER SEECT The time-out period is obtained using the following equation : RESCER ms OSC Before Watchdog time-out occurs the program must clear the -bit timer by writing to WTC6 (CRW) fter is written to this bit the -bit timer prescaler and this bit will be reset on the next instruction cycle The Watchdog timer is cleared on reset WI ENW IE EXTERN RESET OSC / RESCER -BIT TIMER CER INTERN RESET Watchdog Timer Block iagram CRW ublication Release ate: ecember Revision

8 reliminary W78E5B Typical Watch-og time-out period when OSC = MHz Clock S S S WTCHOG TIME-OUT ERIO 966 ms 9 ms 786 ms 578 ms 57 ms 69 ms 5 S 5 S The W78E5B is designed to be used with either a crystal oscillator or an external clock Internally the clock is divided by two before it is used This makes the W78E5B relatively insensitive to duty cycle variations in the clock The W78E5B incorporates a built-in crystal oscillator To make the oscillator work a crystal must be connected across pins XT and XT In addition a load capacitor must be connected from each pin to ground n external clock source should be connected to pin XT in XT should be left unconnected The XT input is a CMOS-type input as required by the crystal oscillator ower Management Idle Mode The idle mode is entered by setting the I bit in the CON register In the idle mode the internal clock to the processor is stopped The peripherals and the interrupt logic continue to be clocked The processor will exit idle mode when either an interrupt or a reset occurs ower-down Mode When the bit of the CON register is set the processor enters the power-down mode In this mode all of the clocks are stopped including the oscillator The only way to exit power-down mode is by a reset Reset The external RESET signal is sampled at S5 To take effect it must be held high for at least two machine cycles while the oscillator is running n internal trigger circuit in the reset line is used to deglitch the reset line when the W78E5B is used with an external RC network The reset logic also has a special glitch removal circuit that ignores glitches on the reset line uring reset the ports are initialized to FFH the stack pointer to 7H CON (with the exception of bit ) to H and all of the other SFR registers except SBUF to H SBUF is not reset ON-CHI MT ROM CHRCTERISTICS The W78E5B has several modes to program the on-chip MT-ROM ll these operations are configured by the pins RST E SEN 9CTR() CTR() CTR() OECTR() CE (6) OE (7) () and V(E ) Moreover the 5 (7-8 -

9 reliminary W78E5B 7 ) and the 7 (7 ) serve as the address and data bus respectively for these operations Read Operation This operation is supported for customer to read their code and the Security bits The data will not be valid if the ock bit is programmed to low Output isable Condition When the OE is set to high no data output appears on the 7 rogram Operation This operation is used to program the data to MT ROM and the security bits rogram operation is done when the Vpp is reach to Vcp (5V) level CE set to low and OE set to high rogram Verify Operation ll the programming data must be checked after program operations This operation should be performed after each byte is programmed; it will ensure a substantial program margin Erase Operation n erase operation is the only way to change data from to This operation will erase all the MT ROM cells and the security bits from to This erase operation is done when the Vpp is reach to Vep level CE set to low and OE set to high Erase Verify Operation fter an erase operation all of the bytes in the chip must be verified to check whether they have been successfully erased to or not The erase verify operation automatically ensures a substantial erase margin This operation will be done after the erase operation if Vpp = Vep (5V) CE is high and OE is low rogram/erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data When 6( CE )= VIH 7( OE ) = VIH erasing or programming of non-targeted chips is inhibited So except for the 6 and 7 pins the individual chips may have common inputs ublication Release ate: ecember Revision

10 reliminary W78E5B Company/evice I Read Operation This operation is supported for MT ROM programmer to get the company I or device I on the W78E5B OERTIONS (9 CTR) ( CTR) ( CTR) (OE CTR) 6 ( CE ) 7 ( OE ) E (V) (5) (7) Read ddress ata Out Output isable X Hi-Z rogram VC ddress ata In rogram Verify NOTE VC ddress ata Erase VE : others: X ata In FFH Erase Verify VE ddress ata rogram/eras e Inhibit X VC/ VE Company I = ata Out evice I = ata Out Notes: ll these operations happen in RST = VIH E = and SEN = VIH VC = 5V VE = 5V VIH = V = Vss The program verify operation follows behind the program operation This erase operation will erase all the on-chip MT-ROM cells and the Security bits 5 The erase verify operation follows behind the erase operation X SECURITY BITS uring the on-chip MT-ROM operation mode the MT-ROM can be programmed and verified repeatedly Until the code inside the MT-ROM is confirmed OK the code can be protected The protection of MT ROM and those operations on it are described below The W78E5B has several Special Setting Registers including the Security Register and Company/evice I Registers which can not be accessed in normal mode These registers can only be accessed from the MT-ROM operation mode Those bits of the Security Registers can not be changed once they have been programmed from high to low They can only be reset through erase-all operation The contents of the Company I and evice I registers have been set in factory Both registers are addressed by the address line during the same specific condition The Security Register is addressed in the MT-ROM operation mode by address #FFFFh - -

11 reliminary W78E5B Company I (#H) KB MT ROM h evice I (#EH) rogram Memory B7 Reserved B B B B : ock bit logic : active Security Bits B : MOVC inhibit logic : the MOVC instruction in external memory cannot access the code in internal memory logic : no restriction B : Encryption logic : the encryption logic enable logic : the encryption logic disable B7 : Osillator Control logic : / gain logic : Full gain efault for all security bits Reserved bits must be kept in logic Special Setting Registers Reserved Security Register FFFh FFFFh ock bit This bit is used to protect the customer's program code in the W78E5B It may be set after the programmer finishes the programming and verifies sequence Once this bit is set to logic both the MT ROM data and Special Setting Registers can not be accessed again MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction It can prevent the MOVC instruction in external program memory from reading the internal program code When this bit is set to logic a MOVC instruction in external program memory space will be able to access code only in the external memory not in the internal memory MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory If this bit is logic there are no restrictions on the MOVC instruction Encryption This bit is used to enable/disable the encryption logic for code protection Once encryption feature is enabled the data presented on port will be encoded via encryption logic Only whole chip erase will reset this bit +5V +5V V V to 7 GM T to 7 GM T VIH 6 7 E/Vpp E RST SEN VC VIH VIH VIH 6 7 E/Vpp E RST SEN VC VIH VIH X'tal X'tal 8 to 5 X'tal X'tal 8 to 5 Vss Vss rogramming Configuration rogramming Verification ublication Release ate: ecember Revision

12 reliminary W78E5B BSOUTE MXIMUM RTINGS RMETER SYMBO MIN MX UNIT C ower Supply V VSS - +7 V Input Voltage VIN VSS - V + V Operating Temperature T 7 C Storage Temperature TST C Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device C CHRCTERISTICS VCC VSS = 5V ±% T = 5 C unless otherwise specified RMETER SYMBO TEST CONITIONS SECIFICTION UNIT MIN MX Operating Voltage V 5 55 V Operating Current I No load V = 55V - m Idle Current IIE Idle mode V = 55V - 6 m ower own Current IWN ower-down mode Input Current ogical -to- Transition Current (*) V = 55V IIN V = 55V VIN = V or V Input Current IIN V = 55V RST (*) VIN = V Input eakage Current E Output ow Voltage - 5 µ -5 + µ IT V = 55V VIN = V (*) µ IK V = 55V V < VIN < V VO V = 5V IO = + m Output ow Voltage VO V = 5V E SEN (*) IO = + m Output High Voltage VOH V = 5V IOH = - µ Output High Voltage VOH V = 5V E SEN (*) IOH = - µ - + µ - + µ - 5 V - 5 V - V - V - -

13 reliminary W78E5B C Characteristics continued RMETER SYMBO TEST CONITIONS SECIFICTION UNIT Input ow Voltage (Except RST) MIN MX V = 5V 8 V Input ow Voltage V = 5V 8 V RST (*) Input ow Voltage V = 5V 8 V XT (*) Input High Voltage (Except RST) Sink Current VIH V = 5V V + V ISK V = 5V Vs = 5V m Input High Voltage VIH V = 5V 67 V V + V RST (*) Input High Voltage VIH V = 5V 67 V V + V XT (*) Sink Current ISK V = 5V E SEN (*) Vs = 5V Source Current ISR V = 5V V S = V Source Current ISR V = 5V E SEN (*) V s = V Notes: 8 6 m - -5 u -8 - m * ins and source a transition current when they are being externally driven from to The transition current reaches its maximum value when VIN is approximately V * RST pin has an internal pull-down resistor * E SEN are in the external access memory mode * XT is a CMOS input and RST is a Schmitt trigger input C CHRCTERISTICS The C specifications are a function of the particular process used to manufacture the part the ratings of the I/O buffers the capacitive load and the internal routing capacitance Most of the specifications can be expressed in terms of multiple input clock periods (TC) and actual parts will usually experience less than a ± ns variation The numbers below represent the performance expected from a 6micron CMOS process when using and m output buffers ublication Release ate: ecember Revision

14 reliminary W78E5B Clock Input Waveform XT TCH TC F O TC RMETER SYMBO MIN TY MX UNIT NOTES Operating Speed FO - MHz Clock eriod TC ns Clock High TCH - - ns Clock ow TC - - ns Notes: The clock may be stopped indefinitely in either state The TC specification is used as a reference in other specifications There are no duty cycle requirements on the XT input rogram Fetch Cycle RMETER SYMBO MIN TY MX UNIT NOTES ddress Valid to E ow TS TC ns ddress Hold from E ow TH TC ns E ow to SEN ow T TC ns SEN ow to ata Valid T - - TC ns ata Hold after SEN High TH - TC ns ata Float after SEN High TZ - TC ns E ulse Width TW TC - TC - ns SEN ulse Width TSW TC - TC - ns Notes: 7 7 remain stable throughout entire memory cycle Memory access time is TC ata have been latched internally prior to SEN going high " " (due to buffer driving delay and wire loading) is ns ata Read Cycle RMETER SYMBO MIN TY MX UNIT NOTES E ow to R ow TR TC - - TC + ns R ow to ata Valid T - - TC ns ata Hold from R High TH - TC ns ata Float from R High TZ - TC ns R ulse Width TR 6 TC - 6 TC - ns Notes: ata memory access time is 8 TC " " (due to buffer driving delay and wire loading) is ns - -

15 reliminary W78E5B ata Write Cycle RMETER SYMBO MIN TY MX UNIT E ow to WR ow TW TC - - TC + ns ata Valid to WR ow T TC ns ata Hold from WR High TW TC ns WR ulse Width TWR 6 TC - 6 TC - ns Note: " " (due to buffer driving delay and wire loading) is ns ort ccess Cycle RMETER SYMBO MIN TY MX UNIT ort Input Setup to E ow TS TC - - ns ort Input Hold from E ow TH - - ns ort Output to E T TC - - ns Note: orts are read during S5 and output data becomes available at the end of S6 The timing data are referenced to E since it provides a convenient reference rogram Operation RMETER SYMBO MIN TY MX UNIT V Setup Time TVS - - µs ata Setup Time TS - - µs ata Hold Time TH - - µs ddress Setup Time TS - - µs ddress Hold Time TH - - µs CE rogram ulse Width for rogram Operation TW 9 µs OECTR Setup Time TOCS - - µs OECTR Hold Time TOCH - - µs OE Setup Time TOES - - µs OE High to Output Float TF - ns ata Valid from OE TOEV ns Note: Flash data can be accessed only in flash mode The RST pin must pull in VIH status the E pin must pull in status and the SEN pin must pull in VIH status ublication Release ate: ecember Revision

16 reliminary W78E5B TIMING WVEFORMS rogram Fetch Cycle XT S S S S S5 S6 S S S S S5 S6 E T T W SEN T S T SW ORT T H T TH T Z ORT Code -7 ata -7 Code -7 ata -7 ata Read Cycle XT S S5 S6 S S S S S5 S6 S S S E SEN ORT 8-5 ORT R -7 T R T T T H T Z T R - 6 -

17 reliminary W78E5B Timing Waveforms continued ata Write Cycle S S5 S6 S S S S S5 S6 S S S XT E SEN ORT 8-5 ORT -7 T OUT WR T T W T W T WR ort ccess Cycle S5 S6 S XT E TS TH T ORT T OUT INUT SME ublication Release ate: ecember Revision

18 reliminary W78E5B Timing Waveforms continued rogram Operation rogram rogram Verify Read Verify (5 ) V IH V I ddress Stable ddress Valid 6 (CE) V IH V I T S T W (OECTR) 7 (OE) (7 ) Vpp V T IH H TOCS V I TOCH V IH T OES V I T T F H V IH V ata In OUT ata Out I T S Vcp T OEV V IH T VS - 8 -

19 reliminary W78E5B TYIC ICTION CIRCUITS Expanded External rogram Memory and Crystal V V u 8 K C CRYST C R E XT XT RST INT INT T T R 7 WR 6 SEN 9 E TX RX Q Q Q Q 9 7 Q Q Q Q GN 8 OC 9 9 G GN CE OE 75 O O O O 5 O 6 O5 7 O6 8 O W78E5B Figure CRYST C C R 6 MHz - MHz MHz 68K MHz 5 5 7K bove table shows the reference values for crystal applications (full gain) Note: C C R components refer to Figure ublication Release ate: ecember Revision

20 reliminary W78E5B Typical pplication Circuits continued Expanded External ata Memory and Oscillator V 8 K V u OSCITOR E XT XT RST INT INT T T R 7 WR 6 9 SEN E TX RX Q Q 5 7 Q Q Q Q5 Q6 Q GN OC G GN CE OE WR W78E5B Figure B - -

21 reliminary W78E5B CKGE IMENSIONS -pin I E S B e B Base lane Seating lane a E e c Symbol B B c E E e a e S imension in inch imension in mm Min Nom Max Min Nom Max Notes: imension Max & S include mold flash or tie bar burrs imension E does not include interlead flash imension & E include mold mismatch and are determined at the mold parting line imension B does not include dambar protrusion/intrusion 5 Controlling dimension: Inches 6 General appearance spec should be based on final visual inspection spec pin CC H θ e Seating lane G 8 b b 9 E H E 9 y c G E Symbol b b c E e G G E H HE y imension in inch imension in mm Min Nom Max Min Nom Max BSC Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Inches General appearance spec should be based on final visual inspection spec BSC ublication Release ate: ecember Revision

22 reliminary W78E5B ackage imensions continued -pin QF Seating lane H e b See etail F y E HE c θ etail F Symbol b c E e H H E y θ Notes: imension in inch imension in mm Min Nom Max Min Nom Max imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec should be based on final visual inspection spec pin TQF Seating lane H e See etail F b y E H E c θ etail F Symbol b c E e H H E y θ Notes: imension in inch imension in mm Min Nom Max Min Nom Max imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec should be based on final visual inspection spec

23 reliminary W78E5B Headquarters Winbond Electronics (HK) td No Creation Rd III Rm 8 World Trade Square Tower II Science-Based Industrial ark Hoi Bun Rd Kwun Tong Hsinchu Taiwan Kowloon Hong Kong TE: TE: FX: FX: Voice & Fax-on-demand: Taipei Office F No 5 Sec Min-Sheng East Rd Taipei Taiwan TE: FX: Winbond Electronics North merica Corp Winbond Memory ab Winbond Microelectronics Corp Winbond Systems ab 77 N First Street San Jose C 95 US TE: FX: Note: ll data and specifications are subject to change without notice ublication Release ate: ecember Revision