W78E52B 8-BIT MICROCONTROLLER GENERAL DESCRIPTION FEATURES

Transcription

1 W78E5B 8-BI MICROCONROLLER GENERL ESCRIION he W78E5B is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption he instruction set for the W78E5B is fully compatible with the standard 85 he W78E5B contains an 8K bytes Flash EROM; a 56 bytes RM; four 8-bit bi-directional and bitaddressable I/O ports; an additional -bit I/O port ; three 6-bit timer/counters; a hardware watchdog timer and a serial port hese peripherals are supported by eight sources two-level interrupt capability o facilitate programming and verification the Flash EROM inside the W78E5B allows the program memory to be programmed and read electronically Once the code is confirmed the user can protect the code for security he W78E5B microcontroller has two power reduction modes idle mode and power-down mode both of which are software selectable he idle mode turns off the processor clock but allows for continued peripheral operation he power-down mode stops the crystal oscillator for minimum power consumption he external clock can be stopped at any time and in any state without affecting the processor FEURES Fully static design 8-bit CMOS microcontroller Wide supply voltage of 5V to 55V 56 bytes of on-chip scratchpad RM 8 KB On-chip Flash EROM 6 KB program memory address space 6 KB data memory address space Four 8-bit bi-directional ports One extra -bit bit-addressable I/O port additional IN / IN (available on -pin LCC/QF package) hree 6-bit timer/counters One full duplex serial port(ur) Watchdog imer Eight sources two-level interrupt capability EMI reduction mode Built-in power management Code protection mechanism ackages: I : W78E5B-/ LCC : W78E5B-/ QF : W78E5BF-/ ublication Release ate: ecember - - Revision

2 W78E5B IN CONFIGURIONS -in I (W78E5B) EX RS RX X IN IN 5 WR 6 R 7 XL XL VSS V E LE SEN in LCC (W78E5B) E X / I N V -in QF (W78E5BF) E X / I N V RS RX IN X IN IN E LE SEN RS RX IN X IN IN E LE SEN / W R 7 / R X L X L V S S / W R 7 / R X L X L V S S

3 W78E5B IN ESCRIION SYMBOL E ESCRIIONS EXERNL CCESS ENBLE: his pin forces the processor to execute out of external ROM It should be kept high to access internal ROM he ROM address and data will not be presented on the bus if E pin is high and the program counter is within on-chip ROM area SEN ROGRM SORE ENBLE: SEN enables the external ROM data onto the ort address/ data bus during fetch and MOVC operations When internal ROM access is performed no SEN strobe signal outputs from this pin LE RS XL XL VSS V RESS LCH ENBLE: LE is used to enable the address latch that separates the address from the data on ort RESE: high on this pin for two machine cycles while the oscillator is running resets the device CRYSL: his is the crystal oscillator input his pin may be driven by an external clock CRYSL: his is the crystal oscillator output It is the inversion of XL GROUN: Ground potential OWER SULY: Supply voltage for operation OR : ort is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory he ort is also an open-drain port and external pull-ups need to be connected while in programming OR : ort is a bi-directional I/O port with internal pull-ups he bits have alternate functions which are described below: (): imer/counter external count input EX(): imer/counter Reload/Capture control OR : ort is a bi-directional I/O port with internal pull-ups his port also provides the upper address bits for accesses to external memory OR : ort is a bi-directional I/O port with internal pull-ups ll bits have alternate functions which are described below: RX() : Serial ort receiver input X() : Serial ort transmitter output IN () : External Interrupt IN() : External Interrupt () : imer External Input (5) : imer External Input WR (6) : External ata Memory Write Strobe R (7) : External ata Memory Read Strobe OR : nother bit-addressable bidirectional I/O port and are alternative function pins It can be used as general I/O port or external interrupt input sources (IN /IN ) ublication Release ate: ecember - - Revision

4 W78E5B BLOCK IGRM ~ 7 ort ort Latch IN IN Interrupt imer imer imer SW CC LU B Stack ointer ort Latch R emp Reg C ort ~ 7 UR Incrementor ddr Reg ~ 7 ~ ort ort ort Latch ort Latch Instruction ecoder & Sequencer Bus & Clock Controller SFR RM ddress 56 bytes RM & SFR ROM Watchdog imer ort Latch ort ~ 7 Oscillator Reset Block ower control XL XL LE SEN RS Vcc Vss FUNCIONL ESCRIION he W78E5B architecture consists of a core controller surrounded by various registers five general purpose I/O ports 56 bytes of RM three timer/counters and a serial port he processor supports different opcodes and references both a 6K program address space and a 6K data storage space imers and imers and each consist of two 8-bit data registers hese are called L and H for imer L and H for imer and L and H for imer he CON and MO registers provide control functions for timers and he CON register provides control functions for imer RCH and RCL are used as reload/capture registers for imer - -

5 W78E5B he operations of imer and imer are the same as in the W78C5 imer is a special feature of the W78E5B: it is a 6-bit timer/counter that is configured and controlled by the CON register Like imers and imer can operate as either an external event counter or as an internal timer depending on the setting of bit C/ in CON imer has three operating modes: capture autoreload and baud rate generator he clock speed at capture or auto-reload mode is the same as that of imers and New efined eripheral In order to be more suitable for I/O an extra -bit bit-addressable port and two external interrupt IN IN has been added to either the LCC or QF pin package nd description follows: IN / IN wo additional external interrupts IN and IN whose functions are similar to those of external interrupt and in the standard 8C5 he functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register he XICON register is bit-addressable but is not a standard register in the standard 8C5 Its address is at CH o set/clear bits in the XICON register one can use the "SEB (/CLR) bit" instruction For example "SEB CH" sets the EX bit of XICON XICON - external interrupt control (CH) X EX IE I X EX IE I X: External interrupt priority high if set EX: External interrupt enable if set IE: If I = IE is set/cleared automatically by hardware when interrupt is detected/serviced I: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software X: External interrupt priority high if set EX: External interrupt enable if set IE: If I = IE is set/cleared automatically by hardware when interrupt is detected/serviced I: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INERRU SOURCE VECOR RESS OLLING SEQUENCE WIHIN RIORIY LEVEL ENBLE REQUIRE SEINGS INERRU YE EGE/LEVEL External Interrupt H (highest) IE CON imer/counter BH IE - External Interrupt H IE CON imer/counter BH IE - Serial ort H IE - imer/counter BH 5 IE5 - External Interrupt H 6 XICON XICON External Interrupt BH 7 (lowest) XICON6 XICON ublication Release ate: ecember Revision

6 W78E5B OR nother bit-addressable port is also available and only bits (<:>) can be used his port address is located at 8H with the same function as that of port except the and are alternative function pins It can be used as general I/O pins or external interrupt input sources (IN IN ) Example: REG 8H MOV #H ; Output data "" through MOV ; Read status to ccumulator ORL #B ; Set bit NL #B ; Clear bit Reduce EMI Emission Because of on-chip ROM when a program is running in internal ROM space the LE will be unused he transition of LE will cause noise so it can be turned off to reduce the EMI emission if it is useless urning off the LE signal transition only requires setting the bit of the UXR SFR which is located at 8Eh When LE is turned off it will be reactivated when the program accesses external ROM/RM data or jumps to execute an external ROM code he LE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space he O bit in the UXR register when set disables the LE output In order to reduce EMI emission from oscillation circuitry W78E5B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register Once B7 is set to a half of gain will be decreased Care must be taken if user attempts to diminish the gain of oscillator amplifier reducing a half of gain may affect the external crystal operating improperly at high frequency above MHz he value of R and CC may need some adjustment while running at lower gain ***UXR - uxiliary register (8EH) O O: urn off LE output ower-off Flag ***CON - ower control (87H) OF GF GF IL OF: ower off flag Bit is set by hardware when power on reset It can be cleared by software to determine chip reset is a warm boot or cold boot GF GF: hese two bits are general-purpose flag bits for the user : ower down mode bit Set it to enter power down mode IL: Idle mode bit Set it to enter idle mode - 6 -

7 W78E5B he power-off flag is located at CON his bit is set when V has been applied to the part It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software Watchdog imer he Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor a time-base generator or an event timer It is basically a set of dividers that divide the system clock he divider output is selectable and determines the time-out interval When the time-out occurs a system reset can also be caused if it is enabled he main use of the Watchdog timer is as a system monitor his is important in real-time control applications In case of power glitches or electromagnetic interference the processor may begin to execute errant code If this is left unchecked the entire system may crash he watchdog time-out selection will result in different time-out values depending on the clock speed he Watchdog timer will de disabled on reset In general software should restart the Watchdog timer to put it into a known state he control bits that support the Watchdog timer are discussed below Watchdog imer Control Register Bit: ENW CLRW WIL - - S S S Mnemonic: WC ddress: 8FH ENW : Enable watch-dog if set CLRW : Clear watch-dog timer and prescaler if set his flag will be cleared automatically WIL : If this bit is set watch-dog is enabled under ILE mode If cleared watch-dog is disabled under ILE mode efault is cleared S S S: Watch-dog prescaler timer select rescaler is selected when set S~ as follows: S S S RESCLER SELEC he time-out period is obtained using the following equation: RESCLER ms OSC ublication Release ate: ecember Revision

8 W78E5B Before Watchdog time-out occurs the program must clear the -bit timer by writing to WC6 (CLRW) fter is written to this bit the -bit timer prescaler and this bit will be reset on the next instruction cycle he Watchdog timer is cleared on reset WIL ENW ILE EXERNL RESE OSC / RESCLER -BI IMER CLER INERNL RESE Watchdog imer Block iagram CLRW ypical Watch-og time-out period when OSC = MHz S S S WCHOG IME-OU ERIO 966 ms 9 ms 786 ms 578 ms 57 ms 69 ms 5 S 5 S Clock he W78E5B is designed to be used with either a crystal oscillator or an external clock Internally the clock is divided by two before it is used his makes the W78E5B relatively insensitive to duty cycle variations in the clock he W78E5B incorporates a built-in crystal oscillator o make the oscillator work a crystal must be connected across pins XL and XL In addition a load capacitor must be connected from each pin to ground n external clock source should be connected to pin XL in XL should be left unconnected he XL input is a CMOS-type input as required by the crystal oscillator ower Management Idle Mode he idle mode is entered by setting the IL bit in the CON register In the idle mode the internal clock to the processor is stopped he peripherals and the interrupt logic continue to be clocked he processor will exit idle mode when either an interrupt or a reset occurs - 8 -

9 W78E5B ower-down Mode When the bit of the CON register is set the processor enters the power-down mode In this mode all of the clocks are stopped including the oscillator he only way to exit power-down mode is by a reset Reset he external RESE signal is sampled at S5 o take effect it must be held high for at least two machine cycles while the oscillator is running n internal trigger circuit in the reset line is used to deglitch the reset line when the W78E5B is used with an external RC network he reset logic also has a special glitch removal circuit that ignores glitches on the reset line uring reset the ports are initialized to FFH the stack pointer to 7H CON (with the exception of bit ) to H and all of the other SFR registers except SBUF to H SBUF is not reset ON-CHI FLSH EROM CHRCERISICS he W78E5B has several modes to program the on-chip ROM ll these operations are configured by the pins RS LE SEN 9CRL() CRL() CRL() OECRL() CE (6) OE (7) () and V(E ) Moreover the 5 (7 7 ) and the 7 (7 ) serve as the address and data bus respectively for these operations Read Operation his operation is supported for customer to read their code and the Security bits he data will not be valid if the Lock bit is programmed to low Output isable Condition When the OE is set to high no data output appears on the 7 rogram Operation his operation is used to program the data to Flash EROM and the security bits rogram operation is done when the Vpp is reach to Vcp (5V) level CE set to low and OE set to high rogram Verify Operation ll the programming data must be checked after program operations his operation should be performed after each byte is programmed; it will ensure a substantial program margin Erase Operation n erase operation is the only way to change data from to his operation will erase all the ROM cells and the security bits from to his erase operation is done when the Vpp is reach to Vep level CE set to low and OE set to high Erase Verify Operation fter an erase operation all of the bytes in the chip must be verified to check whether they have been successfully erased to or not he erase verify operation automatically ensures a substantial erase margin his operation will be done after the erase operation if Vpp = Vep(5V) CE is high and OE is low ublication Release ate: ecember Revision

10 W78E5B rogram/erase Inhibit Operation his operation allows parallel erasing or programming of multiple chips with different data When 6( CE ) = VIH 7( OE ) = VIH erasing or programming of non-targeted chips is inhibited So except for the 6 and 7 pins the individual chips may have common inputs OERIONS (9 CRL) ( CRL) ( CRL) (OE CRL) 6 ( CE ) 7 ( OE ) E (V) (5 ) (7 ) Read ddress ata Out Output isable X Hi-Z rogram VC ddress ata In rogram Verify VC ddress ata Erase VE : others: X ata In FFH Erase Verify VE ddress ata rogram/erase Inhibit X VC/ VE Notes: ll these operations happen in RS = VIH LE = and SEN = VIH VC = 5V VE = 5V VIH = V = Vss he program verify operation follows behind the program operation his erase operation will erase all the on-chip ROM cells and the Security bits 5 he erase verify operation follows behind the erase operation X X SECURIY BIS uring the on-chip Flash EROM operation mode the ROM can be programmed and verified repeatedly Until the code inside the ROM is confirmed OK the code can be protected he protection of ROM and those operations on it are described below he W78E5B has a Security Register which can not be accessed in normal mode hese registers can only be accessed from the Flash EROM operation mode hose bits of the Security Register can not be changed once they have been programmed from high to low hey can only be reset through erase-all operation he Security Register is addressed in the Flash EROM operation mode by address #FFFFh - -

11 W78E5B B7 Reserved B B B Security Bits B : Lock bit logic : active B : MOVC inhibit logic : the MOVC instruction in external memory cannot access the code in internal memory logic : no restriction B : Encryption logic : the encryption logic enable logic : the encryption logic disable B7 : Osillator Control logic : / gain logic : Full gain efault for all security bits Reserved bits must be kept in logic Special Setting Register 8KB On-chip ROM rogram Memory Reserved Security Register h FFFh FFFFh Lock bit his bit is used to protect the customer's program code in the W78E5B It may be set after the programmer finishes the programming and verifies sequence Once this bit is set to logic both the ROM data and Special Setting Register can not be accessed again MOVC Inhibit his bit is used to restrict the accessible region of the MOVC instruction It can prevent the MOVC instruction in external program memory from reading the internal program code When this bit is set to logic a MOVC instruction in external program memory space will be able to access code only in the external memory not in the internal memory MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory If this bit is logic there are no restrictions on the MOVC instruction Encryption his bit is used to enable/disable the encryption logic for code protection Once encryption feature is enabled the data presented on port will be encoded via encryption logic Only whole chip erase will reset this bit ublication Release ate: ecember - - Revision

12 W78E5B +5V +5V V V to 7 GM to 7 GM VIH 6 7 E/Vpp LE RS SEN VC VIH VIH VIH 6 7 E/Vpp LE RS SEN VC VIH VIH X'tal X'tal 8 to 5 X'tal X'tal 8 to 5 Vss Vss rogramming Configuration rogramming Verification BSOLUE MXIMUM RINGS RMEER SYMBOL MIN MX UNI C ower Supply V VSS - +7 V Input Voltage VIN VSS - V + V Operating emperature 7 C Storage emperature S C Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device C CHRCERISICS VCC VSS = 5V ±% = 5 C unless otherwise specified RMEER SYMBOL ES CONIIONS SECIFICION UNI MIN MX Operating Voltage V 5 55 V Operating Current I No load V = 55V - m Idle Current IILE Idle mode V = 55V - 6 m ower own Current IWN ower-down mode V = 55V Input Current IIN V = 55V VIN = V or V Logical -to- ransition IL V = 55V Current (*) Input Current IIN V = 55V RS (*) VIN = V - 5 µ -5 + µ VIN = V (*) µ - + µ - -

13 W78E5B C Characteristics continued RMEER SYMBOL ES CONIIONS SECIFICION UNI Input Leakage Current E Output Low Voltage ILK V = 55V V < VIN < V VOL V = 5V IOL = + m Output Low Voltage VOL V = 5V LE IN (*) IOL = + m Output High Voltage VOH V = 5V IOH = - µ Output High Voltage VOH V = 5V LE SEN (*) IOH = - µ Input Low Voltage (Except RS) MIN MX - + µ - 5 V - 5 V - V - V V = 5V 8 V Input Low Voltage V = 5V 8 V RS (*) Input Low Voltage V = 5V 8 V XL (*) Input High Voltage (Except RS) Sink Current VIH V = 5V V + V ISK V = 5V VS = 5V m Input High Voltage VIH V = 5V 67 V V + V RS (*) Input High Voltage VIH V = 5V 67 V V + V XL (*) Sink Current LE SEN (*) Source Current Source Current LE SEN (*) ISK V = 5V VS = 5V ISR V = 5V VS = V ISR V = 5V V = V 8 6 m - -5 u -8 - m Notes: * ins and source a transition current when they are being externally driven from to he transition current reaches its maximum value when VIN is approximately V * RS pin has an internal pull-down resistor * LE SEN are in the external access memory mode * XL is a CMOS input and RS is a Schmitt trigger input ublication Release ate: ecember - - Revision

14 W78E5B C CHRCERISICS he C specifications are a function of the particular process used to manufacture the part the ratings of the I/O buffers the capacitive load and the internal routing capacitance Most of the specifications can be expressed in terms of multiple input clock periods (C) and actual parts will usually experience less than a ± ns variation he numbers below represent the performance expected from a 6micron CMOS process when using and m output buffers Clock Input Waveform XL CH CL F O C RMEER SYMBOL MIN Y MX UNI NOES Operating Speed FO - MHz Clock eriod C ns Clock High CH - - ns Clock Low CL - - ns Notes: he clock may be stopped indefinitely in either state he C specification is used as a reference in other specifications here are no duty cycle requirements on the XL input rogram Fetch Cycle RMEER SYMBOL MIN Y MX UNI NOES ddress Valid to LE Low S C ns ddress Hold from LE Low H C ns LE Low to SEN Low L C ns RES Low to ata Valid - - C ns ata Hold after SEN High H - C ns ata Float after SEN High Z - C ns LE ulse Width LW C - C - ns SEN ulse Width SW C - C - ns Notes: 7 7 remain stable throughout entire memory cycle Memory access time is C ata have been latched internally prior to SEN going high " " (due to buffer driving delay and wire loading) is ns - -

15 W78E5B ata Read Cycle RMEER SYMBOL MIN Y MX UNI NOES LE Low to R Low R C - - C + ns R Low to ata Valid - - C ns ata Hold from R High H - C ns ata Float from R High Z - C ns R ulse Width R 6 C - 6 C - ns Notes: ata memory access time is 8 C " " (due to buffer driving delay and wire loading) is ns ata Write Cycle RMEER SYMBOL MIN Y MX UNI LE Low to WR Low W C - - C + ns ata Valid to WR Low C ns ata Hold from WR High W C ns WR ulse Width WR 6 C - 6 C - ns Note: " " (due to buffer driving delay and wire loading) is ns ort ccess Cycle RMEER SYMBOL MIN Y MX UNI ort Input Setup to LE Low S C - - ns ort Input Hold from LE Low H - - ns ort Output to LE C - - ns Note: orts are read during S5 and output data becomes available at the end of S6 he timing data are referenced to LE since it provides a convenient reference rogram Operation RMEER SYMBOL MIN Y MX UNI V Setup ime VS - - µs ata Setup ime S - - µs ata Hold ime H - - µs ddress Setup ime S - - µs ddress Hold ime H - - µs ublication Release ate: ecember Revision

16 W78E5B rogram Operation continued RMEER SYMBOL MIN Y MX UNI CE rogram ulse Width for rogram Operation W 9 µs OECRL Setup ime OCS - - µs OECRL Hold ime OCH - - µs OE Setup ime OES - - µs OE High to Output Float F - ns ata Valid from OE OEV ns Note: Flash data can be accessed only in flash mode he RS pin must pull in VIH status the LE pin must pull in status and the SEN pin must pull in VIH status IMING WVEFORMS rogram Fetch Cycle XL S S S S S5 S6 S S S S S5 S6 LE L LW SEN OR S SW H H Z OR Code -7 ata -7 Code -7 ata

17 W78E5B iming Waveforms continued ata Read Cycle XL S S5 S6 S S S S S5 S6 S S S LE SEN OR 8-5 OR R -7 R H Z R ata Write Cycle S S5 S6 S S S S S5 S6 S S S XL LE SEN OR 8-5 OR WR -7 OU W W WR ublication Release ate: ecember Revision

18 W78E5B iming Waveforms continued ort ccess Cycle S5 S6 S XL LE S H OR OU INU SMLE rogram Operation rogram rogram Verify Read Verify (5 ) V IH V IL ddress Stable ddress Valid 6 (CE) V IH V IL S W (OECRL) 7 (OE) (7 ) Vpp V IH H OCS V IL OCH V IH OES V IL F H V IH V ata In OU ata Out IL S Vcp OEV V IH VS - 8 -

19 W78E5B YICL LICION CIRCUIS Expanded External rogram Memory and Crystal V V u 8 K C CRYSL C R E XL XL RS IN IN R 7 WR 6 SEN 9 LE X RX Q Q Q Q 9 7 Q Q Q Q GN 8 OC 9 9 G GN CE OE 75 O O O O 5 O 6 O5 7 O6 8 O W78E5B Figure CRYSL C C R 6 MHz - MHz MHz 68K MHz 5 5 7K bove table shows the reference values for crystal applications (full gain) Note: C C R components refer to Figure ublication Release ate: ecember Revision

20 W78E5B ypical pplication Circuits continued Expanded External ata Memory and Oscillator V 8 K V u OSCILLOR E XL XL RS IN IN R 7 WR 6 SEN 9 LE X RX Q Q 5 7 Q 6 8 Q 9 Q 5 5 Q Q Q7 9 GN OC G GN CE OE WR W78E5B Figure B - -

21 W78E5B CKGE IMENSIONS -pin I Symbol B B c E imension in inch imension in mm Min Nom MaxMax Min Nom E L S B B e Base lane Seating lane a E e c E e L a 5 5 e S 9 86 Notes: imension Max & S include mold flash or tie bar burrs imension E does not include interlead flash imension & E include mold mismatch and are determined at the mold parting line imension B does not include dambar protrusion/intrusion 5 Controlling dimension: Inches 6 General appearance spec should be based on final visual inspection spec -pin LCC H L θ e Seating lane G 8 b b 9 E H E 9 y c GE Symbol b b c E e G G E H imension in inch imension in mm Min Nom MaxMax Min Nom 5 BSC H E L y Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Inches General appearance spec should be based on final visual inspection spec BSC ublication Release ate: ecember - - Revision