W78E58 8-BIT MICROCONTROLLER GENERAL DESCRIPTION FEATURES

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Terence Oliver
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1 GENER ESCRITION 8-BIT MICROCONTROER The W78E58 is an 8-bit microcontroller that is functionally compatible with the W78C58 except that the mask ROM is replaced by a flash EEROM with a size of KB To facilitate programming and verification the flash EEROM inside the W78E58 allows the program memory to be programmed and read electronically Once the code is confirmed the user can protect the code for security The W78E58 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market It is functionally compatible with the industry-standard 8C5 microcontroller series except that one extra -bit bit-addressable I/O port(ort ) and two additional external interrupts ( INT INT ) The W78E58 contains four 8-bit bi-directional and bit-addressable I/O ports three 6-bit timer/counters and a serial port These peripherals are supported by a eight-source two-level interrupt capability There are 56 bytes of RM and an KB flash EEROM for application programs The W78E58 microcontroller has two power reduction modes idle mode and power-down mode both of which are software selectable The idle mode turns off the processor clock but allows for continued peripheral operation The power-down mode stops the crystal oscillator for minimum power consumption The external clock can be stopped at any time and in any state without affecting the processor FETURES 8-bit CMOS microcontroller Fully static design ow standby current at full supply voltage C- MHz operation 56 bytes of on-chip scratchpad RM KB electrically erasable/programmable EROM 6 KB program memory address space 6 KB data memory address space Four 8-bit bidirectional ports One extra -bit bit-addressable I/O port additional INT / INT (available on -pin CC/QF package) Three 6-bit timer/counters One full duplex serial port Boolean processor Eight-source two-level interrupt capability Built-in power management Code protection mechanism ackages: I : W78E58-6// CC : W78E58-6// QF : W78E58F-6// TQF : W78E58M-6// ublication Release ate: November Revision

2 IN CONFIGURTIONS -in I (W78E58) T TEX RX TX INT INT T T 5 WR 6 R 7 XT XT VSS VCC E E SEN in CC (W78E58) -in QF/TQF (W78E58F/W78E58M) T E X T / I N T V C C T E X T / I N T V C C RX INT TX INT INT T T E E SEN RX INT TX INT INT T T E E SEN / W R 7 / R X T X T V S S / W R 7 / R X T X T V S S

3 IN ESCRITION The W78E58 has two operating modes normal and flash In normal mode the W78E58 corresponds to the W78C58 In flash mode the user (the maker of the flash EEROM writer) can access the flash EEROM 7- ort Bits 7- MOE Normal Flash ESCRITION ort Bits through 7 ort is a bidirectional I/O port This port also provides a multiplexed low order address/data bus during accesses to external memory This port provides the data bus during access to the flash EEROM 7- ort Bits 7- MOE Normal Flash ESCRITION ort Bits through 7 ort is a bidirectional I/O port with internal pull-ups ins and also serve as T (Timer external input) and TEX (Timer capture/reload trigger) respectively This port provides the low-order address bus during access to the flash EEROM 7- ort Bits 7- MOE Normal Flash ESCRITION ort Bits through 7 ort is a bidirectional I/O port with internal pull-ups This port also provides the upper address bits for accesses to external memory This port provides the high-order address bus during access to the flash EEROM 7- ort Bits 7- MOE Normal Flash ESCRITION ort Bits through 7 ort is a bidirectional I/O port with internal pull-ups ll bits have alternate functions and 7 6 are the flash mode configuration pins Input and 7 6 are configured to select or execute the flash operations For details see Flash Operations - ort Bits - (available on -pin CC/QF package) MOE Normal ESCRITION nother bit-addressable bidirectional I/O port and are alternative function pins It can be used as general I/O pins or external interrupt input sources (INT / INT ) ublication Release ate: November Revision

4 Flash No function in this mode E/V MOE Normal Flash E External ccess Input active low ESCRITION This pin forces the processor to execute a program from the external ROM When the internal flash EEROM is accessed as in the W78C58 this pin should be kept high V rogram ower supply pin Input This pin accepts the high voltage (V) needed for programming the flash EEROM MOE Normal Flash Reset Input active high ESCRITION This pin resets the processor It must be kept high for at least two machine cycles in order to be recognized by the processor Flash mode configuration pin Input active high is used to configure the flash operations For details see Flash Operations E MOE Normal Flash ESCRITION E ddress atch Enable Output active high E is used to enable the address latch that separates the address from the data on ort E runs at /6th of the oscillator frequency single E pulse is skipped during external data memory accesses E goes to a high impedance state with a weak pull-up during reset state Flash mode configuration pin Input active low E is used to configure the flash operations For details see Flash Operations SEN MOE Normal Flash ESCRITION SEN rogram Store Enable Output active low This pin enables the external ROM onto the ort address/data bus during fetch and MOVC operations SEN goes to a high impedance state with a weak pull-up during reset state Flash mode configuration pin Input active high SEN is used to configure the flash operations For details see Flash Operations XT MOE ESCRITION - -

5 Normal Flash XT MOE Normal Flash Crystal This is the crystal oscillator input This pin may be driven by an external clock Connect to VSS ESCRITION Crystal This is the crystal oscillator output It is the inversion of XT No function in this mode VSS VCC ower Supplies These are the chip ground and positive supplies ublication Release ate: November Revision

6 BOCK IGRM ~ 7 ort ort atch INT INT Interrupt URT Timer Timer Timer SW CC T U T B Stack ointer ort atch TR Temp Reg C Incrementor ort ~ 7 ddr Reg ~ 7 ~ ort ort ort atch ort atch Instruction ecoder & Sequencer Bus & Clock Controller SFR RM ddress 56 bytes RM & SFR ort atch ort ~ 7 Oscillator Reset Block ower Control XT XT E SEN Vcc Vss - 6 -

7 FUNCTION ESCRITION The W78E58 architecture consists of a core controller surrounded by various registers five general purpose I/O ports 56 bytes of RM three timer/counters and a serial port The processor supports different opcodes and references both a 6K program address space and a 6K data storage space Timers and Timers and each consist of two 8-bit data registers These are called T and TH for Timer T and TH for Timer and T and TH for Timer The TCON and TMO registers provide control functions for timers and The TCON register provides control functions for Timer RCH and RC are used as reload/capture registers for Timer The operations of Timer and Timer are the same as in the W78C5 Timer is a special feature of the W78E58: it is a 6-bit timer/counter that is configured and controlled by the TCON register ike Timers and Timer can operate as either an external event counter or as an internal timer depending on the setting of bit C/T in TCON Timer has three operating modes: capture autoreload and baud rate generator The clock speed at capture or auto-reload mode is the same as that of Timers and Clock The W78E58 is designed to be used with either a crystal oscillator or an external clock Internally the clock is divided by two before it is used This makes the W78E58 relatively insensitive to duty cycle variations in the clock Crystal Oscillator The W78E58 incorporates a built-in crystal oscillator To make the oscillator work a crystal must be connected across pins XT and XT In addition a load capacitor must be connected from each pin to ground and a resistor must also be connected from XT to XT to provide a C bias when the crystal frequency is above MHz External Clock n external clock should be connected to pin XT in XT should be left unconnected The XT input is a CMOS-type input as required by the crystal oscillator s a result the external clock signal should have an input one level of greater than 5 volts ower Management Idle Mode The idle mode is entered by setting the I bit in the CON register In the idle mode the internal clock to the processor is stopped The peripherals and the interrupt logic continue to be clocked The processor will exit idle mode when either an interrupt or a reset occurs ower-down Mode When the bit of the CON register is set the processor enters the power-down mode In this mode all of the clocks are stopped including the oscillator The only way to exit power-down mode is by a reset ublication Release ate: November Revision

8 Reset The external RESET signal is sampled at S5 To take effect it must be held high for at least two machine cycles while the oscillator is running n internal trigger circuit in the reset line is used to deglitch the reset line when the W78E58 is used with an external RC network The reset logic also has a special glitch removal circuit that ignores glitches on the reset line uring reset the ports are initialized to FFH the stack pointer to 7H CON (with the exception of bit ) to H and all of the other SFR registers except SBUF to H SBUF is not reset Option Setting Users write programs into the W78E58 by using the Winbond proprietary writer The writer programs the data into an internal KB region and reads the data back for verification fter confirming that the program is correct the user can lock the data so that they can no longer be read ock Bit This bit is used to protect the customer data in the W78E58 It may be turned on after the programmer finishes the programming and verify sequence Once this bit is set to logic no flash data can be accessed again MOVC Execute This bit is used to restrict the region accessible to the MOVC instruction It can prevent the program from being downloaded using this instruction if the program needs to jump outside to get data When this bit is set to logic a MOVC instruction in external program memory space will be able to access code in the external memory but it will not be able to access code in the internal memory MOVC instruction in internal program memory space will always be able to access code in both internal and external memory If this bit is logic there are no restrictions on the MOVC instruction New efined eripheral In order to be more suitable for I/O an extra -bit bit-addressable port and two external interrupt INT INT has been added to either the CC or QF pin package nd description follows: INT/INT Two additional external interrupts INT and INT whose functions are similar to those of external interrupt and in the standard 8C5 The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register The XICON register is bit-addressable but is not a standard register in the standard 8C5 Its address is at CH To set/clear bits in the XICON register one can use the "SETB (/CR) bit" instruction For example "SETB CH" sets the EX bit of XICON ***XICON - external interrupt control (CH) X EX IE IT X EX IE IT X: External interrupt priority high if set - 8 -

9 EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software X: External interrupt priority high if set EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INTERRUT SOURCE VECTOR RESS OING SEQUENCE WITHIN RIORITY EVE ENBE REQUIRE SETTINGS INTERRUT TYE EGE/EVE External Interrupt H (highest) IE TCON Timer/Counter BH IE - External Interrupt H IE TCON Timer/Counter BH IE - Serial ort H IE - Timer/Counter BH 5 IE5 - External Interrupt H 6 XICON XICON External Interrupt BH 7 (lowest) XICON6 XICON ORT nother bit-addressable port is also available and only bits (<:>) can be used This port address is located at 8H with the same function as that of port except the and are alternative function pins It can be used as general I/O pins or external interrupt input sources (INT / INT ) Example: REG 8H MOV #H ; Output data "" through MOV ; Read status to ccumulator SETB ; Set bit CR ; Clear bit Reduce EMI Emission Because of the large on-chip flash EEROM when a program is running in internal ROM space the E will be unused The transition of E will cause noise so it can be turned off to reduce the EMI ublication Release ate: November Revision

10 emission if it is useless Turning off the E signal transition only requires setting the bit of the UXR SFR which is located at 8Eh When E is turned off it will be reactivated when the program accesses external ROM/RM data or jumps to execute an external ROM code The E signal will turn off again after it has been completely accessed or the program returns to internal ROM code space The O bit in the UXR register when set disables the E output ***UXR - uxiliary register (8EH) O O: Turn off E output ower-off Flag ***CON - ower control (87H) SMO - - OF GF GF I SMO: ouble baud rate bit When set to a the baud rate is doubled when the serial port is being used in either modes OF: ower off flag Bit is set by hardware when power on reset It can be cleared by software to determine chip reset is a warm boot or cold boot GF GF: These two bits are general-purpose flag bits for the user : ower down mode bit Set it to enter power down mode I: Idle mode bit Set it to enter idle mode The power-off flag is located at CON This bit is set when V has been applied to the part It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software Flash Operations In normal operation the W78E58 is functionally compatible with the W78C58 In the flash operating mode the flash EEROM can be programmed and verified repeatedly Once the code inside the flash EEROM is confirmed the code can be protected The flash EEROM and the operations on it are described below ll of the operations are configured by the pins E SEN 9CTR () CTR () CTR () OECTR () CE (6) OE (7) () and V (E ) In these operations 5 to (7 to 7 to ) and 7 to (7 to ) serve as the address and data bus respectively Read Operation This operation enables customers to read their codes and the option bits The data will not be valid if the lock bit is programmed to low - -

11 rogram Operation This operation is used to program data to the flash EEROM and the option bits rogramming is initiated when V reaches VC (5V) level CE is set to low and OE is set to high rogram Verify Operation ll data must be checked after programming This operation should be performed after each byte is programmed and it will ensure a substantial program margin OERTION (9 CTR) ( CTR) ( CTR) (OE CTR) 6 ( CE ) 7 ( OE ) E (V) (5 TO ) (7 TO ) Read VI VI VI VI VI VI VIH ddress ata Out rogram VI VI VI VI VI VIH VC ddress ata In rogram Verify VI VI VI VI VIH VI VC ddress ata Out Notes: uring all of these operations = VIH E = VI and SEN = VIH VC = V VIH = V VI = Vss The program verify operation should follow the programming operaion NOTES BSOUTE MXIMUM RTINGS RMETER SYMBO MIN MX UNIT C ower Supply V VSS - +7 V Input Voltage VIN VSS - V + V Operating Temperature T 7 C Storage Temperature TST C Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability the device of +5V +5V V V to 7 GM T to 7 GM T V IH 6 7 E/Vpp E SEN V C V IH V IH V IH 6 7 E/Vpp E SEN V C V IH V IH X'tal X'tal 8 to 5 X'tal X'tal 8 to 5 Vss Vss rogramming Configuration rogramming Verification ublication Release ate: November Revision

12 C CHRCTERISTICS (V-VSS = 5V ±% T = 5 C Fosc = MHz unless otherwise specified) RMETER SYM SECIFICTION UNIT TEST CONITIONS MIN MX Operating Voltage V 5 55 V Operating Current I - m No load V = 55V Idle Current IIE - 6 m Idle mode V = 55V ower own Current IWN - 5 µ ower-down mode Input Current Input Current Input eakage Current E ogic to Transition Current Input ow Voltage E Input ow Voltage Input ow Voltage XT[*] Input High Voltage E Input High Voltage Input High Voltage XT [*] Output ow Voltage V = 55V IIN -5 + µ V = 55V VIN = V or V IIN - + µ V = 55V < VIN < V IK - + µ V = 55V V <VIN < V IT [*] -5 - µ V = 55V VIN =V VI 8 V V = 5V VI 8 V V = 5V VI 8 V V = 5V VIH V + V V = 55V VIH 5 V + V V = 55V VIH 5 V + V V = 55V VO - 5 V V = 5V IO = + m - -

13 C Characteristics continued RMETER SYM SECIFICTION UNIT TEST CONITIONS Output ow Voltage E SEN [*] Sink Current Sink Current E SEN Output High Voltage Output High Voltage E SEN [*] Source Current Source Current E SEN Notes: MIN MX VO - 5 V V = 5V IO = +m ISK m V = 5V Vs = 5V ISK m V = 5V Vs = 5V VOH - V V = 5V IOH = - µ VOH - V V = 5V IOH = - µ ISR - -5 µ V = 5V Vs = V ISR -8 - m V = 5V * pin is a Schmitt trigger input has internal pull-low resistors of about KΩ * E and /SEN are tested in the external access mode * XT is a CMOS input Vs = V *5 ins of can source a transition current when they are being externally driven from to The transition current reaches its maximum value when V IN approximates to V C CHRCTERISTICS The C specifications are a function of the particular process used to manufacture the part the ratings of the I/O buffers the capacitive load and the internal routing capacitance Most of the specifications can be expressed in terms of multiple input clock periods (TC) and actual parts will usually experience less than a ± ns variation The numbers below represent the performance expected from a 8 micron CMOS process when using and m output buffers Clock Input Waveform ublication Release ate: November Revision

14 XT TCH TC F O TC RMETER SYMBO MIN TY MX UNIT NOTES Operating Speed FO - MHz Clock eriod TC ns Clock High TCH - - ns Clock ow TC - - ns Notes: The clock may be stopped indefinitely in either state The TC specification is used as a reference in other specifications There are no duty cycle requirements on the XT input rogram Fetch Cycle RMETER SYMBO MIN TY MX UNIT NOTES ddress Valid to E ow TS TC ns ddress Hold from E ow TH TC ns E ow to SEN ow T TC ns SEN ow to ata Valid T - - TC ns ata Hold after SEN High TH - TC ns ata Float after SEN High TZ - TC ns E ulse Width TW TC - TC - ns SEN ulse Width TSW TC - TC - ns Notes: 7 7 remain stable throughout entire memory cycle Memory access time is TC ata have been latched internally prior to SEN going high " " (due to buffer driving delay and wire loading) is ns ata Read Cycle RMETER SYMBO MIN TY MX UNIT NOTE S E ow to R ow TR TC - - TC + ns R ow to ata Valid T - - TC ns - -

15 ata Hold from R High TH - TC ns ata Float from R High TZ - TC ns R ulse Width TR 6 TC - 6 TC - ns Notes: ata memory access time is 8 TC " " (due to buffer driving delay and wire loading) is ns ata Write Cycle RMETER SYMBO MIN TY MX UNIT E ow to WR ow TW TC - - TC + ns ata Valid to WR ow T TC ns ata Hold from WR High TW TC ns WR ulse Width TWR 6 TC - 6 TC - ns Note: " " (due to buffer driving delay and wire loading) is ns ort ccess Cycle RMETER SYMBO MIN TY MX UNIT ort Input Setup to E ow TS TC - - ns ort Input Hold from E ow TH - - ns ort Output to E T TC - - ns Note: orts are read during S5 and output data becomes available at the end of S6 The timing data are referenced to E since it provides a convenient reference rogram Operation RMETER SYMBO MIN TY MX UNIT V Setup Time TVS - - µs ata Setup Time TS - - µs ata Hold Time TH - - µs ddress Setup Time TS - - µs ddress Hold Time TH - - µs CE rogram ulse Width for rogram Operation CE rogram ulse Width for rogram Operation TW 95 5 µs TOW 95 5 µs OECTR Setup Time TOCS - - µs OECTR Hold Time TOCH - - µs ublication Release ate: November Revision

16 OE Setup Time TOES - - µs OE High to Output Float TF - ns ata Valid from OE TOEV ns Note: Flash data can be accessed only in flash mode The pin must pull in VIH status the E pin must pull in VI status and the SEN pin must pull in VIH status - 6 -

17 TIMING WVEFORMS rogram Fetch Cycle XT S S S S S5 S6 S S S S S5 S6 E T T W SEN ORT T S T SW T H T TH T Z ORT Code -7 ata -7 Code -7 ata -7 ata Read Cycle XT S S5 S6 S S S S S5 S6 S S S E SEN ORT 8-5 ORT R -7 T R T T T H T Z T R ublication Release ate: November Revision

18 Timing Waveforms continued ata Write Cycle S S5 S6 S S S S S5 S6 S S S XT E SEN ORT 8-5 ORT -7 T OUT WR T T W T W T WR ort ccess Cycle S5 S6 S XT E TS TH T ORT T OUT INUT SME - 8 -

19 Timing Waveforms continued rogram Operation rogram rogram Verify Read Verify (5 ) V IH ddress Stable ddress Valid 6 (CE) V IH T S T W (OECTR) 7 (OE) (7 ) Vpp V T IH H T OCS TOCH V IH T OES T T F H V IH V ata In OUT ata Out I T S Vcp T OEV V IH T VS ublication Release ate: November Revision

20 TYIC ICTION CIRCUITS Expanded External rogram Memory and Crystal V CC VCC u 8 K C CRYST C R E XT XT INT INT T T R 7 WR 6 SEN 9 E TX RX Q Q Q Q 9 7 Q Q Q Q GN 8 OC 9 9 G 7S GN CE OE 75 O O O O 5 O 6 O5 7 O6 8 O W78E58 Figure CRYST C C R 6 MHz - MHz MHz 68K MHz 5 5 7K bove table shows the reference values for crystal applications Note: C C R components refer to Figure - -

21 Typical pplication Circuits continued Expanded External ata Memory and Oscillator V CC VCC u 8 K OSCITOR E XT XT INT INT T T R 7 WR 6 SEN 9 E TX RX 8 9 Q Q 5 7 Q 6 8 Q 9 Q 5 5 Q Q Q7 9 GN OC G 7S GN CE OE WR W78E58 Figure B CKGE IMENSIONS -pin I Symbol B c E B imension in inches Min Nom Max Min Nom Max imension in mm E S B B e Base lane Seating lane a E e c E e a e S Notes: imension Max & S include mold flash or tie bar burrs imension E does not include interlead flash imension & E include mold mismatch and are determined at the mold parting line imension B does not include dambar protrusion/intrusion 5 Controlling dimension: Inches 6 General appearance spec should be based on final visual inspection spec ublication Release ate: November Revision

22 ackage imensions continued -pin CC H θ e Seating lane G 8 b b 9 E H E 9 y c G E Symbol b b c E e G G E H H E y imension in inches imension in mm Min Nom Max Min Nom Max BSC Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Inches General appearance spec should be based on final visual inspection spec BSC pin QF H E HE Symbol b c E e imension in inch imension in mm Min Nom Max Min Nom Max Seating lane e b See etail F y c θ etail F H H E y θ Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec should be based on final visual inspection spec

23 Timing Waveforms continued -pin TQF Seating lane H e See etail F b y E H E c θ etail F Symbol b c E e H H E y θ Notes: imension in inch imension in mm Min Nom Max Min Nom Max imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec should be based on final visual inspection spec Headquarters No Creation Rd III Science-Based Industrial ark Hsinchu Taiwan TE: FX: Voice & Fax-on-demand: Taipei Office F No 5 Sec Min-Sheng East Rd Taipei Taiwan TE: FX: Note: ll data and specifications are subject to change without notice Winbond Electronics (HK) td Rm 8 World Trade Square Tower II Hoi Bun Rd Kwun Tong Kowloon Hong Kong TE: FX: Winbond Electronics North merica Corp Winbond Memory ab Winbond Microelectronics Corp Winbond Systems ab 77 N First Street San Jose C 95 US TE: FX: ublication Release ate: November Revision

5.2.1 CRYSTAL OSCILLATOR EXTERNAL CLOCK POWER MANAGEMENT IDLE MODE POWER-DOWN MODE RESET...

5.2.1 CRYSTAL OSCILLATOR EXTERNAL CLOCK POWER MANAGEMENT IDLE MODE POWER-DOWN MODE RESET... W8CC/W8CC T SHEET Table of Contents- 8-BIT MICROCONTROER GENER ESCRITION FETURES IN CONFIGURTIONS 4 IN ESCRITION 4 5 FUNCTION ESCRITION 6 5 TIMERS N 6 5 COCK 6 5 CRYST OSCITOR 6 5 EXTERN COCK 6 5 OWER