Ensemble 6000 Series OpenVPX HCD6210 Dual QorIQ T4240 Processing Module

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1 Ensemble 6000 Series OpenVPX HCD6210 Dual QorIQ T4240 Processing Module Next-Generation High Density Processing With I/O in a Single VPX slot OpenVPX The Ensemble 6000 Series OpenVPX HCD6210 High Compute Density processing module from Mercury Computer Systems combines next-generation Power Architecture processing technology from Freescale with multiple high-speed data movement interfaces and customizable I/O in a single VPX slot. Designed to meet the needs of a variety of applications, the HCD6210 is ideal for both legacy upgrades and new designs, supporting Mercury s extensive MultiCore Plus (MCP) software libraries for optimized algorithms and data movement with virtually no changes required. With rugged air-cooled and conduction-cooled variants available, the HCD6210 can be deployed in applications with the most challenging environmental requirements with confidence. The HCD6210 module is designed to the most commonly deployed OpenVPX payload slot profile, implementing data, control, management and expansion planes to support interoperation with a variety of other modules. Power Architecture Processor and Subsystem Each of the Freescale T GHz 12-core processors integrates 12 of the next-generation e6500 cores, three DDR memory controllers, 75 MB L2 and L3 cache, and a flexible System-on-Chip (SoC) I/O subsystem. Each core retains the high-performance AltiVec vector processing unit. Algorithms optimized for the AltiVec engine will port seamlessly to the T4240 processor. Each processor may be configured with 6 GB or 12 GB of DRAM, providing each core with ample memory for embedded applications. Each processor also has its own independent write-protectable X8 MB boot flash with a protected boot vector to prevent accidental erasure. This flash architecture allows each node to boot independently from other nodes on the module. Failures on a single node can be recovered without disrupting the operation of other nodes on the module or in the system. Each processor is also equipped with an 8 GB application flash to support the fastest boot and application load times possible. High-Bandwidth, Low-Latency Data Plane As per the VITA 46.3 standard, four 4x lanes of Gen2 Serial RapidIO are available for high-bandwidth data movement via the OpenVPX data plane two from each T4240 processor. Supporting Serial RapidIO data rates at up to 5 Gbaud, each T4240 connects to the on-board IDT CPS-1848 RapidIO crossbar, which links the HCD6210 to other modules in the system as well as interconnecting the on-board processors. The Serial RapidIO links can be used to create smaller subsystems with a RapidIO data plane mesh. For larger architectures, the data plane can be switched by an OpenVPX switch module (such as the SFM6101 from Mercury Computer Systems). Data movement over these interfaces can be implemented via multiple software interfaces, such as Mercury s performance-enhanced OpenMPI/OFED layer, or via the legacy ICS software API. 10 Gigabit Ethernet Sensor I/O Interfaces The HCD6210 module takes advantage of the built-in Ethernet interfaces on the T4240 processor to implement high-speed 10 Gigabit Ethernet interfaces to the OpenVPX backplane P6 connector. Two interfaces from each processor deliver a total of four 10GBASE-KX4 connections. These interfaces can be linked to a subsystem 10 Gigabit Ethernet switch (such as the SFM6102), or to an external sensor interface. This allows standard 10 Gigabit Ethernet traffic to be routed directly into the HCD6210, delivering data for processing directly to the heart of the subsystem. Having a direct sensor I/O interface of this nature eliminates costly store-and-forward mechanisms and supports direct subsystem sensor integration with the HCD6210.

2 PCI Express Expansion Plane The HCD6210 also includes dual x8 Gen2 PCI Express interfaces to the OpenVPX expansion plane. An on-board PCI Express switch interconnects these interfaces to each T4240 processor as well as the PMC/ XMC mezzanine site. These interfaces can be combined into a single x16 interface, and can be used to tightly couple other modules in the subsystem to the HCD6210. Examples include specialty processing modules such as the FPGA-based SCFE-V6-OVPX, or expansion PMC/ XMC carriers such as the CCM6020. PMC/XMC Mezzanine Card Flexibility The standard PMC/XMC site local to the HCD6210 can be configured with off-the-shelf mezzanine cards using PCI, PCI-X and PCIe protocols. PMC modules configured to operate at up to 133 MHz are supported by the PMC site. XMCs configured for x8, x4 or x1 Gen2 PCIe are supported on the J15 connector per the VITA 42.3 standard. PMC and XMC user I/O is mapped to the backplane in accordance with the VITA 46.9 draft standard (P64s and x12d+8d patterns). Figure 1. HCD6210 functional block diagram

3 Strong Control Plane Architecture The HCD6210 module implements a strong control plane architecture via Gigabit Ethernet. On-chip Ethernet interfaces provide I/O connectivity to drive system-level Ethernet architectures with the HCD6210. The two T4240 processors are directly connected via dual Gigabit Ethernet interfaces. Two 10/100/1000BASE-T Ethernet interfaces are routed to the OpenVPX control plane backplane interfaces. On air-cooled variants of the HCD6210, these interfaces can be redirected to front-panel RJ-45 connectors. Two 1000BASE-BX Gigabit Ethernet interfaces are brought to the backplane, one from each T4240 processor. These links can connect to additional payload processing modules directly, or be switched by an OpenVPX switch module (such as Mercury s SFM6101). System Management Plane The HCD6210 module leverages the robust, scalable and well-tested system management infrastructure per the draft VITA system management standard. Using the standard I2C bus and IPMI protocol, the on-board system management block implements the Intelligent Platform Management Controller (IPMC) function. This allows the HCD6210 to: Manage system management firmware updates Read sensor values Read and write sensor thresholds, allowing an application to react to thermal, voltage or current variations that exceed those thresholds Reset the entire module Power up/down the entire module Be managed remotely by an OpenVPX Chassis Management Controller (ChMC) at the system level (such as that implemented on the SFM6101 VPX switch module) SBC-Style Additional Features The HCD6210 module provides many of the features typically found on a single-board computer. In addition to the sophisticated management subsystem and fabric interconnect, the HCD6210 provides users with a toolkit enabling many different application use cases. Features include: clock signals taking various actions upon expiration (such as interrupting the processors, resetting the node or resetting the module) measurement up to 30 years capable of interrupting the processor upon expiration boot and application load scenarios, such as network booting as well as independent booting from each processor s on-board flash memory capable of RS-232/422/485 signaling levels, and two of which are RS-232 only level functionality of the HCD6210 module VPX-REDI VPX (VITA 46) defines 6U and 3U board formats with a modern highperformance connector set that is capable of supporting today s high-speed fabric interfaces, such as RapidIO. VPX is most attractive when paired with the Ruggedized Enhanced Design Implementation REDI (VITA 48). The HCD6410 is implemented as a 6U conduction-cooled implementation of VPX-REDI, with air-cooled variants in the same VPX form factor available for less rugged environments. Targeted primarily for harsh-environment embedded applications, VPX-REDI offers extended mechanical configurations supporting higher functional density, such as two-level maintenance (2LM). 2LM allows relatively unskilled maintenance personnel to replace a failed module and restore the system to an operational state in a limited time period. Open Software Environment Mercury has a history of leveraging over 20 years of multicomputer software expertise across its many platforms. This strategy is fully applied to the HCD6210 module. Due to Mercury s investment in leveraged software blocks, software developed on prior generations of OpenVPX hardware based on earlier PowerPC or Intel processors will migrate seamlessly to the HCD6210. Linux or VxWorks development and run-time environments are supported by the same leveraged software libraries on the HCD6210. This open software environment gives the HCD6210 access to a wide ecosystem of stacks, middleware, libraries and tools. Mercury s Scientific Algorithm Library (SAL) is optimized for the on-board AltiVec engine and is available to give the HCD6210 industry-leading signal processing performance. Software support is available on the HCD6210 for the following products: that provides insight into the dynamic interaction of up to a few hundred processors. (Scientific Algorithm Library) is optimized for the AltiVec-based architecture of the HCD6210. Interprocessor Communication System (ICS) support is carried forward from the Race++/MCOE software environment. ICS provides a low-level interprocessor communication API, enabling users to take advantage of the high-bandwidth, low latency Serial RapidIO fabric with an easy-touse software interface. management capabilities for multiple HCD6210 modules. With MCP, applications may use industry standard middleware such as MPI, DRI or CORBA, ported to run seamlessly over the fabric. MCP also offers a software tool which can help migrate legacy applications created with MCOE into the MCP domain.

4 Specifications Two 12-core Freescale QorIQ T4240 AMP Series processors Single PMC/XMC site configured for PCI-X and PCI Express operation SLT6-4F1Q2U2T OpenVPX slot profile MOD6-4F1Q2U2T OpenVPX module profile Air-cooled (commercial or rugged) or conduction-cooled configurations available Maximum power dissipation HCD6210 without XMC W Freescale T GHz Cores per device 12 DDR3 DRAM 6 or 12 GB per processor at 1866 MT/s 8 MB on-board boot flash per processor 8 GB on-board application flash per processor PCI /PCI-X PMC site per IEEE1386/VITA 39 at up to 133 MHz PCI Express XMC site per VITA 42.3 at up to 5 Gbaud User-defined I/O from PMC J14 per VITA 46.9 P64S pattern User-defined I/O from XMC J16 per VITA 46.9 X12D+8D pattern Four 4x Gen2 Serial RapidIO links at 5 Gbaud to P1 backplane connector per VITA 46.3 standard Dual x8 Gen2 PCI Express interfaces to P2 backplane connector Configurable as single x16 PCIe interface Linked to T4240 processors and PMC/XMC site via Gen2 PCIe switch Four 10GBASE-KX4 10 Gigabit Ethernet interfaces to backplane P6 connector Two routed to each T4240 processor Two 10/100/1000Base-T Ethernet ports to backplane (redirectable to front panel on air- cooled variants only) Two backplane 1000BASE-BX Gigabit Ethernet ports to backplane On-board system management block, including MMC functionality IPMI over I2C bus to backplane Four serial interfaces to backplane Two RS-232/422/485 interfaces Two RS-232 interfaces Real-time clock Avionics-class windowing-capable watchdog timer General purpose 32-bit timers/counters per processor Micro-mezzanine for low-level I/O expansion Commercial (L0), L1, L3 rugged-level specifications:

5 Temperature-Operating Temperature-Storage Commercial Rugged Level 1 Rugged Level 3 NOTES 0 to +40 ºC Inlet Air Temperature -25 to +55 ºC Inlet Air Temperature -40 to +71 ºC Card Edge Temp -40 to +85 ºC -55 to +85 ºC -55 to +125 ºC Methods & Rate of Change N/A 5ºC/min 10ºC/min Based on RTCA/DO-160D Humidity Vibration-Random Vibration-Sine Vibration-Shock Altitude-Operating 10 to 90% G 2 /Hz Hz, 1 hr/axis 5 to 95% 0.04 G 2 /Hz Hz, 1 hr/axis 5 to 95% 100% Condensing 0.1 G 2 /Hz Hz, 1 hr/axis N/A N/A 10G Peak Hz, 1 hr/axis Z-Axis - 20G X & Y-axes - 32G Z-axis - 12G X & Y-axes -20G Z-Axis - 50G X & Y-axes - 80G Z-axis - 30G X & Y-axes -50G Z-Axis - 50G X & Y-axes - 80G N/A Methods notice 3 (Aggravated) Methods Based on Mil-HDBK-5400 Methods 516.5, Procedure 1 0 to Ft. 0 to 30,000 Ft. 0 to 70,000 Ft. Operating altitudes are reached by either increasing airflow and/or decreasing inlet air temperature Altitude-Storage 0 to Ft. 0 to Ft. 0 to Ft. Salt Fog N/A Special (Request Test) Designed to 10% NaCl Methods Challenges Drive Innovation, Echotek, EchoCore, Ensemble and MultiCore Plus are registered trademarks, and Application Ready Subsystem and ARS are trademarks of Mercury Computer Systems, Inc. RapidIO is a registered trademark of the RapidIO Trade Association. PCI, PCIe, PCI-X and PCI Express are registered trademarks and/or service marks of PCI-SIG Corporation. OpenVPX is a trademark of VITA. Freescale and AltiVec are registered trademarks of Freescale Semiconductor, Inc. PowerPC is a registered trademark of IBM. Power Architecture is a registered trademark of Power.org. Other products mentioned may be trademarks or registered trademarks of their respective holders. Mercury Computer Systems, Inc. believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject to change without notice. Copyright 2012 Mercury Computer Systems, Inc E DS-hsd6210 CORPORATE HEADQUARTERS 201 Riverneck Road Chelmsford, MA USA