Freescale Semiconductor, Inc.

Transcription

1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semiconductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, program and data memories, a number of peripherals, and system support circuitry. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This combination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP applicatio, especially speech coding, digital communicatio, and cellular base statio. The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP based DSPs, the DSP56156 coists of three execution units operating in parallel, allowing up to six operatio to be performed during each itruction cycle. This parallelism greatly increases the effective processing speed of the DSP The MPU-style programming model and itruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to design and program one greatly reduces the time needed to learn the others. On-Chip Emulation (OnCE TM port) circuitry provides convenient and inexpeive debug facilities normally available only through expeive external hardware. Development costs are reduced and in-field testing is greatly simplified using the OnCE TM port. Figure 1 illustrates the DSP56156 in detail. Internal Data Bus Switch 7 Sigma- Delta Codec 16-bit DSP Core 2 16-bit Timer/ Event Counter nc. Advance Information 16-bit Digital Signal Processor Sync. Serial (SSI) or I/O Sync. Serial (SSI) or I/O Address Generation Unit Host Interface (HI) or I/O Program Memory * RAM ROM (boot) PAB XAB1 XAB2 GDB PDB XDB Data Memory RAM 16-bit Bus External Address Bus Switch External Data Bus Switch Order this document by DSP56156/D REV 1 DSP56156 DSP56156ROM Address 16 Data 16 OnCE Port PLL Clock Gen. Interrupt Control Program Decode Controller Program Control Unit Program Address Generator Data ALU 16 x > 40-bit MAC Two 40-bit Accumulators Bus Control Control IRQ 2 * 12 k x 16 ROM replaces the program RAM on the DSP56156ROM Figure 1 DSP56156 Block Diagram Specificatio and information herein are subject to change without notice. OnCE is a trademark of Motorola, Inc. MOTOROLA INC., 1994

2 nc. Introduction DSP56156 Features DSP56156 Features Digital Signal Processing Core Efficient, object code compatible, 16-bit Family DSP engine Up to 30 Million Itructio Per Second (MIPS) 33 itruction cycle at 60 MHz Up to 180 Million Operatio Per Second (MOPS) at 60 MHz Highly parallel itruction set with unique DSP addressing modes Two 40-bit accumulators including exteion byte Parallel bit multiply-accumulate in 1 itruction cycle (2 clock cycles) Double precision bit multiply with 72-bit result in 6 itruction cycles Least Mean Square (LMS) adaptive loop filter in 2 itructio 40-bit Addition/Subtraction in 1 itruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware-nested DO loops including infinite loops Zero-overhead fast interrupts (2 itruction cycles) Three 16-bit internal data buses and three 16-bit internal address buses for maximum information trafer on-chip Memory On-chip Harvard architecture permitting simultaneous accesses to program and memories bit on-chip program RAM and bit bootstrap ROM (or 12 k 16-bit on-chip program ROM on the DSP56156ROM) bit on-chip data RAM External memory expaion with 16-bit address and data buses Bootstrap loading from external data bus, Host Interface, or Synchronous Serial Interface Peripheral and Support Circuits Byte-wide Host Interface (HI) with Direct Memory Access support Two Synchronous Serial Interfaces (SSI) to communicate with codecs and synchronous serial devices Built in µ-law and A-law compression/expaion Up to 32 software-selectable time slots in network mode 16-bit Timer/Event Counter also generates and measures digital waveforms On-chip sigma-delta voice band Codec: Sampling clock rates between 100 khz and 3 MHz Four software-programmable decimation/interpolation ratios Internal voltage reference ( 2 / 5 of positive power supply) No external components required 2 DSP56156 Data Sheet MOTOROLA

3 nc. Introduction DSP56156 Features Documentation On-chip peripheral registers memory mapped in data memory space Double buffered peripherals Up to 27 general purpose I/O pi Two external interrupt request pi On-Chip Emulation (OnCE ) port for unobtrusive, processor speed-independent debugging Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the core clock Miscellaneous Features Power-saving Wait and Stop modes Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; mm 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; mm 5 V power supply Product Documentation This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156 description and are necessary to properly design with the part. Documentation is available from a local Motorola distributor, a semiconductor sales office, or through a Motorola Literature Distribution Center. Table 1 DSP56156 Documentation Topic Description Order Number DSP56100 Family Manual Detailed description of the family architecture and the 16-bit core processor and itruction set DSP56100FAMUM/AD DSP56156 User s Manual DSP56156 Data Sheet Detailed description of memory, peripherals, and interfaces Pin and package descriptio, and electrical and timing specificatio DSP56156UM/AD DSP56156/D MOTOROLA DSP56156 Data Sheet 3

4 nc. Introduction Documentation Data Sheet Contents Related Documentation Table 2 lists additional documentation relevant to the DSP Table 2 Related Motorola Documentation Topic Description Order Number DSP Family Brochure Overview of all DSP product families BR1105/D Development Tools Product Brief. Includes ordering information DSPTOOLSP/D Fractional and Integer Arithmetic Application Report. Includes code APR3/D Fast Fourier Traforms (FFTs) Application Report. Compreheive FFT algorithms and code for DSP56001, DSP56156, and DSP96002 G.722 Audio Processing Application Report. Theory and code using SB-ADPCM Dr. BuB Bulletin Board Third Party Compendium University Support Program Flyer. Motorola s electronic bulletin board where free DSP software is available Brochures from companies selling hardware and software that supports Motorola DSPs Flyer. Motorola s program that supports universities in DSP research and education APR4/D APR404/D BR297/D DSP3RDPTYPAK/D BR382/D Data Sheet Contents This data sheet contai: signal definitio and pin locatio electrical specificatio and timings package descriptio design coideratio ordering information 4 DSP56156 Data Sheet MOTOROLA

5 nc. Introduction Pin Groupings Pin Groupings The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional groups indicated in Table 3. Figure 2 illustrates the chip s pin functio. Table 3 Functional Pin Groupings Functional Group Number of Pi Address 16 Data Bus 16 Bus Control 9 Host Interface (HI) 15 Synchronous Serial Interfaces (SSI) 10 Timer Interface 2 Interrupt and Mode Control 4 Phase-Locked Loop (PLL) and Clock 3 On-Chip Emulation (OnCE TM Port) 4 On-Chip Codec 7 Power (V CC ) 10 Ground (GND) 16 Total 112 NOTE: OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typically a TTL logic low V IL or V OL ) when the function is logically true. These signals are, likewise, at V CC voltage (typically a TTL logic high V IH or V OH ) when the function is logically false. MOTOROLA DSP56156 Data Sheet 5

6 nc. Introduction Pin Functio A0-A15 D0-D15 RD WR BR BG BS TA PS/DS R/W BB MODA/IRQA MODB/IRQB MODC RESET DSO DSI/OS0 DSCK/OS1 DR MIC AUX SPKP SPKM BIAS VREF VDIV External Bus Interrupt/ Mode Control On-Chip Emulator (OnCE ) Port On-Chip Codec DSP pi Host Interface (HI) Two Synchronous Serial Interfaces (SSI) Timer/Event Counter Clock and Phase-locked Loop (PLL) H0-H7* HA0-HA2* HR/W* HEN* HREQ* HACK* STD0* SRD0* SCK0* SC00-SC10* STD1* SRD1* SCK1* SC01-SC11* TIN* TOUT* EXTAL CLKO SXFC V CC GND * These pi have an alternate function of general purpose input/output. Figure 2 DSP56156 Pin Functio 6 DSP56156 Data Sheet MOTOROLA

7 nc. Pin Descriptio Address and Data Bus Bus Control Pin Descriptio Address and Data Bus A0-A15 D0-D15 (Address Bus) three-state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. (Data Bus) three-state, active high, bidirectional input/outputs. Read data is sampled on the trailing edge of t2, while write data output is enabled by the leading edge of t2 and three-stated at the leading edge of t0. If there is no external bus activity, D0-D15 are three-stated. D0-D15 are also threestated during hardware reset. Bus Control PS/DS (Program/Data Memory Select) three-state, active low output. This output is asserted only when external data memory is referenced. PS/DS timing is the same for the A0-A15 address lines. PS/DS is high for program memory access and is low for data memory access. If the external bus is not used during an itruction cycle (t0, t1, t2, t3), PS/DS goes high in t0. PS/DS is in the high impedance state during hardware reset. R/W (Read/Write) three-state, active low output. Timing is the same as the address lines, providing an early write signal. R/W (which changes in t0) is high for a read access and is low for a write access. If the external bus is not used during an itruction cycle (t0, t1, t2, t3), R/W goes high in t0. R/W is three-stated during hardware reset. WR (Write Enable) three-state, active low output. This output is asserted during external memory write cycles. When WR is asserted in t1, the data bus pi D0-D15 become outputs and the DSP puts data on the bus during the leading edge of t2. When WR is deasserted in t3, the external data has been latched iide the external device. When WR is asserted, it qualifies the A0-A15 and PS/DS pi. WR can be connected directly to the WE pin of a static RAM. WR is threestated during hardware reset or when the DSP is not bus master. RD (Read Enable) three-state, active low output. This output is asserted during external memory read cycles. When RD is asserted in late t0/early t1, the data bus pi D0-D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted in t3, the external data is latched iide the DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pi. RD can be connected directly to the OE pin of a static RAM or ROM. RD is three-stated during hardware reset or when the DSP is not bus master. BS (Bus Strobe) three-state, active low output. Asserted at the start of a bus cycle (during t0) and deasserted at the end of the bus cycle (during t2). This pin provides an early bus start signal which can be used as address latch and as an early bus end signal which can be used by an external bus controller. BS is three-stated during hardware reset. MOTOROLA DSP56156 Data Sheet 7

8 nc. Pin Descriptio Bus Control TA (Trafer Acknowledge) active low input. If there is no external bus activity, the TA input is ignored by the DSP. When there is external bus cycle activity, TA can be used to iert wait states in the external bus cycle. TA is sampled on the leading edge of the clock. Any number of wait states from 1 to infinity may be ierted by using TA. If TA is sampled high on the leading edge of the clock beginning the bus cycle, the bus cycle will end 2T after the TA has been sampled low on a leading edge of the clock; if the Bus Control Register (BCR) value does not program more wait states. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. TA is still sampled during the leading edge of the clock when wait states are controlled by the BCR value. In that case, TA will have to be sampled low during the leading edge of the last period of the bus cycle programmed by the BCR (2T before the end of the bus cycle programmed by the BCR) in order not to add any wait states. TA should always be deasserted during CLKO t3 to be sampled high by the leading edge of T0. If TA is sampled low (asserted) at the leading edge of the t0 beginning the bus cycle, and if no wait states are specified in the BCR register, zero wait states will be ierted in the external bus cycle, regardless the status of TA during the leading edge of T2. BR (Bus Request) active low output when in master mode, active low input when in slave mode. After poweron reset, this pin is an input (slave mode). In this mode, the bus request BR allows another device such as a processor or DMA controller to become the master of the DSP external data bus D0-D15 and external address bus A0-A15. The DSP asserts BG a few T states after the BR input is asserted. The DSP bus controller releases control of the external data bus D0-D15, address bus A0-A15 and bus control pi PS/DS, RD, WR, and R/W at the earliest time possible coistent with proper synchronization. These pi are then placed in the high impedance state and T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 TA BS CLKO T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2 TA BS Figure 3 TA Controlled Accesses 8 DSP56156 Data Sheet MOTOROLA

9 nc. Pin Descriptio Bus Control the BB pin is deasserted. The DSP continues executing itructio only if internal program and data memory resources are accessed. If the DSP requests the external bus while BR input pin is asserted, the DSP bus controller ierts wait states until the external bus becomes available (BR and BB deasserted). Note that interrupts are not serviced when a DSP itruction is waiting for the bus controller. Note also that BR is prevented from interrupting the execution of a read/ modify/write itruction. If the master bit in the OMR register is set, this pin becomes an output (Master Mode). In this mode, the DSP is not the external bus master and has to assert BR to request the bus mastership. The DSP bus controller will iert wait states until BG input is asserted and will then begin normal bus accesses after the rising of the clock which sampled BB high. The BR output signal will remain asserted until the DSP no longer needs the bus. In this mode, the Request Hold bit (RH) of the Bus Control Register (BCR) allows BR to be asserted under software control. During external accesses caused by an itruction executed out of external program memory, BR remai asserted low for coecutive external X memory accesses and continues toggling for coecutive external P memory accesses unless the Request Hold bit (RH) is set iide the Bus Control Register (BCR). In the master mode, BR can also be used for non arbitration purpose: if BG is always asserted, BR is asserted in t0 of every external bus access. It can then be used as a chip select to turn a external memory device off and on between internal and external bus accesses. BR timing is in that case similar to A0-A15, R/W and PS/DS; it is asserted and deasserted during t0. BG (Bus Grant) active low input when in master mode, active low output when in slave mode. Output after power on reset if the slave is selected, this pin is asserted to acknowledge an external bus request. It indicates that the DSP will release control of the external address bus A0-A15, data bus D0-D15 and bus control pi when BB is deasserted. The BG output is asserted in respoe to a BR input. When the BG output is asserted and BB is deasserted, the external address bus A0-A15, data bus D0-D15 and bus control pi are in the high impedance state. BG assertion may occur in the middle of an itruction which requires more than one external bus cycle for execution. Note that BG assertion will not occur during indivisible read-modify-write itructio (BFSET, BFCLR, BFCHG). When BR is deasserted, the BG output is deasserted and the DSP regai control of the external address bus, data bus, and bus control pi when the BB pin is sampled high. This pin becomes an input if the master bit in the OMR register is set (Master Mode). It is asserted by an external processor when the DSP may become the bus master. The DSP can start normal external memory access after the BB pin has been deasserted by the previous bus master. When BG is deasserted, the DSP will release the bus as soon as the current trafer is completed. The state of BG may be tested by testing the BS bit in the Bus Control Register. BG is ignored during hardware reset. MOTOROLA DSP56156 Data Sheet 9

10 nc. Pin Descriptio Bus Control Interrupt and Mode Control BB (Bus Busy) active low input when not bus master, active low output when bus master. This pin is asserted by the DSP when it becomes the bus master and it performs an external access. It is deasserted when the DSP releases bus mastership. BB becomes an input when the DSP is no longer the bus master. Interrupt and Mode Control MODA/IRQA (Mode Select A/External Interrupt Request A) input. This input has two functio: to select the initial chip operating mode and, to allow an external device to request a DSP interrupt after internal synchronization. MODA is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODA pin changes to the external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request which indicates that an external device is requesting service. It may be programmed to be level seitive or negative edge triggered. If level seitive triggering is selected, an external pull up resistor is required for wired-or operation. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state. MODB/IRQB (Mode Select B/External Interrupt Request B) input. This input has two functio: to select the initial chip operating mode and, to allow an external device to request a DSP interrupt after internal synchronization. MODB is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODB pin changes to the external interrupt request IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request which indicates that an external device is requesting service. It may be programmed to be level seitive or negative edge triggered. If level seitive triggering is selected, an external pull up resistor is required for wired- OR operation. MODC (Mode Select C) input. This input selects the initial bus operating mode. When tied high, the external bus is programmed in the master mode (BR output and BG input) and when tied low the bus is programmed in the slave mode (BR input and BG output). MODC is read and internally latched in the DSP when the processor exits the reset state. After RESET, the bus operating mode can be changed by software by writing the MC bit of the OMR register. RESET (Reset) input. This input is a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the reset state. A Schmitt 10 DSP56156 Data Sheet MOTOROLA

11 nc. Pin Descriptio Interrupt and Mode Control Host Interface trigger input is used for noise immunity. When the reset pin is deasserted, the initial chip operating mode is latched from the MODA and MODB pi, and the initial bus operating mode is latched from the MODC pin. The internal reset signal should be deasserted synchronized with the internal clocks. Host Interface H0-H7 (Host Data Bus) bidirectional. This bidirectional data bus is used to trafer data between the host processor and the DSP. This bus is an input unless enabled by a host processor read. H0-H7 may be programmed as Port B general purpose parallel I/O pi called PB0-PB7 when the Host Interface (HI) is not being used. HA0-HA2 (Host Address 0-2) input*. These inputs provide the address selection for each HI register and are stable when HEN is asserted. HA0-HA2 may be programmed as Port B general purpose parallel I/O pi called PB8-PB10 when the HI is not being used. HR/W (Host Read/Write) input*. This input selects the direction of data trafer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is traferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is traferred to the DSP. When HEN is asserted, HR/W is stable. HR/W may be programmed as a general purpose I/O pin called PB11 when the HI is not being used. HEN (Host Enable) input*. This input enables a data trafer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 becomes an output and DSP data may be latched by the host processor. When HEN is asserted and HR/W is low, H0-H7 is an input and host data is latched iide the DSP when HEN is deasserted. Normally a chip select signal derived from host address decoding and an enable clock is connected to the Host Enable. HEN may be programmed as a general purpose I/O pin called PB12 when the HI is not being used. HREQ (Host Request) output*. This opendrain output signal is used by the HI to request service from the host processor. HREQ may be connected to an interrupt request pin of a host processor, a trafer request of a DMA controller, or a control input of external circuitry. HREQ is asserted when an enabled request occurs in the HI. HREQ is deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used. HACK (Host Acknowledge) input*. This input has two functio: to provide a host acknowledge signal for DMA trafers and, to control handshaking and to provide a host interrupt acknowledge compatible with MC68000 family processors. If programmed as a host acknowledge signal, HACK may be used as a data strobe for HI DMA data trafers. If programmed as an MC68000 host interrupt * These pi can be bidirectional when programmed as general purpose I/O. MOTOROLA DSP56156 Data Sheet 11

12 nc. Pin Descriptio 16-bit Timer SSI acknowledge, HACK enables the HI Interrupt Vector Register (IVR) onto the host data bus H0-H7 if the Host Request HREQ output is asserted. In this case, all other HI control pi are ignored and the HI state is not affected. HACK may be programmed as a general purpose I/O pin called PB14 when the HI is not being used. 16-bit Timer TIN (Timer Input) input*. This input receives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. TIN may be programmed as a general purpose I/O pin called PC10 when the external event function is not being used. TOUT (Timer Output) output*. This output generates pulses or toggles on a timer overflow event or a compare event. TOUT may be programmed as a general purpose I/O pin called PC11 when disabled by the timer out enable bits (TO2-TO0). Synchronous Serial Interfaces (SSI) STD0-1 (SSI0-1 Tramit Data) output*. These output pi tramit serial data from the SSI0-1 Tramit Shift Register. STD0 and STD1 may be programmed as a general purpose I/O pin called PC0 and PC5, respectively, when the STD function is not being used. SRD0-1 (SSI0-1 Receive Data) input*. These input pi receive serial data and trafer the data to the SSI0-1 Receive Shift Register. SRD0 and SRD1 may be programmed as a general purpose I/O pin called PC1 and PC6, respectively, when the SRD function is not being used. SCK0-1 (SSI0-1 Serial Clock) bidirectional. These bidirectional pi provide the serial bit rate clock for the SSI0-1 interface. SCK0 and SCK1 may be programmed as a general purpose I/O pin called PC2 and PC7, respectively, when the SSI0-1 interfaces are not being used. SC10-11 (SSI0-1 Serial Control 1) bidirectional. These bidirectional pi are used by the SSI0-1 serial interface as frame sync I/O or flag I/O. SC10 and SC11 may be programmed as a general purpose I/O pin called PC3 and PC8, respectively, when the SSI0-1 are not using these pi. SC00-01 (SSI0-1 Serial Control 0) bidirectional. These bidirectional pi are used by the SSI0-1 serial interface as frame sync I/O or flag I/O. SC00 and SC01 may be programmed as a general purpose I/O pin called PC4 and PC9, respectively, when the SSI0-1 are not using these pi. * These pi can be bidirectional when programmed as general purpose I/O. 12 DSP56156 Data Sheet MOTOROLA

13 nc. Pin Descriptio OnCE On-Chip Codec On-Chip Emulation (OnCE TM Port) DSI/OS0 (Debug Serial Input/Chip Status 0) bidirectional. The DSI/OS0 pin, when an input, is the pin through which serial data or commands are provided to the OnCE port controller. The data received on the DSI pin will be recognized only when the DSP has entered the debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSP is not in the debug mode, the DSI/ OS0 pin provides information about the chip status if it is an output and used in conjunction with the OS1 pin. DSCK/OS1 (Debug Serial Clock/Chip Status 1) bidirectional. The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE serial port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge. If the DSCK/OS1 pin is an output and used in conjunction with the OS0 pin, it provides information about the chip status when the DSP is not in the debug mode. DSO (Debug Serial) output. The debug serial output provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. When idle, this pin is high. When the requested data is available, the DSO line will be asserted (negative true logic) for four T cycles (one itruction cycle) to indicate that the serial shift register is ready to receive clocks in order to deliver the data. When the chip enters the debug mode due to an external debug request (DR), an internal software debug request (DEBUG), a hardware breakpoint occurrence or a trace/step occurrence, this line will be asserted for three T cycles to indicate that the chip has entered the debug mode and is waiting for commands. Data is always shifted out the OnCE serial port with the most significant bit first. DR (Debug Request) input. The debug request input provides a mea of entering the debug mode of operation. This pin, when asserted, will cause the DSP to finish the current itruction being executed, enter the debug mode, and wait for commands to be entered from the debug serial input line. On-Chip Codec AUX (Auxiliary) input. This pin is selected as the analog input to the A/D converter when the INS bit is set in the codec control register COCR. This pin should be left floating when the codec is not used. BIAS (Bias current) input. This input is used to determine the bias current for the analog circuitry. Connecting a resistor between BIAS and GNDA will program the current bias generator. This pin should be left floating when the codec is not used. MIC (Microphone) input. This pin is selected as the analog input to the A/D converter when the INS bit is cleared in MOTOROLA DSP56156 Data Sheet 13

14 nc. Pin Descriptio On-Chip Codec Power, Ground, and Clock the codec control register COCR. This pin should be left floating when the codec is not used. SPKP (Speaker Plus) output. This pin is the positive analog output from the onchip D/A converter. This pin should be left floating when the codec is not used. SPKM (Speaker Minus) output. This pin is the negative analog output from the on-chip D/A converter. This pin should be left floating when the codec is not used. VREF (Voltage Reference) output. This pin is the op-amp buffer output in the reference voltage generator. It has a value of ( 2 / 5 )V CCA. This pin should always be connected to the GNDA through two capacitors, even when the codec is not used. VDIV (Voltage Division) output. This output pin is also the output to the onchip op-amp buffer in the reference voltage generator. It is connected to a resistor divider network located within the codec block which provides a voltage equal to ( 2 / 5 )V CCA. This pin should be connected to the GND via a capacitor when the codec is used and should be left floating when the codec is not used. Power, Ground, and Clock V CC (Power) Power pi GND (Ground) Ground pi V CCS (Synthesizer Power) This pin supplies a quiet power source to the Phase- Locked Loop (PLL) to provide greater frequency stability. GNDS (Synthesizer Ground) This pin supplies a quiet ground source to the PLL to provide greater frequency stability. V CCA (Analog Power) This pin is the positive analog supply input. It should be connected to V CC when the codec is not used. GNDA (Analog Ground) This pin is the analog ground return. It should be connected to digital GND when the codec is not used. EXTAL (External Clock) input. This input should be driven by an external clock or by an external oscillator. After being squared, the input frequency can be used as the DSP core internal clock. In that case, it is divided by two to produce a four phase itruction cycle clock, the minimum itruction time being two input clock periods. This input frequency is also used, after division, as input clock for the on-chip codec and the onchip PLL. CLKO (Clock Output) output. This pin outputs a buffered clock signal. By programming two bits (CS1-CS0) iide the PLL Control Register (PLCR), the user can select between outputting a squared version of the signal applied to EXTAL, a squared version of the signal applied to EXTAL divided by 2, and a delayed version of the DSP core master clock. The clock frequency on this pin can be disabled by setting the Clockout Disable bit (CD; bit 7) of the Operating Mode Register (OMR). When disabled, the pin can be left floating. SXFC (External Filter Capacitor) This pin adds an external capacitor to the PLL filter circuit. A low leakage capacitor should be connected between and located very close to SXFC and V CCS. 14 DSP56156 Data Sheet MOTOROLA

15 nc. Electrical Characteristics and Timing Electrical Characteristics and Timing CAUTION: Exceeding maximum electrical ratings will permanently damage or disable the chip, or impair the chip s long term reliability. The DSP56156 is fabricated in high deity HCMOS with TTL compatible inputs and CMOS compatible outputs. Table 4 Maximum Electrical Ratings (GND = 0 Vdc) Rating Symbol Value Unit Supply Voltage V CC -0.3 to +7.0 V All Input Voltages V IN GND to V CC V Current Drain per Pin excluding V CC and GND I 10 ma Storage Temperature T stg -55 to +150 C Table 5 Operating Conditio Supply Voltage V CC Junction Temperature T J ( C) Min Max Min Max Table 6 Thermal Characteristics of CQFP and TQFP Packages Thermal Resistance Characteristics Symbol CQFP Value TQFP Rating Junction to Ambient Θ JA C/W Junction to Case (estimated) Θ JC 7 8 C/W NOTE: This device contai protective circuitry to guard agait damage due to high static voltage or electrical fields. However, normal precautio are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC ). MOTOROLA DSP56156 Data Sheet 15

16 Electrical Characteristics and Timing Analog I/O Characteristics nc. Analog I/O Characteristics (V CCA = 5.0 V dc ± 10%, T J = -40 to +125 C) The analog I/O characteristics of this device are listed in Table 7. For additional information regarding the use of analog signals, see Design Coideratio at the end of this document. Table 7 Analog I/O Characteristics Characteristic Min Typ Max Unit Input Impedance on MIC and AUX (See Note 1) kω Input Capacitance on MIC and AUX 10 pf Peak Input Voltage on the MIC/AUX Input for Full Scale Linearity (0.14 dbm0): 6 db - MGS1-0 = 00 (See Note 2) 0 db - MGS1-0 = 01 6 db - MGS1-0 = db - MGS1-0 = 11 Internal Input Gain Variation; G = -6 db, 0 db, 6 db or 17 db (±0.83 db variation due to 10% variation on V CC ): Vp Vp mvp mvp G G G db VREF Output Voltage V VREF Output Current ±1 ma DC Offset Between SPKP and SPKM 100 mv Allowable Differential Load Capacitance on SPKP and SPKM (with 1 kω in series) Allowable Single-ended Load Capacitance on SPKP or SPKM (with 0.5 kω in series) µf 0 (See Note 3) Maximum Single-ended Signal Output Level 1 Vp Maximum Differential Signal Output Level 2 Vp µf Single-ended Load Resistance 500 Ω Differential Load Resistance 1 kω Resistance BIAS 10 (See Note 4) kω Internal Output Volume Control Variation VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 db (± 0.83 db variation due to 10% variation on V CC ) VC VC VC db NOTES: 1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 khz 2. 0 dbm0 corresponds to 3.14 db below the input saturation level 3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF 4. ± 10% 16 DSP56156 Data Sheet MOTOROLA

17 nc. Electrical Characteristics and Timing A/D and D/A Performance A/D and D/A Performance (V CCA = 5.0 V dc ± 10%, T J = -40 to +125 C) The A/D and D/A performance of the codec section are given in Table 8 with an example presented in Figure 4. Table 8 A/D and D/A Performance of Codec Characteristic Level Min Analog to Digital Section Signal to Noise plus Distortion Ratio (S/N+T) Digital to Analog Section Signal to Noise plus Distortion Ratio (S/N+T) 0 dbm0 (See Note 2) Typ (See Note 1) NOTES: 1. 0 db gain on the A/D and D/A; Codec clock at MHz with 128 decimation/interpolation ratio and tested at 1502 Hz 2. 0 dbm0 corresponds to db below the input saturation level S/N S/N+T Max Unit db -50 dbm db 0 db db -50 db db 13 MHz 2 MHz 6.5 CODEC Codec 13 1 MHz PLL (12+1)*4 (12+1)x4 COCR=$E MHz Signal S in db in db Figure 4 Example: S/N and S/N+T Performance for the A/D Section MOTOROLA DSP56156 Data Sheet 17

18 Electrical Characteristics and Timing Other On-Chip Codec Characteristics nc. Other On-Chip Codec Characteristics (V CCA = 5.0 V dc ± 10%, T J = -40 to +125 C, C L = 50 pf + 1 TTL Load) The analog I/O characteristics of this device are shown in Table 9. Table 9 Analog I/O Characteristics of On-Chip Codec Characteristic Min Typ Max Unit Codec Master Clock MHz Codec Sampling Rate Hz A/D Section Group Delay 0.2 msec D/A Section Group Delay 0.2 msec 18 DSP56156 Data Sheet MOTOROLA

19 nc. DC Electrical Characteristics and Timing DC Electrical Characteristics (GND = 0 V dc) (V CC = 5.0 V dc ± 10%, T J = -40 to +125 C, C L = 50 pf + 1 TTL Load) The DC electrical characteristics of this device are shown in Table 10. Table 10 DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Input High Voltage except EXTAL, RESET, MODA, MODB, MODC Input Low Voltage except EXTAL, MODA, MODB, MODC Input High Voltage EXTAL DC coupled EXTAL AC coupled (See Note 1) Input Low Voltage EXTAL DC coupled EXTAL AC coupled (See Note 1) V IH 2.0 V CC V V IL V V IHC 70% of V CC 1 V ILC V CC V CC 20% of V CC V CC -1 Input High Voltage RESET V IHR 2.5 V CC V Input High Voltage MODA, MODB, MODC V IHM 3.5 V CC V Input Low Voltage MODA, MODB, MODC V ILM V Input Leakage Current EXTAL RESET, MODA, MODB, MODC, TA, DR, BR Three-State (Off-State) Input Current (@2.4 V/0.5 V) I IN V V µa µa TSI µa Output High Voltage (I OH = -10 µa) V OHC V CC -0.1 V Output High Voltage (I OH = -0.4 ma) V OH 2.4 V Output Low Voltage (I OL = 10 µa) V OLC 0.1 V Output Low Voltage (I OL = 3.2 ma R/W I OL = 1.6 ma; Open Drain HREQ I OL = 6.7 ma, TXD I OL = 6.7 ma) V OL 0.4 V Input Capacitance (See Note 2) C IN 10 pf NOTES: 1. When EXTAL is AC coupled, V IHC - V ILC Š 1 V must be true. 2. Input capacitance is periodically sampled and not 100% tested in production. MOTOROLA DSP56156 Data Sheet 19

20 AC Electrical Characteristics and Timing Clock Operation Timing nc. AC Electrical Characteristics (GND = 0 V dc) The timing waveforms in the AC Electrical Characteristics are tested with a V IL maximum of 0.5 V and a V IH minimum of 2.4 V for all pi, except EXTAL, RESET, MODA, MODB and MODC. These five pi are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specificatio which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal s traition. The DSP56156 output levels are measured with the production test machine V OL and V OH reference levels set at 0.8 V and 2.0 V respectively. Clock Operation Timing The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in Figure 6. Num Characteristics Sym Table 11 Clock Operation Timing 40 MHz 50 MHz 60 MHz Min Max Min Max Min Max 1 Frequency of Operation (EXTAL) f MHz 2 Itruction Cycle Time = 2T C I CYC Wait State Time = T C = 2T EXTAL Cycle Period T C EXTAL Rise Time (See Note 1) EXTAL Fall Time (See Note 1) EXTAL Width High 48-52% duty cycle (See Notes 2, 3, 4) Unit T H EXTAL Width Low 48%-52% duty cycle (See Notes 2, 3, 4) T L NOTES: 1. Rise and fall time may be relaxed to 12 maximum if the EXTAL input frequency is less than or equal to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should meet the specified values in the 40 MHz column (4 maximum). 2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that T H and T L meet the specified values in the 40 MHz column (12 minimum). 3. T = I CYC / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty cycle of the external clock input. 4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and at V CC /2 when not AC coupled. 20 DSP56156 Data Sheet MOTOROLA

21 nc. T H T L 90% AC Electrical Characteristics and Timing Clock Operation Timing PLL V IHC EXTAL Midpoint 10% VILC Figure 5 External Clock Timing Other Clock and PLL Operation Timing Clock and PLL timings are listed in Table 12 and the clocking configuratio are illustrated in Figure 6. Table 12 Clock and PLL Timing Characteristics Min Max Unit PLL Output frequency 10 Max Fosc (See Note 1) MHz EXTAL Input Clock Amplitude (See Note 2) 1 V CC Vpp NOTES: 1. Maximum DSP operating frequency. See Table An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level range (V ILC >20% of V CC or V IHC <70% of V CC ). EXTAL 100 KΩ 1 to 16 ED3-ED0 PFD SXFC 10 nf LF XFC 0.01 µf 0.1 µf V CCS VCO GNDS PLLE=1 Fosc 1000 pf PLL 1 to 16 YD3-YD0 4 PLLE=0 CS1-CS0 6.5 GSM CODEC CLKO 2 internal phase PH0 at Fosc Figure 6 Clocking Configuratio MOTOROLA DSP56156 Data Sheet 21

22 AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing nc. Reset, Stop, Wait, Mode Select, and Interrupt Timing (V CC = 5.0 V dc ± 10%, T J = -40 to +125 C, C L = 50 pf + 1 TTL Load) cyc = Clock cycle = 1 / 2 itruction cycle = 2 T cycles ws = Number of wait states programmed into external bus access using BCR (WS = 0-31) Num Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristics 10 RESET Assertion to Address, Data and Control Signals High Impedance 11 Minimum Stabilization Duration (See Note 1) OMR bit 6=0 OMR bit 6=1 12 Asynchronous RESET Deassertion to First External Address Output (See Note 7) 13 Synchronous Reset Setup Time from RESET Deassertion to Rising Edge of CLKO 14 Synchronous Reset Delay Time from CLKO High to the First External Access (See Note 7) 40 MHz 50 MHz 60 MHz Min Max Min Max Min Max Unit KT 60T 600KT 60T 600KT 60T 16T 18T+20 16T 18T+17 16T 18T+15 7 cyc-4 6 cyc-3 5 cyc-2 16T+3 16T+20 16T+ 3 16T+18 16T+3 16T Mode Select Setup Time Mode Select Hold Time Edge-triggered Interrupt Request Width Delay from IRQA, IRQB Assertion to External Data Memory Access Out Valid - Caused by First Interrupt Itruction Fetch - Caused by First Interrupt Itruction Execution 11T+4 19T+4 11T+4 19T+4 11T+3 19T+3 19 Delay from IRQA, IRQB Assertion to General Purpose Output Valid Caused by the Execution of the First Interrupt Itruction 22T+5 22T+4 22T+3 20 Delay from External Data Memory Address Output Valid Caused by First Interrupt Itruction Execution to Interrupt Request Deassertion for Level Seitive Fast Interrupts (See Note 2) 5T-26 + cyc ws 5T-24 + cyc ws 5T-22 + cyc ws 22 DSP56156 Data Sheet MOTOROLA

23 nc. AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing (V CC = 5.0 V dc ± 10%, T J = -40 to +125 C, C L = 50 pf + 1 TTL Load) Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued) Num Characteristics 40 MHz 50 MHz 60 MHz Min Max Min Max Min Max Unit 21 Delay from General-Purpose Output Valid Caused by the Execution of the First Interrupt Itruction to IRQA, IRQB Deassertion for Level Seitive Fast Interrupts If 2nd Interrupt Itruction is: Single Cycle (See Note 2) Two Cycles 22 Synchronous setup time from IRQA, IRQB assertion to Synchronous falling edge of CLKO (See Notes 5 and 6) 23 Falling Edge of CLKO to First Interrupt Vector Address Out Valid after Synchronous recovery from Wait State (See Notes 3 and 5) 24 IRQA Width Assertion to Recover from Stop State (See Note 4) 25 Delay from IRQA Assertion to Fetch of first itruction (exiting Stop) (See Notes 1 and 3) OMR bit 6=0 OMR bit 6=1 28 Duration for Level Seitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Itruction (exiting Stop) (See Notes 1 and 3) OMR bit 6=0 OMR bit 6=1 cyc cyc - 29 cyc cyc - 27 cyc cyc cyc-3 13 cyc-2 12 cyc-1 27T+3 27T+20 27T+3 27T+18 27T+3 27T T+4 47T T 47T T+3 47T T 47T T+3 47T T 47T 29 Delay from Level Seitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) (See Notes 1 and 3) OMR bit 6=0 OMR bit 6= T+4 47T T+3 47T T+3 47T+3 MOTOROLA DSP56156 Data Sheet 23

24 AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing nc. NOTES: 1. Circuit stabilization delay is required during reset when using an external clock in two cases: after power-on reset when recovering from Stop mode 2. When using fast interrupts, IRQA or IRQB is defined as level-seitive, then timings 20 and 21 apply to prevent multiple interrupt service. To avoid these timing restrictio, the negative edge-triggered mode is recommended when using fast interrupts. 3. The interrupt itruction fetch is visible on the pi only in Mode The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state. 6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state. 7. The itruction fetch is visible on the pi only in Mode 2 and Mode 3. RESET D0-D15 A0-A15 PS/DS R/W BS CLKO Figure 7 Asynchronous Reset Timing V IHR First Fetch 13 RESET A0-A15 PS/DS BS R/W 14 Figure 8 Synchronous Reset Timing 24 DSP56156 Data Sheet MOTOROLA

25 nc. AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET V IHR MODA MODB MODC V IHM V ILM V IH V IL IRQA IRQB IRQA IRQB A0-A15 PS/DS BS R/W IRQA IRQB Figure 9 Operating Mode Select Timing 17 Figure 10 External Interrupt Timing (Negative Edge-Triggered) First Interrupt Itruction Execution a) First Interrupt Itruction Execution General Purpose I/O Pin IRQA IRQB b) General Purpose I/O Figure 11 External Level-Seitive Fast Interrupt Timing MOTOROLA DSP56156 Data Sheet 25

26 AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing nc. CLKO T0, T2 phi0 T1, T3 phi1 IRQA IRQB 22 A0-A15 PD/DS BS R/W 23 First Interrupt Itruction Fetch IRQA A0-A15 PD/DS BS R/W Figure 12 Synchronous Interrupt from Wait State Timing First Itruction Fetch Not IRQA Interrupt Vector Figure 13 Recovery from Stop State Using Asynchronous Interrupt Timing IRQA 28 A0-A15 PD/DS BS R/W 29 First IRQA Interrupt Itruction Fetch Figure 14 Recovery from Stop State Using IRQA Interrupt Service 26 DSP56156 Data Sheet MOTOROLA

27 nc. AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 14 Wait and Stop Timings Num Characteristics 40 MHz 50 MHz 60 MHz Min Max Min Max Min Max Unit 30 DR Asserted to CLK high (Setup Time for Synchronous Recovery from Wait State) 31 CLK high to DSO (ACK) Valid (Enter Debug Mode) after Synchronous Recovery from Wait State 10 cyc cyc cyc cyc 18 cyc 18 cyc 32 DR to DSO (ACK) Valid (Enter Debug Mode) - After Asynchronous Recovery from Stop State - After Asynchronous Recovery from Wait State 33 DR Assertion Width - to Recover from Wait/Stop without entering debug mode - to Recover from Wait/Stop short wake-up and enter debug mode - to Recover from Stop long wake-up and enter debug mode DR (input) 29 cyc 18 cyc cyc cyc 10 cyc cyc 18 cyc cyc cyc 10 cyc 29 cyc 18 cyc cyc cyc 10 cyc 32 DSO (output) Figure 15 Recovery from Wait State Using DR Pin Synchronous Timing MOTOROLA DSP56156 Data Sheet 27

28 AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing Capacitance Derating nc. CLKO (output) T0, T2 T1, T3 DR (input) 33 DSO (output) Figure 16 Recovery from Wait/Stop State Using DR Pin Asynchronous Timing Capacitance Derating 30 The DSP56156 External Bus Timing Specificatio are designed and tested at the maximum capacitive load of 50 pf, including stray capacitance. Typically, the drive capability of the External Bus pi (A0-A15, D0-D15, PS/DS, RD, BS, WR, R/W) derates linearly at 1 per 12 pf of additional capacitance from 50 pf to 250 pf of loading. Port B and C pi derate linearly at 1 per 5 pf of additional capacitance from 50 pf to 250 pf of loading. When an internal memory access follows an external memory access, the PS/DS, R/W, RD and WR strobes remain deasserted and A0-A15 do not change from their previous state DSP56156 Data Sheet MOTOROLA

29 nc. AC Electrical Characteristics and Timing External Bus Synchronous Timing External Bus Synchronous Timing (V CC = 5.0 V dc ± 10%, T J = -40 to +125 C, C L = 50 pf + 1 TTL Load) Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings with no wait states and two wait states, respectively. Table 15 External Bus Synchronous Timing Num Characteristic 40 MHz 50 MHz 60 MHz Min Max Min Max Min Max 34 EXTAL CLK In High to CLKO High CLKO High to a. A0-A15 Valid b. PS/DS, R/W Valid, BS, RD Asserted (See Note) 36 BS Width Deasserted CLKO High to WR Asserted Low T+3.1 T+12.4 T+3.1 T+12.4 T+3.1 T WR and RD Deasserted High to BS Asserted Low (2 Successive Bus Cycles) 39 <intentionally blank> 4 Unit CLKO High to BS Deasserted TA Valid to CLKO High (Setup) CLKO High to TA Invalid (Hold) CLKO High to D0-D15 Out Valid CLKO High to D0-D15 Out Invalid D0-D15 In Valid to CLKO Low (Setup) CLKO Low to D0-D15 In Invalid (Hold) CLKO Low to WR, RD Deasserted WR, RD Hold Time from CLKO Low CLKO High to D0-D15 Three-state CLKO High to D0-D15 Out Active CLKO High to A0-A15, PS/DS, R/W Invalid NOTE: 10 C L = 25 pf MOTOROLA DSP56156 Data Sheet 29

30 AC Electrical Characteristics and Timing External Bus Synchronous Timing nc. EXTAL (Input) T0 T1 T2 T3 T0 T1 T2 CLKO (Output) 34 A0-A15 PS/DS R/W (See Note) BS (Output) WR (Output) RD (Output) TA (Input) D0-D15 (Output) Data Out D0-D15 (Input) 45 Data In 46 NOTE: During Read-Modify-Write itructio and internal itructio, the address lines do not change state. Figure 17 External Bus Synchronous Timing No Wait States 30 DSP56156 Data Sheet MOTOROLA

31 nc. AC Electrical Characteristics and Timing External Bus Synchronous Timing EXTAL (Input) T0 T1 T2 Tw T2 Tw T2 T3 T0 CLKO (Output) A0-A15, PS/DS, R/W (Outputs) BS (Output) WR (Output) RD (Output) TA (Input) D0-D15 (Output) 43 Data Out D0-D15 (Input) Data In Figure 18 External Bus Synchronous Timing Two Wait States MOTOROLA DSP56156 Data Sheet 31