MEMORIES. Memories. EEC 116, B. Baas 3

Transcription

1 MEMORIES Memories VLSI memories can be classified as belonging to one of two major categories: Individual registers, single bit, or foreground memories Clocked: Transparent latches and Flip-flops Unclocked: SR latches, etc. Arrays, background memories Key design goal: density, especially for the memory s. This means fitting the largest amount of memory storage into a certain amount of chip area EEC 116, B. Baas 3 1

2 Array Memories 1. Read-write memories SRAM: Static random access memory Data is stored as the state of a bistable circuit typically using back-to-back inverters State is retained without refresh as long as power is supplied DRAM: Dynamic random access memory Data is stored as a charge on a capacitor State leaks away, refresh is required 2. ROM: Read-only memory, non-volatile Basic ROM mask programmed at design time PROM: Programmable read-only memory; typically programmed at manufacture time by a PROM burner 3. NVRWM: Non-volatile read-write memory EPROM: Erasable ROM, erasable with UV light Flash: ROM at low voltages, writable at high voltages EEC 116, B. Baas 4 Memories Array memories contain three main components: Array of s Address decoder Read circuitry (sense amplifiers) And a fourth if it supports writes (not ROMs): Write circuitry Address decoder bitline Read / (Write) circuitry wordline EEC 116, B. Baas 5 2

3 bitlines Memories Differential bitlines Differential bitlines (bitline and bitline_) require more area but dramatically increase robustness and speed Much smaller voltage differences can be detected Much more noise can be tolerated Address decoder Read / (Write) circuitry wordline EEC 116, B. Baas 6 Six-Transistor (6T) SRAM Cell Cross-coupled inverters: a bistable element (two stable states) Density is critically important in memories Single NMOS used for reading/writing A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory the area of a 6T is typically one of the top critical parameters of a fabrication technology! EEC 116, B. Baas 7 3

4 SRAM Cell Cross-coupled inverters: a bistable element (two stable states) Density is critically important in memories Single NMOS used for reading/writing A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory EEC 116, B. Baas 8 Retrieved November 17, 2016 Layout: 6-transistor Two 6T SRAM s Small area is everything Wordlines horizontal, bitlines vertical Bitline Bitline_ Wordline0 Wordline1 Gnd Vdd EEC 116, B. Baas 9 4

5 Layout: 6T array Cell array Sense amplifiers and write circuits EEC 116, B. Baas 10 Layout: Memory array 128 words x 36 bits Single-ported 6T SRAM Low-power hierarchical bitline structure Wordline decoders array Sense amplifiers EEC 116, B. Baas 11 5

6 Layout: Memory array Layout issues Cell density is critical Decoder design should probably not use full N-word fanout; predecoding address bits often used Wordline decoders Carefully consider Vdd and Gnd routing array Sense amplifiers EEC 116, B. Baas 12 Memory Array Human hair on a 256 Kbit memory chip EEC 116, B. Baas Source: Helmut Föll 13 6

7 SRAM Operation: Read 1 -> 1 M3 M5 M6 M4 1 -> 0 M1 M2 Bitlines () typically precharged to Vdd Wordline () activated (raised to Vdd in this case) The side of the memory which is at Gnd (0) pulls its bitline from Vdd towards Gnd The sense amplifier detects which bitline s voltage dropped and converts the bit into a standard-value signal EEC 116, B. Baas 14 SRAM Design: Read 1 -> 1 M3 M5 M6 M4 1 -> 0 M1 M2 Data must not be destroyed V must not exceed the threshold of the inverter Assume V remains at V k CC n 4 VCC VCC V M4 in saturation, M2 in linear 2 2 k k n,4 n,2 W L 4 W L 2 V 2 V 2V V V / 4 CC CC TN V CC TN CC kn 2 CC V 2 4 CC VTN EEC 116, B. Baas ,,2 V VCC TN 7

8 SRAM Operation: Write -> 1 M3 M5 M6 M4 -> 0 M1 M2 One bitline driven high, one bitline driven low Wordline activated (driven to Vdd) The bitline driven to Gnd writes the Remember: NMOS transistors pass 1 s poorly Current through M4 overpowers M6, shuts off M5, turns on M1 EEC 116, B. Baas 16 SRAM Design: Write 0 M3 M5 M6 M4 M1 M2 Data must be forced into the V must fall below the threshold of the inverter Assume V remains at k p, 5 V k M3 in linear, M5 in linear CC n,3 V CC V 2 CC VTP VCC VCC VTN VCC W L k 5 n W kp L 3 EEC 116, B. Baas 17 8

9 Multi-ported SRAM Frequently used in register files Classic RISC computers have 1 write and 2 read ports Modern multiple-instruction-issue computers can have many ports (20+ reported) More commonly use single-ended (non-differential) bitlines 2 write ports Memory 4 read ports EEC 116, B. Baas 18 Multi-ported SRAM Example: one write port, two read ports If feedback inverter is not tri-statable during writes, it must be made weak to permit writes, especially a high value (Vdd) on the bitline Write bitline Read bitline 0 Read bitline 1 Write wordline Read wordline 0 Read wordline 1 EEC 116, B. Baas 19 9

10 Layout: Dual-ported memory 10T one-read, one-write port Operates at very low supply voltages read wordline_ write wordline_ Vdd write bitline Vdd Gnd read bitline Gnd write wordline read wordline EEC 116, B. Baas 20 Layout: Dual-ported memory array Eight 10T dualported memory s EEC 116, B. Baas 21 10

11 Layout: Dual-ported memory array 10T one-read, one-write port 16 words x 40 bits write decoder read decoder bitline drivers and EEC 116, B. Baas sense amplifiers 22 DRAM Smaller size (1T ) One transistor to access Often has special structure for capacitor (trench capacitor) that is not available in standard fabrication technologies Single bitline to read and write the memory Must be periodically refreshed Write operation: Wordline at Vdd Bitline value stored on capacitor EEC 116, B. Baas 23 Trench capacitor 11

12 DRAM Classic DRAM High density dedicated DRAM chips typically packaged in DIMMs Top manufacturers include: Samsung (47%), Hynix (26%), Micron (19%), and others. [Source: Statista, for ] Embedded DRAM (edram) DRAM arrays are also available as a process option for standard logic -type CMOS fabrication technologies Ex: IBM 22 nm z Processor CP Microprocessor chip on left: 8 cores, 64MB of edram Level-3 cache, 678 mm2 die area, 4.0 billion transistors, 17 metal layers. edram is used for Level-3 cache and memory controller; and also inside each processor for Level-2 and Branch Target Buffer caches. SC System Controller chip on right: 480 MB of edram Level-4 cache, 678 mm2 die area, 7.1 billion transistors, 15 metal layers [Source: 22nm Next-Generation IBM System z Microprocessor, ISSCC, 2015.] EEC 116, B. Baas 24 DRAM Read operation: Wordline at Vdd Bitline precharged to intermediate voltage level (e.g., Vdd/2) Read bitline voltage is the charge shared result of storage capacitor and bitline capacitance C_ ~ C_bitline / (10-100) ΔV_bitline ~ 250 mv Read is a destructive read and value must be re-written to be read again Circuit challenges: More complex sense amplifiers Many use differential sense amplifier with dummy Higher noise susceptibility Vdd not needed in array EEC 116, B. Baas 25 12

13 Trench Capacitor Deep trench capacitor provides high capacitance per area Example to the right shows a DRAM cross section EEC 116, B. Baas Memory Array Human hair on a 4 Mbit memory chip Note DRAM trench capacitors EEC 116, B. Baas Source: Helmut Föll 27 13

14 ROM Similar to DRAM except the source of the access transistor is tied to Gnd directly For the other value ( 0), the circuit is modified so that nothing happens when goes high. Possibilities include: Omit -Gnd to global-gnd connection Omit source-to-gnd or drain-to-bitline contact Omit poly to contact Omit MOS transistor diffusion Omit transistor entirely In this particular example circuit: A circuit to precharge bitlines is needed but not shown bitline is driven low very strongly when a transistor is present ROMs are typically among the densest of all circuits Keep in mind that sometimes it is more efficient to use synthesized random logic instead of a ROM, especially if the stored data contains patterns and is not truly random Gnd Gnd EEC 116, B. Baas 28 Layout: ROM array 1 transistor s The presence or absence of a transistor s connection determines the stored value EEC 116, B. Baas 29 14

15 Layout: ROM array 256 words x 40 bits Main issue: pitch matching decoders with array ROM s have a very fine pitch! EEC 116, B. Baas 30 Memory Array Red blood s on a 1 Mbit memory chip EEC 116, B. Baas Source: Helmut Föll 31 15