ARCHITECTURE DESIGN FOR SOFT ERRORS

Transcription

1 ARCHITECTURE DESIGN FOR SOFT ERRORS Shubu Mukherjee ^ШВпШшр"* AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO T^"ТГПШГ SAN FRANCISCO SINGAPORE SYDNEY TOKYO ^ P f ^ ^ ELSEVIER Morgan Kaufmann Publishers is an imprint of Elsevier MORGAN KAUFMANN PUBLISHERS

2 Foreword Preface xiii xvii 1 Introduction Overview Evidence of Soft Errors Types of Soft Errors Cost-Eff ective Solutions to Mitigate the Impact of Soft Errors Faults Errors Metrics Dependability Models Reliability Availability Miscellaneous Models Permanent Faults in Complementary Metal Oxide Semiconductor Technology Metal Failure Modes Gate Oxide Failure Modes Radiation-Induced Transient Faults in CMOS Transistors The Alpha Particle The Neutron Interaction of Alpha Particles and Neutrons with Silicon Crystals Architectural Fault Models for Alpha Particle and Neutron Strikes Silent Data Corruption and Detected Unrecoverable Error Basic Definitions: SDC and DUE SDC and DUE Budgets 34 vii

3 viii 1.10 Soft Error Scaling Trends SRAM and Latch Scaling Trends DRAM Scaling Trends Summary Historical Anecdote 39 References 40 2 Device- and Circuit-Level Modeling, Measurement, and Mitigation Overview Modeling Circuit-Level SERs Impact of Alpha Particle or Neutron on Circuit Elements Critical Charge (Qcrit) Timing Vulnerability Factor Masking Effects in Combinatorial Logic Gates Vulnerability of Clock Circuits Measurement Field Data Collection Accelerated Alpha Particle Tests Accelerated Neutron Tests Mitigation Techniques Device Enhancements Circuit Enhancements Summary Historical Anecdote 76 References 76 3 Architectural Vulnerability Analysis Overview AVF Basics Does a Bit Matter? SDC and DUE Equations Bit-Level SDC and DUE FIT Equations Chip-Level SDC and DUE FIT Equations False DUE AVF Case Study: False DUE from Lockstepped Checkers Process-Kill versus System-Kill DUE AVF ACE Principles Types of ACE and Un-ACE Bits Point-of-Strike Model versus Propagated Fault Model 3.6 Microarchitectural Un-ACE Bits Idle or Invalid State Misspeculated State Predictor Structures Ex-ACE State

4 3.7 Architectural Un-ACE Bits NOP Instructions Performance-Enhancing Operations Predicated False Instructions Dynamically Dead Instructions Logical Masking AVF Equations for a Hardware Structure Computing AVF with Little's Law Implications of Little's Law for AVF Computation Computing AVF with a Performance Model Limitations of AVF Analysis with Performance Models ACE Analysis Using the Point-of-Strike Fault Model AVF Results from an Itanium 2 Performance Model ACE Analysis Using the Propagated Fault Model Summary Historical Anecdote 118 References Advanced Architectural Vulnerability Analysis Overview Lifetime Analysis of RAM Arrays Basic Idea of Lifetime Analysis Accounting for Structural Differences in Lifetime Analysis Impact of Working Set Size for Lifetime Analysis Granularity of Lifetime Analysis Computing the DUE AVF Lifetime Analysis of CAM Arrays Handling False-Positive Matches in a CAM Array Handling False-Negative Matches in a CAM Array Effect of Cooldown in Lifetime Analysis AVF Results for Cache, Data Translation Buffer, and Store Buffer Unknown Components RAM Arrays CAM Arrays DUE AVF Computing AVFs Using SFI into an RTL Model Comparison of Fault Injection and ACE Analyses Random Sampling in SFI Determining if an Injected Fault Will Result in an Error Case Study of SFI The Illinois SFI Study SFI Methodology Transient Faults in Pipeline State Transient Faults in Logic Blocks 156

5 4.8 Summary Historical Anecdote 159 References 160 Error Coding Techniques Overview Fault Detection and ECC for State Bits Basics of Error Coding Error Detection Using Parity Codes Single-Error Correction Codes Single-Error Correct Double-Error Detect Code Double-Error Correct Triple-Error Detect Code Cyclic Redundancy Check Error Detection Codes for Execution Units AN Codes Residue Codes Parity Prediction Circuits Implementation Overhead of Error Detection and Correction Codes Number of Logic Levels Overhead in Area Scrubbing Analysis DUE FIT from Temporal Double-Bit Error with No Scrubbing DUE Rate from Temporal Double-Bit Error with Fixed-Interval Scrubbing Detecting False Errors Sources of False DUE Events in a Microprocessor Pipeline Mechanism to Propagate Error Information Distinguishing False Errors from True Errors Hardware Assertions Machine Check Architecture Informing the OS of an Error Recording Information about the Error Isolating the Error Summary Historical Anecdote 205 References 205 Fault Detection via Redundant Execution Overview Sphere of Replication Components of the Sphere of Replication The Size of Sphere of Replication Output Comparison and Input Replication 211

6 XI 6.3 Fault Detection via Cycle-by-Cycle Lockstepping Advantages of Lockstepping Disadvantages of Lockstepping Lockstepping in the Stratus ftserver Lockstepping in the Hewlett-Packard NonStop Himalaya Architecture Lockstepping in the IBM Z-series Processors Fault Detection via RMT RMT in the Marathon Endurance Server RMT in the Hewlett-Packard NonStop Advanced Architecture RMT Within a Single-Processor Core A Simultaneous Multithreaded Processor Design Space for SMT in a Single Core Output Comparison in an SRT Processor Input Replication in an SRT Processor Input Replication of Cached Load Data Two Techniques to Enhance Performance of an SRT Processor Performance Evaluation of an SRT Processor Alternate Single-Core RMT Implementation RMT in a Multicore Architecture DIVA: RMT Using Specialized Checker Processor RMT Enhancements Relaxed Input Replication Relaxed Output Comparison Partial RMT Summary Historical Anecdote 248 References Hardware Error Recovery Overview Classification of Hardware Error Recovery Schemes Reboot Forward Error Recovery Backward Error Recovery Forward Error Recovery Fail-Over Systems DMR with Recovery Triple Modular Redundancy Pair-and-Spare Backward Error Recovery with Fault Detection Before Register Commit Fujitsu SPARC64 V: Parity with Retry IBM Z-Series: Lockstepping with Retry 265

7 XII Simultaneous and Redundantly Threaded Processor with Recovery Chip-Level Redundantly Threaded Processor with Recovery (CRTR) Exposure Reduction via Pipeline Squash Fault Screening with Pipeline Squash and Re-execution Backward Error Recovery with Fault Detection before Memory Commit Incremental Checkpointing Using a History Buffer Periodic Checkpointing with Fingerprinting Backward Error Recovery with Fault Detection before I/O Commit LVQ-Based Recovery in an SRT Processor Re Vive: Backward Error Recovery Using Global Checkpoints SafetyNet: Backward Error Recovery Using Local Checkpoints Backward Error Recovery with Fault Detection after I/O Commit Summary Historical Anecdote 294 References Software Detection and Recovery Overview Fault Detection Using SIS Fault Detection Using Software RMT Error Detection by Duplicated Instructions Software-Implemented Fault Tolerance Configurable Transient Fault Detection via Dynamic Binary Translation Fault Detection Using Hybrid RMT CRAFT: A Hybrid RMT Implementation CRAFT Evaluation Fault Detection Using RVMs Application-Level Recovery Forward Error Recovery Using Software RMT and AN Codes for? auist Detection Log-Based Backward Error Recovery in Database Systems Checkpoint-Based Backward Error Recovery for Shared-Memory Programs OS-Level and VMM-Level Recoveries Summary 323 References 324 Index 327