Table of Contents List of Figures... 2 List of Tables Introduction Main features Function description On-chip Flash memo

Size: px

Start display at page:

Download "Table of Contents List of Figures... 2 List of Tables Introduction Main features Function description On-chip Flash memo"

Elfreda Newton
6 years ago
Views:

1 GigaDevice Semiconductor Inc. GD32F103xx ARM 32-bit Cortex -M3 MCU Application Note AN002

2 Table of Contents List of Figures... 2 List of Tables Introduction Main features Function description On-chip Flash memory Reading the Flash memory Programming the Flash memory Erasing the Flash memory Option bytes features Page protection Registers Flash FMCU flag register (FLASH_FMCUFR) Flash option byte flag register (FLASH_OBFR) Flash operation status register (FLASH_OSR) Flash operation control register (FLASH_OCR) Flash target address register (FLASH_TAR) Flash option byte status register (FLASH_OBSR) Flash write protection register (FLASH_WPTR) Revision history / 17

3 List of Figures Figure 1. Flash module organization... 5 Figure 2. Flash programming flowchart... 7 Figure 3. Flash page erase operation flowchart... 8 Figure 4. Flash mass erase operation flowchart / 17

4 List of Tables Table 1. Flash module organization... 5 Table 2. Boot modes... 5 Table 3. Option bytes memory map... 9 Table 4. Revision history / 17

5 1 Introduction The Flash Memory Control Unit (FMCU) provides the on-chip Flash memory of GD32F103xx device with all the necessary functions for routinely updated and re-programmed. Benefit from the Flash technology and innovative system architecture, the CPU waiting time which will cause CPU instruction execution delays has been eliminated and realized zero wait. Flash Memory operation as half-word program and word page erase functions are also described in this document. 2 Main features Up to 128 KB of on-chip Flash memory (128 pages, each page size of 1KB) for storing instruction/data and options Page read accesses can be performed 32 bits per cycle with zero wait state Page erase and mass erase capability Half-word (16 bits) program Interrupt function to indicate end of flash memory operations or an error occurs Page erase/program protection functions to prevent unwilling read/write operations on the Flash memory. 3 Function description 3.1 On-chip Flash memory The GD32F103xx series of devices provide up to 128 KB of on-chip flash memory. Read accesses can be performed 32 bits per cycle without any wait state. Besides, all of byte, half-word (16 bits) and word (32 bits) read accesses are supported. The flash memory can be programmed half-word (16 bits) or word (32 bits) at a time. Each page of the flash memory can be erased individually. The whole flash memory space except information blocks can be erased at a time. A data storage or firmware upgrade can be implemented using several methods such as In System Programming (ISP), In Application Programming (IAP) or In Circuit Programming (ICP). The following figure is the Flash memory map of the GD32F103xx in which the address ranges from 0x to 0x1FFF FFFF (0.5 GB). The address from 0x1FFF F000 to 0x1FFF F7FF as system memory is mapped to the boot loader block with a capacity of 2 KB. Additionally, the region addressed from 0x1FFF F800 to 0x1FFF F80F is the option bytes with a capacity of 16 B. The memory organization mapping view is shown as below. 4 / 17

6 Figure 1. Flash module organization 0x1FFF FFFF 0x1FFF F80F 0x1FFF F800 0x1FFF F000 Reserved Option Bytes System memory Reserved 0x0801 FFFF 0x x Flash memory Aliased to Flash or system memory by BOOT pins configuration The flash memory consists of up to 128 KB main flash organized into 128 pages with 1 KB capacity per page and a 2 KB information block for the boot loader. The following table shows details. Table 1. Flash module organization Block Name Address Size Page 0 0x x FF 1 Kbytes Page 1 0x x FF 1 Kbytes Main Flash Block Page 2 0x x0800 0BFF 1 Kbytes Page 127 0x0801 FC00-0x0801 FFFF 1 Kbytes Information Block System memory 0x1FFF F000-0x1FFF F7FF 2 Kbytes Option Bytes 0x1FFF F800-0x1FFF F80F 16 bytes The GD32F103xx provides three kinds of boot sources which can be selected using the BOOT1 and BOOT0 pins. The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after a power-on reset or a system reset to select the required boot source. The details are shown in the following table. Table 2. Boot modes Boot mode selection pins Selected boot source Boot1 Boot0 Main Flash Memory x 0 System Memory 0 1 On-chip SRAM / 17

7 After power-on sequence or a system reset, the ARM Cortex -M3 processor fetches the top-of-stack value from address 0x and the base address of boot code from 0x in sequence. Then, it starts executing code from the base address of boot code. Due to the selected boot source, either the main flash memory (original memory space beginning at 0x ) or the system memory (original memory space beginning at 0x1FFF F000) is aliased in the boot memory space which begins at the address 0x When the on-chip SRAM whose memory space is beginning at 0x is selected as the boot source, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register. The embedded boot loader is located in the system memory, which is used to reprogram the Flash memory. In GD32F103xx devices, the boot loader can be activated through the USART1 interface. 3.2 Reading the Flash memory The Flash memory access is performed through the AHB bus and can be addressed directly. Reading operation accesses the requested data of the content of the Flash memory by steps of read sequence, which under control of the hardware read interface in FMCU. 3.3 Programming the Flash memory After system reset, the FMCU function is protected. There needs an unlocking sequence to write value into FLAG1 and FLAG2 of the FLASH_FMCUFR register to enable the FMCU function and access the FLASH_OCR register. The GD32F103xx provides a half-word (16 bits) programming function which is used to modify the Flash memory contents at a time. The following steps show the half word programming operation register access sequence. Check the BUSY bit in the FLASH_OSR register to confirm that no Flash memory operation is in progress. Set the PG bit in the FLASH_OCR register to write the page program command Write the half-word (16 bits) data to the target address Wait until the operations have been completed by checking the reset of the BUSY bit in the FLASH_OSR register Read and verify the programmed page 6 / 17

8 Figure 2. Flash programming flowchart START Is BUSY equal to 1? No Set PG=1 to send command Write half-word data to addr Is BUSY equal to 1? No Read and verify 3.3 Erasing the Flash memory Page erase A page of the Flash memory can be erased using the Page Erase feature of the FMCU. Each page can be erased independently without affecting the contents of other pages. The following steps show the access sequence of the register for a page erase operation. Check the BUSY bit in the FLASH_OSR register to confirm that no Flash memory operation is in progress. Set the PER bit in the FLASH_OCR register to write the page erase command Write the FLASH_TAR register to select page of which to be erased Set the START bit in the FLASH_OCR register to trigger the erase operation Wait until the operations have been completed by checking the reset of the BSY bit in the FLASH_OCR register Read and verify the erased page 7 / 17

9 Figure 3. Flash page erase operation flowchart START Is BUSY equal to 1? No Set PER=1 to send command Write Addr to select page Set START=1 to start page rease Is BUSY equal to 1? No Read and verify Mass erase The user pages of the Flash memory can also be completely erase using the mass erase function. The following steps show the mass erase register access sequence. Check the BUSY bit in the FLASH_OSR register to confirm that no Flash memory operation is in progress. Set the MER bit in the FLASH_OCR register to write the mass erase command Set the START bit in the FLASH_OCR register to trigger the erase operation Wait until the operations have been completed by checking the reset of the BSY bit in the FLASH_OCR register Read and verify the erased page 8 / 17

10 Figure 4. Flash mass erase operation flowchart START Is BUSY equal to 1? No Set MER=1 to send command Set START=1 to start page rease Is BUSY equal to 1? No Read and verify 3.4 Option bytes features The option byte block can be treated as an independent Flash memory in which the base address is 0x1FFF F800. The following table shows the functional description and the memory map of the option byte. Table 3. Option bytes memory map Address Fields Option Bytes Description Bit [31:24] nuser User option byte (stored in FLASH_OBSR[9:2]) Bit [23:16] USER Bit 18 nrst_stdby 0: Reset when entering Standby mode. 1: No reset. 0x1FFF 0: Reset when entering deep-sleep mode Bit17 nrst_dslep F800 1: No reset. Bit 16 WDG_SW 0: Hardware watchdog 1: Software watchdog Bits [15:8] nrdp Bits [7:0] RDP Read protection option byte Bits [31:24]: ndata1 For user data storage. 0x1FFF Bits [23:16]: Data1 (stored in FLASH_OBSR[25:18]) F804 Bits [15:8]: ndata0 For user data storage. Bits [7:0]: Data0 (stored in FLASH_OBSR[17:10]) 9 / 17

11 0x1FFF F808 0x1FFF F80C Bits [31:24]: Bits [23:16]: Bits [15:8]: Bits [7:0]: Bits [31:24]: Bits [23:16]: Bits [15:8]: Bits [7:0]: nwrp1 WRP1 nwrp0 WRP0 nwrp3 WRP3 nwrp2 WRP2 Flash memory write protection option bytes (stored in FLASH_WPTR[15:8]) Use 1 bit to protect 4 pages of 1 Kbyte in main memory block, that can protects pages 32 to 63 0: Write protection active 1: Write protection not active Flash memory write protection option bytes (stored in FLASH_WPTR[7:0]) Use 1 bit to protect 4 pages of 1 Kbyte in main memory block, that can protects pages 0 to 31 0: Write protection active 1: Write protection not active Flash memory write protection option bytes (stored in FLASH_WPTR[31:24]) Use 1 bit to protect 4 pages of 1 Kbyte in main memory block, that can protects pages 96 to 127 0: Write protection active 1: Write protection not active Flash memory write protection option bytes (stored in FLASH_WPTR[23:16]) Use 1 bit to protect 4 pages of 1 Kbyte in main memory block, that can protects pages 64 to 95 0: Write protection active 1: Write protection not active 3.5 Page protection The GD32F103xx provides page erase/program protection functions to prevent unwilling read/write operations on the Flash memory Read protection Read protection is enabled by setting the RDP option byte and need a power on reset to reload the new RDP option byte after that. Read protection is disabled by erasing the entire option byte area and program the correct RDP code 0x00A5 to the unprotect memory, then need a power on reset to reload the new RDP option byte after that Write protection Write protection is enabled by configuring the WRP[3:0] option bytes, and need a power on reset to reload the new WRPx option bytes after that. Write protection is disabled by erasing the entire option byte area using the OBER bit in the FLASH_OCR register and program the correct RDP code 0x00A5 to the unprotect memory, 10 / 17

12 then need a power on reset to reload the new WDPx option byte after that. 4 Registers 4.1 Flash FMCU flag register (FLASH_FMCUFR) Address offset: 0x04 Reset value: xxxx xxxx FMCUFR[31:16] w w w w w w w W w w w w w w w w FMCUFR[15:0] w w w w w w w w w w w w w w w w Bits Fields Descriptions 31:0 FMCUFR FMCU flag These bits map to the flags for FMCU unlocking. 4.2 Flash option byte flag register (FLASH_OBFR) Address offset: 0x08 Reset value: xxxx xxxx OBFR[31:16] w w w w w w W w w w w w w w w w OBFR[15:0] w w w w w w w w w w w w w w w w Bits Fields Descriptions 31:0 OBFR Option byte flag These bits represent the flags to unlock the OPTWR 4.3 Flash operation status register (FLASH_OSR) Address offset: 0x0C Reset value: 0x / 17

13 Reserved Reserved EOP WPT ERR Res. PG ERR Res. BUSY rw rw rw r Bits Fields Descriptions 31:6 Reserved must be kept cleared 5 EOP End of operation, set by hardware when programming / erase is completed. Reset by writing 1. 4 WPTERR Set by hardware when programming a write-protected address of the Flash memory. Reset by writing 1. 3 Reserved must be kept cleared 2 PGERR Programming error. Set by hardware when an address to be programmed contains a value different from '0xFFFF' before programming. Reset by writing 1. 1 Reserved must be kept cleared 0 BUSY Busy. Represent Flash operation is in progress. 4.4 Flash operation control register (FLASH_OCR) Address offset: 0x10 Reset value: 0x Reserved Reserved EOPIE Res. ERRIE OBWE Res. LCK START OBER OBPG Res. MER PER PG rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31:13 Reserved must be kept cleared 12 EOPIE End of operation interrupt enable, when the EOP bit in FLASH_OSR register goes to 1. 0: Interrupt disabled 1: Interrupt enabled 11 Reserved must be kept cleared 10 ERRIE Error interrupt enable on an FMCU error (when PGERR / WPTERR are set in the FLASH_OSR register). 0: Interrupt disabled 1: Interrupt enabled 9 OBWE Option bytes write enable 12 / 17

14 1: option bytes can be programmed. Set on writing the correct key sequence to the FLASH_OBFR register. 8 Reserved must be kept cleared 7 LCK Lock Set to 1 to indicate that the FMCU and FLASH_OCR are locked. Reset by hardware after detecting the unlock sequence. 6 START Start. Set to 1 to trigger an ERASE operation. Set only by software and reset when the BSY bit is reset. 5 OBER Option byte erase 1: Option byte erase enable. 4 OBPG Option byte programming 1: Option byte programming enable. 3 Reversed must be kept cleared. 2 MER Mass erase 1: Mass erase enable. 1 PER Page erase 1: Page Erase enable. 0 PG Programming 1: Flash programming enable. 4.5 Flash target address register (FLASH_TAR) Address offset: 0x14 Reset value: 0x FTAR[31:16] w w w w w w w w w w w w w w w w FTAR[15:0] w w w w w w w w w w w w w w w w Bits Fields Descriptions 31:0 FTAR Flash target address The target address to program when using programming, or a page to erase when using page erase. 13 / 17

15 4.6 Flash option byte status register (FLASH_OBSR) Address offset 0x1C Reset value: 0x03FF FFFC Reversed Data1 Data0 r r r r r r r r r r Data0 Reserved nrst_ STDBY nrst_ STOP r r r r r r r r r r r r r r r r WDG SW RPT OBERR Bits Fields Descriptions 31:25 Reserved must be kept cleared 25:18 Data1 User data 17:10 Data0 User data 9:5 Reversed must be kept cleared 5:2 USER User option bytes, loaded by the OBL, including: Bit 4: nrst_stdby Bit 3: nrst_stop Bit 2: WDGSW 1 RPT Read protection 0: read protection disable 1: read protection enable 0 OBERR Option byte error 1: the loaded option byte error, read as 0xFF in the FLASH_OBSR or FLASH_WPTR register. 4.7 Flash write protection register (FLASH_WPTR) Address offset: 0x20 Reset value: 0xFFFF FFFF WPT[31:16] r r r r r r r r r r r r r r r r WPT[15:0] r r r r r r r r r r r r r r r r 14 / 17

16 Bits Fields Descriptions 31:0 WPT Write protection option bytes, loaded by the OBL 0: Write protection enable 1: Write protection disable 15 / 17

17 5 Revision history Table 4. Revision history Revision No. Description Date 1.0 Initial Release Mar.8, / 17

PM0063 Programming manual

PM0063 Programming manual Programming manual STM32F100xx value line Flash programming Introduction This programming manual describes how to program the Flash memory of low-density (STM32F100x4, STM32F100x6), medium-density STM32F100xx