C66x KeyStone Training HyperLink

Transcription

1 C66x KeyStone Training HyperLink

2 1. HyperLink Overview 2. Address Translation 3. Configuration 4. Example and Demo Agenda

3 1. HyperLink Overview 2. Address Translation 3. Configuration 4. Example and Demo Agenda

4 U A R T S P I S p e c i f i c I / O O t h e r s 2 x2 S w i t c h S w i t c h HyperLink Bus Memory Subsystem 64-Bit DDR3 EMIF Debug & Trace Boot ROM Semaphore Power Management PLL EDMA HyperLink x3 x3 I C P C I e x2 MSM SRAM MSMC C66x CorePac L1 P-Cache L2 Cache 1 to 8 up to 1.25 GHz TeraNet L1 D-Cache A p p l i c a t i o n - S R I O x4 E t h e r n e t S G M I I Application-Specific Coprocessors Multicore Navigator Queue Manager Packet DMA Security Accelerator Packet Accelerator Network Coprocessor CorePac & Memory Subsystem Memory Expansion Multicore Navigator Network Coprocessor External Interfaces TeraNet Switch Fabric Diagnostic Enhancements HyperLink Bus Provides the capability to expand the C66x to include hardware acceleration or other auxiliary processors Four lanes with up to 12.5 Gbaud per lane

5 HyperLink in KeyStone 32 Queue Pending Signals 32 Secondary Events from CP_INTC Core 0 Core 1 Core 2 Core 3 DDR MSMC EDMA0 Teranet SCR_2_A Clk/2 256bit HyperLink SRIO Wireless Application Accelerators PCIe MMR PA Teranet SCR_3_A Clk/3 128bit QMSS EDMA1 EDMA2 L2

6 HyperLink Advantages Expands internal bus across chip boundaries Fast (50 Gbaud) Low power (50+% saving compared to other serial interfaces) Low latency Industry standard SerDes Future support for FPGA Many use cases Remote access of accelerators Expand processing capability by adding 4 or 8 cores KeyStone Reduce system power by disabling I/O, accelerators on remote device C6678 KeyStone TCI Cortex A8 4 DSP cores HyperLink HyperLink KeyStone C6678 Remote Lower Power Scalable Processing Expansion KeyStone C DSP cores

7 HyperLink External Interfaces Device A Device B TeraNet SCR HyperLink TX RX PM 1 or 4 SerDes Lanes FL PM 1 or 4 SerDes Lanes FL RX TX HyperLink TeraNet SCR Sideband: LVCMOS signal for control Dedicated control for each direction Flow Control (FL) and Power Management (PM) Data: SerDes: 1 or 4 lanes Supports up to 12.5 GBaud per lane

8 HyperLink External Interfaces Device A Device B TeraNet SCR HyperLink TX RX PM 1 or 4 SerDes Lanes FL PM 1 or 4 SerDes Lanes FL RX TX HyperLink TeraNet SCR Sideband: LVCMOS signal for control Dedicated control for each direction Flow Control (FL) and Power Management (PM) Data: SerDes: 1 or 4 lanes Supports up to 12.5 GBaud per lane NOTE: The PM and FL are transparent to the user after setting the registers.

9 Packet-Based Transfer Protocol Four read/write transactions Write Request / Data Packet Optional Write Response Packet Read Request Packet Read Response Data Packet Interrupt Request Packet passes event to remote side Multiple outstanding transactions 8 byte packet header (currently up to 64 bytes) 8b/9b error correction

10 HyperLink Functionality From the user point of view: Access remote device memory Ability to write to remote device memory Ability to read from remote device memory Ability to generate event / interrupt in the remote device

11 Example Core 0 Core 4 Core 0 Core 4 Local L2 Local L2 Local L2 Local L2 of Core 1 Core 5 Core 1 Core 5 HyperLink Local L2 Core 2 Local L2 Core 6 Local L2 Core 2 Local L2 Core 6 Use Case Local L2 Local L2 Local L2 Local L2 Core 3 Core 7 Core 3 Core 7 Local L2 Local L2 Local L2 Local L2 Shared L2 Shared L2 SRIO Queue Manager HyperLink HyperLink Queue Manager Packet Accelerator SGMII DDR3 Device A Device B 16 bit wide DDR3 16 bit wide DDR3

12 HyperLink Model Core N Local L2 Core N Local L2 DDR HyperLink Window 0x FFFFFFF (256MB) HyperLink Device A Device B Device B (local/tx) can see up to 256MB of Device A (remote/rx) memory: Available memory can be divided up to 64 distinct segments. All segments are the same size (local perspective). Segment size range is 256B to 256MB. All segments are aligned to 128KB boundaries.

13 HyperLink Interrupts Features Detection - detected an interrupt to the HyperLink local device that was generated either as software interrupt (writing to interrupt register) or as hardware Forward generate an interrupt packet and send it to the remote unit Mapping receive an interrupt packet from the remote and forward it to the configure location in the local device Generating generate an interrupt in the local device

14 1. HyperLink Overview 2. Address Translation 3. Configuration 4. Example and Demo Agenda

15 Segmentation The total visible window is 256MB. The application can define up to 64 segments. The segment size on the remote side is 256B to 256MB. All segments are aligned on 17 bits alignment. On the local side, the HyperLink memory is between 0x4000_0000 to 0x4FFF_FFFF. On the remote side, the HyperLink memory address range is device dependent, but is typically 0x0000_0000 to 0xFFFF_FFFF. How is the local address (0x4XXX XXXX) translated to the remote address?

16 Offset Into a Segment Largest Segment Size in Bytes (Power of 2) Number of Bits For Offset Maximum Number of Segments Number of Bits Needed to Choose Segment 256M M M M M K

17 What Does Translation Involve? Translation process inputs on the local/transmit side: bits of remote address (the upper 4 bits are 0x4) 2. Privilege ID Process information sent from the local to the remote/receive side: 1. Lower portion of the remote address offset into the segment 2. Segment Index 3. Privilege ID Translation process outputs on the remote/receive side: 1. Complete remote address 2. Privilege ID

18 Segment Lookup Table (Rx) The Segment Lookup Table is internal to the HyperLink and is not memory mapped. Each segment has a row: o 64 rows o information in each line 16 bits are the MSB Segment Base Address 5 bits are the Remote Segment Size (defines what mask is used when calculating the offset into the segment) The application loads the table row-by-row (segment-by-segment): o First, the Segment Base Address and segment size is written to register Rx Address Segment Value (base address + 0x3c) hyplnkrxsegidxreg_s o Then the Segment Number is written to register Rx Address Segment Index (base + 0x38) hyplnkrxsegvalreg_s During the translation process, the Segment Index is extracted from the upper bits of the local HyperLink address.

19 Low Level Driver Data Structures Here are the data structures with brief descriptions: hyplnkchipverreg_s hyplnkcontrolreg_s hyplnkeccerrorsreg_s hyplnkgensoftintreg_s hyplnkintctrlidxreg_s hyplnkintctrlvalreg_s hyplnkintpendsetreg_s hyplnkintprivecreg_s hyplnkintptridxreg_s hyplnkintptrvalreg_s hyplnkintstatusclrreg_s hyplnklanepwrmgmtreg_s hyplnklinkstatusreg_s hyplnkregisters_s hyplnkrevreg_s hyplnkrxaddrselreg_s hyplnkrxprivididxreg_s hyplnkrxprividvalreg_s hyplnkrxsegidxreg_s hyplnkrxsegvalreg_s hyplnkserdescontrol1reg_s hyplnkserdescontrol2reg_s hyplnkserdescontrol3reg_s hyplnkserdescontrol4reg_s hyplnkstatusreg_s hyplnktxaddrovlyreg_s Specification of the Chip Version Register Specification of the HyperLink Control Register Specification of the ECC Error Counters Register Specification of the HyperLink Generate Soft Interrupt Value Register Specification of the Interupt Control Index Register Specification of the Interrupt Control Value Register Specification of the HyperLink Interrupt Pending/Set Register Specification of the HyperLink Interrupt Priority Vector Status/Clear Register Specification of the Interupt Control Index Register Specification of the Interrupt Control Value Register Specification of the HyperLink Interrupt Status/Clear Register Specification of the Lane Power Management Control Register Specification of the Link Status Register Specification all registers Specification of the HyperLink Revision Register Specification of the Rx Address Selector Control Register Specification of the Rx Address PrivID Index Register Specification of the Rx Address PrivID Value Register Specification of the Rx Address Segment Index Register Specification of the Rx Address Segment Value Register Specification of the SerDes Control And Status 1 Register Specification of the SerDes Control And Status 2 Register Specification of the SerDes Control And Status 3 Register Specification of the SerDes Control And Status 4 Register Specification of the HyperLink Status Register Specification of the Tx Address Overlay Control Register

20 Example LLD: Write Multiple Registers

21 Building the Segment Lookup Table Build on the receive side for the transmit side specifications Here is one simple procedure for building the Segment Lookup Table: 1. Determine the maximum segment size that can be used (Power of 2), where N = The number of bits needed to address into the segment. 2. Calculate the number of bits needed for the segments (but no more than 6). 3. For each segment, load the base address and the remote segment size into the appropriate row of the table. The base address is chosen so that N LSB are all zeros. Only the upper 16 bits are written into the table. 4. If the number of segments is not Power of 2, add rows to complete to Power of 2 with empty segments (Size 0).

22 Table 3-14 Rx Address Segment Value Register Field Descriptions If rxlen_val = 16, the segment size is 0x00002_0000 If rxlen_val = 17, the segment size is 0x00004_0000 If rxlen_val = 18, the segment size is 0x00008_0000 If rxlen_val = 19, the segment size is 0x00010_0000 If rxlen_val = 20, the segment size is 0x00020_0000 If rxlen_val = 21, the segment size is 0x00040_0000 If rxlen_val = 22, the segment size is 0x00080_0000 If rxlen_val = 23, the segment size is 0x00100_0000 If rxlen_val = 24, the segment size is 0x00200_0000 If rxlen_val = 25, the segment size is 0x00400_0000 If rxlen_val = 26, the segment size is 0x00800_0000 If rxlen_val = 27, the segment size is 0x01000_0000 Segment Lookup Table: Example 1 Show the remote DDR addresses between 0x8000_0000 and 0x8FFF_FFFF (addressed in one consecutive 256MB segment): 28-bit offset 0 bits for choosing the segment (only one segment) One row in Segment Lookup Table 0x8000 Size 27 (size 0x01000_0000 = 256MB and the offset mask will be 0xfff_ffff)

23 Segment Lookup Table: Example 2 8 segments Each segment of size 0x0100_0000 (16MB) Addresses start at 0x8000_0000, 0x8200_0000, 0x8400_0000, and continue up to 0x8E00_0000 The maximum size is 16MB. That is, 24 bits. 3 bits to choose the segment (8 segments). Row 0 0x8000_0000 Size 23 Row 1 0x8200_0000 Size 23 Row 2 0x8400_0000 Size 23 Row 3 0x8600_0000 Size 23 Row 4 0x8800_0000 Size 23 Row 5 0x8A00_0000 Size 23 Row 6 0x8C00_0000 Size 23 Row 7 0x8E00_0000 Size 23 Size 23 = 0x = 16MB and the mask that will be used is 0x000f ffff

24 Segment Lookup Table: Example 3 8 segments 7 each of size 0x0100_0000 (16MB) Addresses start at 0x8000_0000, 0x8100_0000, 0x8200_0000, and continue up to 0x8600_0000. The last segment is 32MB starting at address 0x8700_0000. The maximum size is 32MB. That is, 25 bits. 3 bits to choose the segment (8 segments) Row 0 0x8000_0000 Size 23 Row 1 0x8100_0000 Size 23 Row 2 0x8200_0000 Size 23 Row 3 0x8300_0000 Size 23 Row 4 0x8400_0000 Size 23 Row 5 0x8500_0000 Size 23 Row 6 0x8600_0000 Size 23 Row 7 0x8700 _0000 Size 24

25 Segment Lookup Table: Example 4 9 segments The first segment is the MSMC (4MB = 22 bits). The next 8 segments are L2 memory of each core (512KB = 19 bits). The maximum size is 4MB. That is, 22 bits. 6 bits to choose the segment (64 segments) Row 0 0x0C00_0000 Size 21 (4MB) Row 1 0x1080_0000 Size 18 (512KB) Row 2 0x1180_0000 Size 18 Row 3 0x1280_0000 Size 18 Row 4 0x1380_0000 Size 18 Row 5 0x1480_0000 Size 18 Row 6 0x1580_0000 Size 18 Row 7 0x1680_0000 Size 18 Row 8 0x1780_0000 Size 18 Row 9 0x0000_0000 Size 0 (0) Row 10 0x0000_0000 Size 0 and so on to Row 15.

26 On the Local/Transmit Side Information included in the Address Word: Offset into Segment Segment Index Privilege ID Value Tx Address Overlay Control Register (base + 0x1c) controls the overlay of the Privilege ID. The Privilege ID lookup Table has 16 rows and is loaded using two registers: Rx address PrivID Index > base + 0x30 hyplnkrxprivididxreg_s Rx Address PrivID Value -> base + 0x34 hyplnkrxprividvalreg_s

27 Local/Tx Side: Example The Tx Address Overlay Control Register (base + 0x1c) controls the overlay of the Privilege ID index. hyplnktxaddrovlyreg_s Agreed values for the HyperLink Privilege Index: 13 (0xD) if the request comes from a core 14 (0xE) if the request initiated from another master Tx Address information bits 0 to 27, depends on the value of txigmask Privilege Index bits txigmask = Determine what address bits will be sent to the remote side: 11 mask 0x0FFF_FFFF,10 0x07FF_FFFF 8 0x01FF_FFFF, 0 0x0001_FFFF Tx Address Overlay Control Register is shown below Reserved txsecovl Reserved Txpriviovl Reserved txigmask R R/W R R/W R R/W For other possible configurations, refer to the HyperLink User Guide.

28 On the Remote/Receive Side Five registers control the behavior of the remote/receive side: 1. Rx Address Selector Control (base + 0x2c) controls how the address word is decoded; hyplnkrxaddrselreg_s 2. Rx Address PrivID Index (base + 0x30) is used to build the Privilege Lookup Table; hyplnkrxprivididxreg_s 3. Rx Address PrivID Value (base + 0x34) is used to build the Privilege Lookup Table; hyplnkrxprividvalreg_s 4. Rx Address Segment Index (base + 0x38) is used to build the Segment Lookup Table; hyplnkrxsegidxreg_s 5. Rx Address Segment Value (base + 0x3c) is used to build the Segment Lookup Table; hyplnkrxsegvalreg_s

29 Remote/Rx Side: Example Rx Address Selector Control (base + 0x2c; hyplnkrxaddrselreg_s) controls how the receiver decodes: Location in the address word and value of security bit (not used) Location in the address word of Privilege Index. Location in the address word of the index into segment lookup table The mask that is used for extracting the offset rxprividsel = 12 (bits 28-31) rxsegsel depends on the maximum segment size: 12 mask 0x0FFF_FFFF, 10 0x03FF_FFFF, 8 0x00FF_FFFF, 1 0x0001_FFFF The Rx Address Selector Control register is shown below Reserved rxsechi rxseclo Reserved rxsecsel Reserved rxprividsel Reserved rxsegsel R R/W R/W R R/W R R/W R R/W For other possible configurations, refer to the HyperLink User Guide.

30 Remote (Rx) Address Examples Building upon each of the prior examples, this section demonstrates how to calculate the address value that is sent to the remote/receive side. The local address is 0x4567_89a0 Assume Privilege ID 0xD (request from a core) was loaded to Index 5 (0101) in the PrivID table. The address sent to the other side is 0x5567_89a0. What address is accessed in the remote side?

31 Segment Lookup Table: Example 1 Show the remote DDR addresses between 0x8000_0000 and 0x8FFF_FFFF (addressed in one consecutive 256MB segment): 28-bit offset 0 bits for choosing the segment (only one segment) One row in Segment Lookup Table 0x8000 Size 27 (size 0x1000_0000 = 256MB)

32 Remote (Rx) Address: Example 1 Show the remote DDR addresses between 0x8000_0000 and 0x8FFF_FFFF (addressed in one consecutive 256MB Segment): 28 bit offset - 0x a0 Bits x0101 = 5 txigmask = 11 mask 0x0FFF_FFFF Address sent to the receive/remote side = 0x5567_89a0 On the receive side, the address is 0x8000_ x0567_89a0 = 0x8567_89a0 (Segment size = 28 -> offset mask = 0x0fff ffff Bit 31:28 as privid index=0b0101 Received address 0x5567_89A PrivID Mapping Table No bit for segment select, goes to Row Segment Value 0x8000_0000 Mask/Length 0x0FFF_FFFF PrivID = 13 Output address = 0x8000_0000+0x5567_89A0 & 0x0FFF_FFFF =0x8567_89A0

33 Segment Lookup Table: Example 2 8 segments Each segment of size 0x0100_0000 (16MB) Addresses start at 0x8000_0000, 0x8200_0000, 0x8400_0000, and continue up to 0x8E00_0000 The maximum size is 16MB. That is, 24 bits. 3 bits to choose the segment (8 segments). Row 0 0x8000_0000 Size 23 Row 1 0x8200_0000 Size 23 Row 2 0x8400_0000 Size 23 Row 3 0x8600_0000 Size 23 Row 4 0x8800_0000 Size 23 Row 5 0x8A00_0000 Size 23 Row 6 0x8C00_0000 Size 23 Row 7 0x8E00_0000 Size 23 Size 23 = 0x = 16MB

34 Remote (Rx) Address: Example 2 8 segments, each segment of size 0x0100_0000 (16M) Addresses start at 0x8000_0000, 0x8200_0000, 0x8400_0000, to 0x8E00_ bits offset 0x067_89a0 Segment number 0101 = 5 Row 5 0x8A00_0000 Size 23 (mask = 0x00ff ffff) On the receive side, the address is 0x8A00_ x0067_89A0 = 0x8A67_89A0 Bit 31:28 as privid index=0b0101 Received address 0x5567_89A PrivID Mapping Table Bit for segment Value 010 = Segment Value 0x8000_0000 0x8A00_0000 Mask/Length 0x00FF_FFFF 0x00FF_FFFF PrivID = 13 Output address = 0x8A00_0000+0x5567_89A0 & 0x00FF_FFFF = 0x8A67_89A0

35 Segment Lookup Table: Example 3 8 segments 7 each of size 0x0100_0000 (16MB) Addresses start at 0x8000_0000, 0x8100_0000, 0x8200_0000, and continue up to 0x8600_0000. The last segment is 32MB starting at address 0x8700_0000. The maximum size is 32MB. That is, 25 bits. 3 bits to choose the segment (8 segments) Row 0 0x8000_0000 Size 23 Row 1 0x8100_0000 Size 23 Row 2 0x8200_0000 Size 23 Row 3 0x8300_0000 Size 23 Row 4 0x8400_0000 Size 23 Row 5 0x8500_0000 Size 23 Row 6 0x8600_0000 Size 23 Row 7 0x8700 _0000 Size 24

36 Remote (Rx) Address: Example 3 8 segments, 7 each of size 0x0100_0000 (16M) Addresses start at 0x8000_0000, 0x8100_0000, 0x8200_0000, to 0x8600_0000. For 8 segments, the maximum size is 32M. That is, 25 bits. 25 bits offset, 3 bits segment number 010 = 2 Row 2 0x8200_0000 Size 23 (mask = 0x00ff ffff) On the receive side, the address is 0x8200_ x0067_89A0 = 0x8267_89A0 Bit 31:28 as privid index=0b0101 Received address 0x5567_89A PrivID Mapping Table Bit for segment Value 010 = Segment Value 0x8000_0000 0x8200_0000 0x Mask/Length 0x00FF_FFFF 0x00FF_FFFF 0x01ff ffff PrivID = 13 Output address = 0x8200_0000+0x556789a0 & 0x00FF_FFFF = 0x8267_89A0

37 Segment Lookup Table: Example 4 9 segments The first segment is the MSMC (4MB = 22 bits). The next 8 segments are L2 memory of each core (512KB = 19 bits). The maximum size is 4MB. That is, 22 bits. 6 bits to choose the segment (64 segments) Row 0 0x0C00_0000 Size 21 (4MB) Row 1 0x1080_0000 Size 18 (512KB) Row 2 0x1180_0000 Size 18 Row 3 0x1280_0000 Size 18 Row 4 0x1380_0000 Size 18 Row 5 0x1480_0000 Size 18 Row 6 0x1580_0000 Size 18 Row 7 0x1680_0000 Size 18 Row 8 0x1780_0000 Size 18 Row 9 0x0000_0000 Size 0 (0) Row 10 0x0000_0000 Size 0 and so on to Row 15.

38 Remote (Rx) Address: Example 4 9 segments The first 8 segments are L2 memory of each core (512K = 19 bits). The 9th segment is the MSMC (4M = 22 bits). The maximum size is 4M. That is, 22 bits. 6 bits to choose the segment (64 segments) 22 bits offset Segment number = 21???? Row 5 0x Size 18 On the receive side, the address is 0x x a0 = 0x a0 (L2 memory of Core 4) Bit 31:28 as privid index=0b0101 Received address 0x a PrivID Mapping Table Bit for segment Value = Segment value 0x0c x x Mask/length 0x003f ffff 0x0007 FFFF 0x0007 FFFF PrivID = 13 Output address = 0x1480_0000+0x556789a0 & 0x0007_FFFF =0x A0

39 1. HyperLink Overview 2. Address Translation 3. Configuration 4. Examples and Demo Agenda

40 Chip Level Configuration 1. Enable power domain for peripherals using CSL routines. Enabling power to peripherals involves the following four functions: CSL_PSC_enablePowerDomain() CSL_PSC_setMosuleNextState() CSL_PSC_startStateTransition() CSL_PSC_isStateTransitionDone() 2. Reset the HyperLink and load the boot code for the PLL. Write 1 to the reset field of control register (address base + 0x04) CSL_BootCfgUnlockKicker(); CSL_BootCfgSetVUSRConfigPLL () 3. Configure the SERDES. CSL_BootCfgVUSRRxConfig() CSL_BootCfgVUSRTxConfig()

41 Platform Level Configuration 1. HyperLink Control registers 2. Interrupt registers 3. Lane Power Management registers 4. Error Detection registers 5. SerDes operation configuration 6. Address Translation registers

42 Basic HyperLink LLD Functions hyplnkret_e Hyplnk_open (int portnum, Hyplnk_Handle *phandle) Hyplnk_open creates/opens a HyperLink instance. hyplnkret_e Hyplnk_close (Hyplnk_Handle *phandle) Hyplnk_close Closes (frees) the driver handle. hyplnkret_e Hyplnk_readRegs (Hyplnk_Handle handle, hyplnklocation_e location, hyplnkregisters_t *readregs) Performs a configuration read. hyplnkret_e Hyplnk_writeRegs (Hyplnk_Handle handle, hyplnklocation_e location, hyplnkregisters_t *writeregs) Performs a configuration write. hyplnkret_e Hyplnk_getWindow (Hyplnk_Handle handle, void **base, uint32_t *size) Hyplnk_getWindow returns the address and size of the local memory window. uint32_t Hyplnk_getVersion (void) Hyplnk_getVersion returns the HYPLNK LLD version information. const char * Hyplnk_getVersionStr (void) Hyplnk_getVersionStr returns the HYPLNK LLD version string.

43 Configuration Functions Configuration functions are part of the HyperLink example in the PDK release and can be used as is or be modified by users. PDK_INSTALL_PATH\ti\drv\hyplnk\example\common\hyplnkLLDIFace.c Some of the configuration functions are: hyplnkret_e hyplnkexampleassertreset (int val) Void hyplnkexampleserdescfg (uint32_t rx, uint32_t tx) hyplnkret_e hyplnkexamplesyssetup (void) Void hyplnkexampleeqlaneanalysis (uint32_t lane, uint32_t status) hyplnkret_e hyplnkexampleperiphsetup (void)

44 Example: Configuration Function /********************************************************** ******************* * Sets the SERDES configuration registers *********************************************************** *****************/ void hyplnkexampleserdescfg (uint32_t rx, uint32_t tx) { CSL_BootCfgUnlockKicker(); CSL_BootCfgSetVUSRRxConfig (0, rx); CSL_BootCfgSetVUSRRxConfig (1, rx); CSL_BootCfgSetVUSRRxConfig (2, rx); CSL_BootCfgSetVUSRRxConfig (3, rx); CSL_BootCfgSetVUSRTxConfig (0, tx); CSL_BootCfgSetVUSRTxConfig (1, tx); CSL_BootCfgSetVUSRTxConfig (2, tx); CSL_BootCfgSetVUSRTxConfig (3, tx); } /* hyplnkexampleserdescfg */

45 1. HyperLink Overview 2. Address Translation 3. Configuration 4. Example and Demo Agenda

46 Example and Demo Included in the PDK (Platform Development Kit) release are a set of examples for each of the peripherals. For HyperLink, there is one example that can be configured either as a single-evm loopback or between two C66x EVM boards. Location of the example: pdk_c6678_1_0_0_19\packages\ti\drv\exampleprojects\hyplnk_exampleproject The loopback flag is in the file hyplnklldcfg.h

47 For More Information For more information, refer to the KeyStone Architecture HyperLink User Guide For questions regarding topics covered in this training, visit the support forums at the TI E2E Community website.