Component Selector Guide November 2004

Transcription

1 Component Selector Guide November 2004

2 Introduction Leadin Throuh Innovation The world s pioneer in reprorammable devices, Altera Corporation offers a complete rane of CPLDs, FPGAs, and structured ASICs that fit into nearly every corner of the diital electronics market. Combined with Altera s interated desin software, comprehensive intellectual property (IP) portfolio, embedded processors, peripherals, and extensive customer trainin proram, Altera s industry-leadin components provide the flexibility, easeof-use, and short development cycles needed to quickly turn desin concepts into solid desin solutions. In an era when cost control is paramount, Altera delivers low-cost, hih-performance devices that help streamline the desin process and et products to market faster. Popular, customer-driven features, toether with the inherent value of prorammable loic exceptional adaptability, low cost, low risk, and rapid development uniquely position Altera s products to displace other, more costly solutions, such as traditional ASICs and ASSPs. Altera solutions enable the future by deliverin proressive technoloy and value to a much broader market than was previously addressed by prorammable loic. From simple lue loic, to sophisticated system-level solutions, to flexible, low-cost ASIC alternatives, Altera s device cateories include: CPLDs: non-volatile, instant-on devices for simple loic interation in a wide variety of applications Low-Cost FPGAs: lowest-cost FPGAs for price-sensitive, volume-driven applications Hih-Density FPGAs: the best possible system interation for hih-bandwidth systems Structured ASICS: a comprehensive, minimal-risk alternative to standard-cell ASICs Sections Device Family Series Description Pae CPLDs Low-cost, hih-volume CPLDs, featurin MAX II: the lowest-cost CPLD ever... 3 Low-Cost FPGAs Low-cost, performance-optimized FPGAs, featurin Cyclone II: the lowest-cost FPGAs ever... 5 Low-cost, 5-V tolerant FPGAs... 6 Hih- Density FPGAs Hih-density, hih-performance FPGAs, featurin Stratix II: the biest and fastest FPGAs... 7 Structured ASICs Structured ASICS with low non-recurrin enineerin (NRE) costs, low-cost tool suite, and uaranteed success, featurin the HardCopy Stratix family

3 CPLDs Altera CPLDs feature sinle-chip, instant-on capability and non-volatility for low-cost, low-density loic interation in a wide variety of diital applications. Application Examples Consumer Electronics Automotive Telematics Storae Servers 3G Base Stations, Servers & Routers Industrial Test Equipment MAX II CPLDs Buildin on more than fifteen years of CPLD market leadership and innovation, Altera introduces the MAX II device family, the lowest-cost CPLDs ever. MAX II devices are based on a roundbreakin new CPLD architecture that delivers the lowest cost per I/O pin and the lowest power of any CPLD family. MAX II devices deliver half the cost, one-tenth the power, four times the density, and twice the performance of previous MAX devices. These benefits allow desiners to interate multiple control path applications onto a sinle device. Control path applications can be divided into four cateories: I/O expansion, interface bridin, power-up sequencin, and system confiuration (see Fiure 1). The MAX II loic array block (LAB) is based on a lookup table (LUT) with row-and-column routin to deliver a sinificant cost reduction over previous CPLDs. Combined with instant-on capability, non-volatility, and reprorammability, this innovative new architecture makes MAX II devices the lowest-cost CPLDs today. MAX II Summary Half the cost of MAX CPLDs CPLDs One-tenth the power Four times the density Twice the performance Unique board manaement features Table 1. MAX II Hihlihts Cost-Optimized Architecture Low Power Hih Density Non-Volatile & Instant-On Functionality User Flash Memory Real-Time In-System Prorammability (ISP) MultiVolt Core MultiVolt I/O Interface MultiTrack Interconnect Joint Test Action Group (JTAG) Translator Get 4X the density at half the price with the roundbreakin new CPLD architecture Reduce power consumption & increase system reliability with device power as low as 3 mw (at 0 MHz) Implement more applications in a sinle, low-cost device with device densities up to 2,210 loic elements (LEs) Reduce cost & board space with a sinle-chip solution Minimize system costs & chip count by interatin discrete serial or parallel nonvolatile storae onto MAX II devices Reduce maintenance costs by updatin while the device is in operation Operate with a 1.8-, 2.5-, or 3.3-V power supply, minimizin power rails & simplifyin board desin Interface seamlessly to other devices at 1.5-, 1.8-, 2.5-, or 3.3-V loic levels Optimize performance with eneral & local routin lines, includin fast I/O connection, and a new direct loic cell-to-i/o path Simplify board manaement by usin MAX II devices to confiure external non- JTAG-compliant devices 3

4 MAX CPLDs Introduced in 1988, Altera s MAX family is the industry-standard for CPLDs. Today s MAX families include the cost-optimized MAX 3000A and hih-performance MAX 7000 CPLDs, each of which offers densities, packaes, and speed rades to meet a variety of desin needs. These devices also offer non-volatile and instant-on operation, MultiVolt I/O, and Jam Standard Test and Prorammin Lanuae (STAPL) support for easy system interation. MAX 3000A CPLDs The cost-optimized MAX 3000A devices are the ideal choice for hih-volume systems. MAX 3000A devices provide desiners with exceptional performance at the lowest price per macrocell amon MAX devices. MAX 3000A Summary Low cost Densities ranin from 32 to 512 macrocells Up to 208 user I/O pins CPLDs Popular thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine BGA packaes Enhanced ISP Deterministic Routin Table 2. MAX 3000A Hihlihts Low Price per Macrocell 4.5-ns Propaation Delays 5.0-V-Tolerant I/O Pins Industrial Temperature Ideal for low-cost, hih-volume applications Provides fast system performance Inherently interfaces to 5.0-V devices Reduces overall system costs for temperature-sensitive applications MAX 7000 CPLDs MAX 7000 devices are well-suited for mixed-voltae environments, offerin 2.5-, 3.3-, or 5.0-V core supply operation and MultiVolt I/O operation to interface with 1.8-, 2.5-, 3.3-, and 5.0-V devices. The popular MAX 7000AE devices are the industry-standard 3.3-V CPLD family. The 2.5-V MAX 7000B devices offer desiners a seamless path to lower voltaes, faster propaation times, and compatibility with new I/O standards. MAX 7000S devices feature 5.0-V core supply operation and are ideal for system-level interation. All MAX 7000 family members are pin-, function-, and prorammin-file compatible. MAX 7000 Summary Densities ranin from 32 to 512 macrocells Up to 212 user I/O pins Advanced I/O standards for MAX 7000B CPLDs Vertical miration across families Extended temperature support for MAX 7000AE CPLDs Deterministic Routin Table 3. MAX 7000 Hihlihts 3.5-ns Propaation Delays Provides fast system performance 1.8-V I/O Interface Supports emerin 1.8-V systems Support for Advanced I/O Standards Supports GTL+ & SSTL-2/-3 I/O standards Prorammable Power-Savin Mode Reduces power consumption by over 50% Commercial, Industrial & Extended Temperature Provides support for all environmental conditions 4

5 Low-Cost FPGAs Altera s low-cost Cyclone II, Cyclone and ACEX FPGA families provide the re-prorammability of an FPGA at an extremely low cost, extendin the benefits of prorammable loic to applications that were traditionally cost-driven to standard products or ASICs. These low-cost devices provide an optimized feature set and abundant on-chip resources specifically tuned for hih-volume applications. Application Examples Diital Set-Top Boxes DVD Player/Recorder System Plasma Displays Automotive Telematics Industrial Automation Equipment Cyclone II FPGAs Buildin on the tremendous success of the Cyclone device family, Cyclone II devices offer hiher densities, more features, exceptional performance, and all the benefits of prorammable loic at the lowest cost. The Cyclone II device family delivers a flexible, low-risk, and low-cost solution that presents a hihly attractive alternative to low- and mid-density ASICs. Cyclone II FPGAs extend the Cyclone series loic density up to 68,416 loic elements (LEs) and lowers cost further than first-eneration Cyclone devices, makin Cyclone II FPGAs the ideal solution for lowcost, hih-volume applications. Cyclone II devices are manufactured on 300-mm wafers usin Taiwan Semiconductor Manufacturin Company s (TSMC s) 90-nm, low-k dielectric process. External memory interfaces supportin data transfer up to 668 Mbps Up to x18 embedded multipliers Up to 4 phase-locked loops (PLLs) Software support in the free Quartus II Web Edition desin software Altera s low-cost serial confiuration devices suppor Fiure 1. Cyclone II Floorplan Phase-Locked Loops Embedded Multipliers Loic Array M4K Memory Blocks Low-Cost FPGAs Cyclone II Summary Densities ranin from 4,608 to 68,416 LEs Up to 622 user I/O pins Up to 1,152 Kbits RAM Sinle-ended and differential I/O standards support Side I/O Elements with Support for PCI/PCI-X & Memory Interfaces Top & Bottom I/O Elements with Support for Memory Interfaces Table 4. Cyclone II Hihlihts Embedded Memory Embedded 18x18 Multipliers I/O Standard Support External Memory Interfaces Clock Manaement Circuitry Nios II Embedded Processors Serial Confiuration Devices Up to 250 M4K (4Kbits) embedded memory blocks that supports multiple confiurations, includin true dual-port and sinle-port RAM, ROM, and first-in first-out (FIFO) buffers. Capable of runnin at up to 250 MHz, Cyclone II 18x18 embedded multipliers can impliment common DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), and correlators. Support for LVTTL, LVCMOS, PCI, PCI-X, SSTL, and HSTL sinle-ended I/O standards and LVDS mini- LVDS, RSDS, and LVPECL differential I/O standards. LVDS is supported at data rates up to 805 Mbps on the receiver side and up to 622 Mbps on the transmitter side. Support for hih-speed memory devices includin QDRII SRAM, SDR SDRAM, DDR SDRAM, and DDR2 SDRAM devices at data rates up to 668 Mbps. Up to 16 low-skew, lobal clock networks span the entire device, fed by 16 dedicated input clock pins. Nios II desiners can achieve performance over 100 DMIPS and spend as little as $0.35 in loic. Altera's serial confiuration device family delivers the lowest total system cost, includin the cost of confiurin the system. 5

6 Cyclone FPGAs Cyclone devices are the first eneration of low-cost Cyclone series of FPGAs. Desined from the round up and based on extensive input from hundreds of customers, the Cyclone family offers an ideal combination of cost, density, features, and performance. Altera s Cyclone device family has taken the industry by storm. In the 18 months since the family s introduction, over 3,000 customers have used Cyclone devices in a wide rane of applications, includin plasma displays, wireless basestations, printers, and hand-held radios. Cyclone Summary Densities ranin from 2,910 to 20,060 LEs Up to 301 user I/O pins Up to 288 Kbits of RAM I/O channels supportin data rates up to 640 Mbps External memory interface support for 133-MHz double data rate (DDR) Up to two phase-locked loops (PLLs) Software support in the free Quartus II Web Edition desin tool Low-cost serial confiuration device support Hih-Density FPGAs Table 5. Cyclone Hihlihts Embedded Memory External Memory Interfaces I/O Standards Supported Nios Embedded Processor Support Serial Confiuration Devices Offers support for the M4K memory block that supports RAM, ROM & first-in first-out (FIFO) memories Support for hih-speed memory devices includin 133-Mhz DDR, FCRAM & SDR SRAM devices Sinle-ended I/O support includin LVTLL, LVCMOS, PCI, SSTL-2, SSTL-3 & 129 LVDS-compatible channels supportin data rates up to 640 Mbps Industry s most widely used embedded processor available for under $2.00 in hih-volume This serial confiuration device family delivers the lowest total system cost, includin the cost of confiurin the system ACEX FPGAs The ACEX family addresses low-density desins for applications that require low-cost and 5.0-V-tolerant I/O pins. ACEX devices are well-suited for 5.0-V applications. ACEX Summary Up to 4,992 LEs Up to 49 Kbits of memory MultiVolt I/O interface Support for one PLL 64-Bit, 66-MHz PCI compliance Software support in the free Quartus II Web Edition desin tool Table 6. ACEX Hihlihts Cost-Efficient Architecture On-Chip Memory Wide I/O Voltae Interface Rane Flexible Interconnect Low-cost solution for communications applications Dual port & FIFO implementation on-chip 2.5-, 3.3- & 5.0-V-tolerant I/O pins FastTrack interconnect continuous routin structure for fast, predictable interconnect delays 6

7 Hih-Density FPGAs Altera s hih-density FPGAs rane from 10,570 to 179,400 LEs and deliver the unsurpassed flexibility, core performance, memory capacity, DSP capabilities, bandwidth, and timeto-market advantaes required for complex SOPC solutions. Incorporatin customer feedback for system desin requirements, Altera developed Stratix II and Stratix devices to address the increasinly complex bandwidth requirements for applications in communications, industrial, automotive, electronic data processin, and diital consumer end-markets. Application Examples Hih-End Routers & Switches IC Testers Medical Imain Equipment Wireless Base Stations Factory Automation Radar Communications Stratix II FPGAs Stratix II devices are the latest in hih-density, hihperformance FPGAs from Altera. Stratix II devices eliminate the performance, density, and cost barriers that have forced desiners to use time-consumin alternative technoloies. Desiners usin Stratix II devices can achieve ASIC-like density and performance plus the time-to-market advantaes of prorammable loic. On averae, Stratix II devices deliver 50 percent hiher performance and offer more than twice the density of previouseneration Stratix devices. Stratix II devices support internal clock frequency rates of up to 500 MHz and typical desin performance over 250 MHz. The new loic structure (see Fiure 2) features adaptive loic modules (ALMs) that allow desiners to pack more functionality into less area, further reducin system costs. Table 6 shows the Stratix II device family hihlihts. Optimized for 90-nm process technoloy, these second-eneration devices include all of the features and characteristics of the award-winnin Stratix FPGA family and cost 40 percent less than Stratix devices for equivalent densities. Hih-volume applications can also benefit from HardCopy structured ASICs, the industry s only seamless miration path from FPGA prototype to hih-volume, low-cost production. The HardCopy version of a Stratix II FPGA desin further increases performance and reduces power consumption over the oriinal FPGA implementation and offers sinificantly lower unit costs. More information on HardCopy devices can be found on pae 9. Hih-Density FPGAs Stratix II Summary 1.2-V, 90-nm low-k process technoloy Up to 71,760 ALMs equivalent to 179,400 LEs Up to 9 Mbits of TriMatrix memory Up to x18 multipliers in DSP blocks Up to 156 receiver & 156 transmitter channels with data rates of up to 1 Gbps usin DPA for hih-speed I/O protocols External memory interface support for advanced memory devices such as DDR2, DDR, QDRII, QDR & RLDRAM II Up to 12 PLLs Up to 1,170 user I/O pins Fiure 2. Stratix II Floorplan PLL Adaptive Loic Modules M512 Block DSP Block M4K Block M-RAM Block Hih-Speed I/O Channels with DPA I/O Channels with External Memory Interface Circuitry Stratix II EP2S60 FPGA 7

8 Table 7. Stratix II Hihlihts New Loic Structure External Memory Interface TriMatrix Memory DSP Blocks Desin Security 1-Gbps Differential I/O & Hih-Speed Interfaces Dynamic Phase Alinment (DPA) Support Remote System Uprades Based on a new and innovative ALM-based loic structure that delivers faster performance & maximum resource efficiency Support for the latest external memory interfaces in dedicated circuitry, includin 267-MHz DDR2 SDRAM, 300-MHz RLDRAM II & 200-MHz QDRII SRAM devices Up to 9 Mbits of memory in three block sizes with parity, capable of up to 370 MHz performance Up to x18 multipliers that operate at up to 370-MHz, optimized for performance-intensive DSP applications such as JPEG2000, CDMA, HSDPA & 1x EV DV Non-volatile, 128-bit advanced encryption standard (AES) desin encryption technoloy for impenetrable desin security, preventin IP theft Support for hih-speed I/O standards & hih-speed interfaces such as 10-Giabit Ethernet (XSBI), SFI-4, SPI 4.2, HyperTransport, RapidIO & UTOPIA IV interfaces at up to 1 Gbps Enables 1-Gbps data transfer rates by eliminatin channel-to-channel & channel-to-clock skew in hih-speed data transmission systems Remote system uprades for reliable & safe deployment of in-system uprades & bu fixes Hih-Density FPGAs Stratix FPGAs Altera s award-winnin Stratix device family provides hih density, performance, and a rich feature set that enables hih levels of system interation. Stratix devices offer systemlevel features that ive desiners the performance, memory bandwidth, DSP functionality, and I/O performance necessary for advanced applications. Stratix Summary 1.5-V, 0.13-µm, all-layer-copper SRAM process Densities ranin from 10,570 to 79,040 LEs TriMatrix memory structure offerin up to 7 Mbits of RAM Up to 22 DSP blocks offerin up to 88 18x18 multipliers Hih-speed differential I/O channels supportin data rates up to 840 Mbps External memory interface support for 200-MHz DDR, QDR, QDR II & RLDRAM II 12 PLLs All devices shippin in production volumes Up to 1,203 user I/O pins Table 8. Stratix Hihlihts Hih-Performance Architecture TriMatrix Memory DSP Blocks Hih-Bandwidth I/O Standards External Memory Interfaces Remote System Uprade Performance optimized MultiTrack interconnect with DirectDrive technoloy for block-based desin Three sizes of memory with up to 7 Mbits of memory & 8 terabits per second of bandwidth Predictable 333-MHz performance for data throuhput of 2.4 GMACS per DSP block Support for hih-speed protocols such as SPI4.2, SFI-4, XSBI Ethernet, UTOPIA IV, RapidIO & HyperTransport standards Support for advanced memory interfaces such as DDR, DDR2, QDR, QDR II & RLDRAM II Real-time updates to FPGAs from remote locations 8

9 Stratix GX FPGAs Stratix GX FPGAs combine Altera s second-eneration transceiver serializer/deserializer (SERDES) technoloy with the award-winnin Stratix FPGA architecture. Stratix GX FPGAs interate an optimized Gbps transceiver that includes features such as 40-inch drive strenth capability, pre-emphasis, equalization, channel alinment, and embedded 8B/10B encoder/decoder. In addition, Stratix GX FPGAs contain source-synchronous differential I/O capability (operatin at up to 1 Gbps) with circuitry that performs dynamic phase alinment (DPA). Stratix GX Summary 1.5-V, 0.13-µm, all-layer-copper SRAM process Up to 20 channels capable of operatin between 500 Mbps and Gbps Densities ranin from 10,570 to 41,250 LEs Pre-emphasis & equalization circuitry improves sinal interity marins Source-synchronous differential I/O pins with DPA supportin channel rates up to 1 Gbps TriMatrix memory structure offerin up to 3.4 Mbits of RAM External memory interface support for 200-MHz DDR, QDR, QDR II & RLDRAM II Table 9. Stratix GX Hihlihts Gbps Transceiver Blocks 40-Inch Drive Strenth Capability Low Power Consumption 1 Gbps Source-Synchronous Differential I/O Pins with DPA Hih-Performance Stratix-Based Architecture Support for protocols such as SerialLite, Giabit Ethernet, XAUI, Giabit Ethernet, Fibre Channel, Serial RapidIO, SONET/SDH, PCI Express, SerialLite & SMPTE 292M standards Pre-emphasis & equalization combine to enable a 40-inch sinal drive capability on traces across an FR4 material 450-mW power consumption per 4-channel transceiver block Support for 10 Giabit Ethernet XSBI, SFI-4, SPI-4.2, HyperTransport, parallel RapidIO & NPSI standards Performance-optimized MultiTrack interconnect with DirectDrive technoloy for block-based desin 9

10 Structured ASICs Desinin standard-cell ASICs today is a very expensive option. It requires sinificant enineerin resources and offers no uarantee that the first silicon will be fully functional or that the final device will be manufactured within the planned time and fiscal budet. Belonin to a new cateory of devices called structured ASICs, Altera s HardCopy devices address these concerns and provide a comprehensive, minimal-risk alternative to standard-cell ASICs. To manufacture HardCopy devices, Altera uses common base arrays across multiple desins for a particular density and implements customer-specific desin information with the top metal layers. The seamless miration of an FPGA-proven, in-system-verified desin to a HardCopy structured ASIC delivers silicon uaranteed to be fully functional the first time. Application Examples Networkin & Storae Wireless Communications Medical Instruments Test & Measurement Hih-End Consumer Electronics Structured ASICs HardCopy Stratix Structured ASICs The HardCopy Stratix device extends the HardCopy Stratix devices are easy to desin usin the features and benefits of Stratix devices advanced features of the Quartus II desin software. The into hih-volume applications. With a Quartus II software includes the capability to prototype and desin flow identical to ASICs and a verify functionality in-system with the FPGA before proven methodoloy that uarantees first-silicon success, committin to the masks and wafers. Fiure 3 shows the HardCopy Stratix devices eliminate the pain with standardcell ASIC desin, and provide comparable cost, perfor- ASICs are shippin in volume today. HardCopy Stratix desin flow. HardCopy Stratix structured mance, and power consumption. Because HardCopy devices preserve the FPGA architecture, desins prototyped with the FPGA can be seamlessly mirated to the HardCopy version. HardCopy Stratix Summary Fiure 3: Unified Desin Methodoloy 1.5-V, 0.13-µm, all-layer-copper process Up to 1 M equivalent standard cell ates (estimated), 5.7 Mbits & 773 user I/O pins Up to 22 DSP blocks offerin up to 88 18x18 multipliers Hih-speed differential I/O channels supportin data rates up to 840 Mbps External memory interface support for 200-MHz DDR, QDR & RLDRAM 1 On averae, 50% performance improvement & 40% lower power consumption over FPGAs Note: 1 Contact your Altera sales representative. Desin Software Timin Optimization Floorplan View Power Estimator Prototype HardCopy Stratix Desin Flow FPGA Prototypin System Verification Mirate Seamlessly Field Trial Production Head Start on Quality Assurance System Software Development Production Low Price Seamless Miration Hiher Performance Lower Power Consumption 10

11 Table 10. HardCopy Structured ASICs Hihlihts Comprehensive Alternative to ASICs Unified Desin Methodoloy with the Quartus II Software Facilitates Total System Development In-System & In-Silicon Verification Seamless Miration Preserves FPGA Architecture Pin-to-Pin Compatibility with the Equivalent FPGA Embedded Testability A complete solution with devices, desin tools & services, IP & technical support from a sinle vendor for prototypes & structured ASICs Provides the option to directly taret a HardCopy device, or prototype first on an FPGA and then mirate to a HardCopy structured ASIC (see Fiure 3) Parallel development of the complete system with the FPGA enables product shipment in the quickest possible time, even as the HardCopy device is bein developed Aids desin verification in the actual environment prior to investment in masks & wafers Minimizes risk, uarantees first-silicon success, reduces development costs & enables fastest time-to-market Proven architecture & the process technoloy ensures seamless miration & its benefits Drop-in replacement of the FPGA prototype removes board re-desin and re-qualification & saves cost & time-to-market Built-in test circuits & test methodoloy provide ~100% test coverae, aidin uaranteed functionality 11

12 Tables 11 throuh 23 list the LE, macrocell and ate counts, pin/packae options, I/O pin counts, supply voltae, RAM bits, and other device-specific features of Altera CPLDs, FPGAs, structured ASICs, and confiuration devices. Table 11. MAX II Devices DEVICE LES TYPICAL EQUIVALENT MACROCELLS PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE USER FLASH MEMORY BITS EPM Pin TQFP V, 2.5 V, 8,192 EPM Pin TQFP, 144-Pin TQFP, 256-Pin BGA 1 76, 116, V, 2.5 V, 8,192 EPM1270 1, Pin TQFP, 256-Pin BGA 1 116, V, 2.5 V, 8,192 EPM2210 2,210 1, Pin BGA 1, 324-Pin BGA 1 204, V, 2.5 V, 8,192 Note to Table 11: mm FineLine BGA packaes. Table 12. MAX 3000 Devices DEVICE MACROCELLS PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE SPEED GRADE EPM3032A Pin PLCC 1 /TQFP V -4, -7, -10 EPM3064A Pin PLCC/TQFP, 100-Pin TQFP 34, V -4, -7, -10 EPM3128A Pin TQFP, 144-Pin TQFP, 256-Pin BGA 2 80, 96, V -5, -7, -10 EPM3256A Pin TQFP, 208-Pin PQFP, 256-Pin BGA 2 116, 158, V -7, -10 EPM3512A Pin PQFP, 256-Pin BGA 2 172, V -7, -10 Notes to Table 12: 1 PLCC: plastic J-lead chip carrier mm pitch FineLine BGA packae. Table 13. MAX 7000 Devices DEVICE MACROCELLS PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE EPM7032S EPM7032AE EPM7032B EPM7064S EPM7064AE EPM7064B EPM7128S EPM7128AE EPM7128B Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 49-Pin BGA 1 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA 2 44-Pin TQFP, 49-Pin BGA 1, 100-Pin TQFP, 100-Pin BGA 1 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA 2, 144-Pin TQFP, 256-Pin BGA Pin TQFP, 100-Pin BGA 2, 144-Pin TQFP, 256-Pin BGA , 36 36, 68, 68 36, 68, 68 36, 41, 68, 68 68, 84, , 84, 84, 100, , 84, 100, V 3.3 V 2.5 V 5.0 V 3.3 V 2.5 V 5.0 V 3.3 V 2.5 V SPEED GRADE -5, -6, -7, -10-4, -7, -10-3, -5, -7-5, -6, -7, -10-4, -7, -10-3, -5, -7-6, -7, -10, -15-5, -7, -10-4, -7, -10 EPM7160S Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 64, 84, V -6, -7, -10 EPM7192S Pin PQFP V -7, -10, -15 EPM7256S EPM7256AE EPM7256B EPM7512AE EPM7512B Pin PQFP/RQFP Pin TQFP, 100-Pin BGA 2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA Pin TQFP, 144-Pin TQFP, 169-Pin BGA 1, 208-Pin PQFP, 256-Pin BGA Pin TQFP, 208-Pin PQFP, 256-Pin BGA 2, 256-Pin BGA 144-Pin TQFP, 169-Pin BGA 1, 208-Pin PQFP, 256-Pin BGA 2, 256-Pin BGA , 84, 120, 164, , 120, 141, 164, , 176, 212, , 141, 176, 212, V 3.3 V 2.5 V 3.3 V 2.5 V -7, -10, -15-5, -7, -10-5, -7, -10-7, -10, -12-5, -7, -10 Notes to Table 13: mm pitch Ultra FineLine BGA packae mm pitch FineLine BGA packae. 3 RQFP: power quad flat pack 12

13 Table 14. Cyclone Devices DEVICE LEs PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE RAM BITS EP1C3 2, Pin TQFP, 144-Pin TQFP 1 65, V 59,904 EP1C4 4, Pin BGA 1, 400-Pin BGA 1 249, V 78,336 EP1C6 5, Pin TQFP, 240-Pin PQFP, 256-Pin BGA 1 98, 185, V 92,160 EP1C12 12, Pin PQFP, 256-Pin BGA 1, 324-Pin BGA 1 173, 185, V 239,616 EP1C20 20, Pin BGA 1, 400-Pin BGA 1 233, V 294,912 Note to Table 14: 1 Space-savin FineLine BGA packae. Table 15. Cyclone II Devices DEVICE LEs PIN/PACKAGE OPTIONS 1 I/O PINS SUPPLY VOLTAGE M4K RAM BLOCKS 2 RAM BITS EMBEDDED MULTIPLIERS 3 EP2C5 4, Pin TQFP, 208-Pin PQFP, 256-Pin FineLine BGA 4 89, V , EP2C8 8, Pin TQFP, 208-Pin PQFP, 256-Pin FineLine BGA EP2C20 18, Pin PQFP, 256-Pin FineLine BGA, 484-Pin FineLine BGA EP2C35 33, Pin FineLine BGA, 672-Pin FineLine BGA DP2C50 50, Pin FineLine BGA, 672-Pin FineLine BGA EP2C70 68, Pin FBGA, 896-Pin FineLine BGA 85, 138, , , , , V , V , V , V , V 250 1,152, PLLs Note to Table 15: 1 Cyclone II devices support vertical miration within the same packae. 2 4Kbits plus 512 parity bits. 3 Total number of 18x18 multipliers. For the total number of 9x9 multipliers per device, multiply the total number of 18x18 multipliers by 2. 4 Contact your local Altera sales representative for more information. Table 16. ACEX Devices DEVICE LES PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE RAM BITS EP1K Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA 1 66, 92, 120, V 12,288 EP1K30 1, Pin TQFP, 208-Pin PQFP, 256-Pin BGA 1 102, 147, V 24,576 EP1K50 2, Pin TQFP, 208-Pin PQFP, 256-Pin BGA 1, 484-Pin BGA 1 102, 147, 186, V 40,960 EP1K100 4, Pin PQFP, 256-Pin BGA 1, 484-Pin BGA 1 147, 186, V 49,152 Note to Table 16: 1 Space-savin FineLine BGA packae. 13

14 Table 17. Stratix II Devices DEVICE ADAPTIVE LOGIC MODULES (ALMS) 1 EQUIVALENT LES 1 PIN/PACKAGE OPTIONS MAXIMUM USER I/O PINS SUPPLY VOLTAGE M512 RAM BLOCKS M4K RAM BLOCKS M-RAM BLOCKS TOTAL RAM BITS DSP BLOCKS EMBEDDED MULTIPLIERS 2 PLLS 3 EP2S15 6,240 15, Pin BGA 4, Pin BGA EP2S30 13,552 33, Pin BGA 4, Pin BGA EP2S60 24,176 60, Pin BGA 4, 672-Pin BGA 4, 1,020-Pin BGA 4 EP2S90 36,384 90, Pin BGA 5,6 780-Pin BGA 4,6 1,020-Pin BGA 4, 1,508-Pin BGA 4 EP2S130 53, , Pin BGA 4,6 1,020-Pin BGA 4 1,508-Pin BGA ,126 EP2S180 71, ,400 1,020-Pin BGA 4 1,508-Pin BGA , V , V ,369, V ,544, V ,520, V ,747, V ,383, Notes to Table 17: 1 Each Stratix II ALM is equivalent to 2.5, 4-input look-up table (LUT)-based LEs. 2 Each DSP block supports four multipliers. 3 Includes enhanced and fast PLLs. 4 Space-savin FineLine BGA packae 5 Hybrid FineLine BGA packae with 27mm x 27mm body size. 6 User 1/0 counts are preliminary and subject to chane. Table 18. Stratix Devices Note 1 DEVICE LEs PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE TOTAL RAM BITS EP1S10 10, Pin BGA 2, 672-Pin BGA, 672-Pin BGA 2, 780-Pin BGA 2 335, 345, 345, V 920,448 6 EP1S20 18, Pin BGA 2, 672-Pin BGA, 672-Pin BGA 2, 780-Pin BGA 2 361, 426, 426, V 1,669, EP1S25 25, Pin BGA, 672-Pin BGA 2, 780-Pin BGA 2, 1,020-Pin BGA 2 473, 473, 597, V 1,944, EP1S30 32, Pin BGA 2, 956-Pin BGA, 1,020-Pin BGA 2 589, 683, V 3,317, EP1S40 41, Pin BGA 2, 956-Pin BGA, 1,020-Pin BGA 2, 1,508-Pin BGA 2 615, 683, 773, V 3,423, EP1S60 57, Pin BGA, 1,020-Pin BGA 2, 1,508-Pin BGA 2 683, 773, 1, V 5,215, EP1S80 79, Pin BGA, 1,020-Pin BGA 2, 1,508-Pin BGA 2 683, 773, 1, V 7,427, Notes to Table 18: 1 The orderin code for Stratix devices is based on the number of LEs; therefore, ate count numbers are not included. 2 Space-savin FineLine BGA packae. DSP BLOCKS Table 19. Stratix GX Devices DEVICE LEs TRANSCEIVER CHANNELS PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE RAM BITS SOURCE-SYNCHRONOUS CHANNELS EP1SGX10C 10, Pin BGA V 920, EP1SGX10D 10, Pin BGA V 920, EP1SGX25C 25, Pin BGA V 1,944, EP1SGX25D 25, Pin BGA 1, 426, 1,020-Pin BGA V 1,944, EP1SGX25F 25, ,020-Pin BGA V 1,944, EP1SGX40D 41, ,020-Pin BGA V 3,423, EP1SGX40G 41, ,020-Pin BGA V 3,423, Note to Table 19: 1 Space-savin FineLine BGA packae. 14

15 Table 20. APEX 20K Devices DEVICE LEs PIN/PACKAGE OPTIONS I/O PINS SUPPLY VOLTAGE RAM BITS EP20K30E 1, Pin TQFP, 144-Pin BGA 1, 208-Pin PQFP 92, 93, ,576 EP20K60E 2, Pin TQFP, 144-Pin BGA 1, 208-Pin PQFP, 324-Pin BGA 1, 356-Pin BGA EP20K100 EP20K100E 4,160 4, Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA 1, 356-Pin BGA 144-Pin TQFP, 144-Pin BGA 1, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA 1, 356-Pin BGA 92, 93, 148, 196, , 159, 189, 252, , 93, 151, 183, 246, 246 EP20K160E 6, Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 88, 143, 175, 356-Pin BGA, 484-Pin BGA 1 271, 316 EP20K200 EP20K200E EP20K200C 8,320 8,320 8, Pin PQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA Pin PQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA 1, 652-Pin BGA, 672-Pin BGA Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA 1 144, 174, 277, , 168, 271, 376, 376, , 168, 271, , V 53,248 53,248 81, V 106, , ,496 EP20K300E 11, Pin PQFP, 652-Pin BGA, 672-Pin BGA 1 152, 408, ,456 EP20K400 EP20K400E EP20K400C EP20K600E EP20K600C EP20K1000E EP20K1000C 16,640 16,640 16,640 24,320 24,320 38,400 38, Pin BGA, 672-Pin BGA Pin BGA, 672-Pin BGA Pin BGA, 672-Pin BGA 1 502, , , Pin BGA, 672-Pin BGA 1, 1,020-Pin BGA 1 488, 508, Pin BGA, 672-Pin BGA 1, 1,020-Pin BGA 1 488, 508, Pin BGA, 672-Pin BGA 1, 1,020-Pin BGA 1 488, 508, Pin BGA, 672-Pin BGA 1, 1,020-Pin BGA 1 488, 508, V 212, , , , , , ,680 EP20K1500E 51, Pin BGA, 1,020-Pin BGA 1 488, ,368 Note to Table 20: 1 Space-savin FineLine BGA packae. Table 21. HardCopy Devices DEVICE ESTIMATED LOGIC LEs PIN/PACKAGE OPTIONS I/O PINS SUPPLY GATES (K) 1 VOLTAGE RAM BITS HC1S , Pin BGA V 1,944,576 HC1S , Pin BGA V 2,137,536 HC1S , Pin BGA V 2,244,096 HC1S ,120 1,020-Pin BGA V 5,215,104 HC1S80 1,000 79,040 1,020-Pin BGA V 5,658,048 HC20K , Pin BGA, 672-Pin BGA 2 488, ,992 HC20K , Pin BGA, 672-Pin BGA 2 488, ,296 HC20K , Pin BGA, 672-Pin BGA 1, 1,020-Pin BGA 2 488, 508, ,680 HC20K , Pin BGA, 1,020-Pin BGA 2 488, ,368 Notes to Table 21: 1 Does not include DSP blocks or memories. 2 Space-savin FineLine BGA packae. 15

16 Table 22. Serial Confiuration Devices for Cyclone II, Stratix II & Cyclone FPGAs DEVICE PIN/PACKAGE OPTIONS SUPPLY VOLTAGE DESCRIPTION EPCS1 8-Pin SOIC V In-system prorammable 1-Mbit serial confiuration device desined to confiure Cyclone II, Stratix II, and Cyclone devices EPCS4 8-Pin SOIC 3.3 V In-system prorammable 4-Mbit serial confiuration device desined to confiure Cyclone II, Stratix II, and Cyclone devices EPCS16 16-Pin SOIC 3.3 V In-system prorammable 16-Mbit serial confiuration device desined to confiure Cyclone II, Stratix II, and Cyclone devices EPCS64 16-Pin SOIC 3.3 V In-system prorammable 64-Mbit serial confiuration device desined to confiure Cyclone II, Stratix II, and Cyclone devices Note to Table 22: 1 SOIC: Small outline interated circuit. Table 23. Confiuration Devices for Stratix II, Stratix, Stratix GX, Cyclone II, Cyclone, APEX II, APEX, Excalibur, FLEX, Mercury & ACEX FPGAs DEVICE PIN/PACKAGE OPTIONS SUPPLY VOLTAGE EPC Pin PDIP 1, 20-Pin PLCC, 32-Pin TQFP 3.3 or 5.0 V EPC1 8-Pin PDIP, 20-Pin PLCC 3.3 or 5.0 V EPC2 20-Pin PLCC, 32-Pin TQFP 3.3 or 5.0 V DESCRIPTION 441-Kbit confiuration device desined to confiure all FLEX and ACEX devices 1-Mbit confiuration device desined to confiure APEX, FLEX, and ACEX devices In-system prorammable 1.6-Mbit confiuration device desined to confiure Stratix II, Stratix, Stratix GX, Cyclone II, Cyclone, APEX II, APEX, FLEX, Mercury TM, ACEX, and Excalibur TM devices EPC4 100-Pin PQFP 3.3 V In-system prorammable 4-Mbit confiuration device desined to confiure Stratix II, Stratix, Stratix GX, Cyclone II, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices EPC8 100-Pin PQFP 3.3 V In-system prorammable 8-Mbit confiuration device desined to confiure Stratix II, Stratix, Stratix GX, Cyclone II, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices EPC16 88-Pin BGA 2, 100-Pin PQFP 3.3 V In-system prorammable 16-Mbit confiuration device desined to confiure Stratix II, Stratix, Stratix GX, Cyclone II, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices Note to Table 23: 1 PDIP: plastic dual in-line packae. 2 Ultra FineLine BGA packae. Altera Offices Altera European Headquarters Altera Japan Ltd. Altera International Ltd. 101 Innovation Drive Holmers Farm Way Shinjuku i-land Tower 32F 2102 Tower 6 San Jose, CA Hih Wycombe 6-5-1, Nishi-Shinjuku The Gateway, Harbour City USA Buckinhamshire Shinjuku-ku, Tokyo Canton Road Telephone: (408) HP12 4XF Japan Tsimshatsui Kowloon United Kindom Telephone: (81) Hon Kon Telephone: (44) Telephone: (852) Copyriht All rihts reserved. Altera, the stylized Altera loo, specific device desinations, and all other words and loos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of in the U.S. and other countries. RapidIO is a trademark of the RapidIO Trade Association. HyperTransport is a trademark of the HyperTransport Consortium. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and forein patents and pendin applications, mask work rihts, and copyrihts. SG-COMP-14.1