Altera Product Overview. Altera Product Overview

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1 Altera Product Overview Tim Colleran Vice President, Product Marketing Altera Product Overview High Density + High Bandwidth I/O Programmable ASSP with CDR High-Speed Product Term Embedded Processor High Performance All Copper Low Cost 2.5 V Software Phase-Locked Loop CAM FIFO Multiplier CDR Termination Resistors Embedded Processors 1

2 Altera I/O Achievements 1 st 1 st 840-Mbps LVDS Support 1 st 1.8-V I/O Product-Term Family, SSTL-2/-3 1 st 1 st 1-Gbps LVDS Support 1.25-Gbps LVDS + CDR Support PLL 16 FLEX 10K 1 APEX 20KE 2000 MAX 7000B 2001 APEX II 2001 Mercury Typical Communications Datapath PMD 10-Gbps CDR Dedicated CDR Circuitry CDR Example: OC-12 Data Path SRAMs & SDRAMs Transceiver 622-MHz LVDS Half Rate Clock 311-MHz Clock Host Processor DDR, ZBT & QDR Interfacing Dedicated Timing Circuitry Multiple I/O Registers POS-PHY UTOPIA Flexbus Framer Half Rate Clock 311-MHz Clock Channels RapidIO HyperTransport 311-MHz Half Rate Clock HyperTransport Buffers Packet Processing CSIX HSTL Buffers Switch Fabric 2

3 The I/O All Stars APEX II: Complete I/O Flexibility Maximum Bandwidth in a PLD Broadest Protocol Support in a PLD Mercury: The Programmable ASSP Clock Data Recovery / SERDES Highest Performance PLD MAX 7000B I/O Super Glue Logic Intellectual Property A Key Ingredient for Success 3

4 APEX II I/O Support High-Speed I/O Capabilities 1-Gbps True-LVDS Solution, LVPECL, PCML & HyperTransport 624-Mbps, Flexible-LVDS Solution, LVPECL & HyperTransport RapidIO, UTOPIA IV, Flexbus CSIX, POS-PHY Level MHz HSTL Internal & External Memory Options 4-Kbit Memory Blocks with Bidirectional Read / Write Ports External Support for ZBT, DDR & QDR RAMs Maximized Chip-to-Chip Performance Clock-Data Synchronization 1-Gbps LVDS & LVPECL Up to 124 High-Speed Channels Programmable Output Drive APEX II Product Offerings Device Logic Elements RAM Bits LVDS Channels (Input/Output) 1-Gbps True-LVDS* 624-Mbps Flexible-LVDS** Max. User I/O Pins EP2A15 16, K 36 / / EP2A25 24, K 36 / / EP2A40 38, K 36 / / EP2A70 67,200 1,120K 36 / / 88 1,060 EP2A0 8,280 1,488K 36 / / 88 1,140 * True-LVDS Channels Also Support LVPECL, PCML & HyperTransport I/O ** Flexible-LVDS Channels Also Support LVPECL Inputs & HyperTransport I/O (3$6DPSOHV6KLSSLQJ 4

5 APEX II True-LVDS Circuitry Dedicated True-LVDS Circuitry Enables 1-Gbps Differential Signaling 36 Input & Output Channels per Device LVDS, LVPECL, PCML & HyperTransport Features 2 Improved & Independent Clock Domains Dedicated LVDS Circuitry General-Purpose Programmable Logic 1-Gbps 1-Bit Data 100-MHz Clock Deserializer (x8) 1-GHz Clock LVDS PLL (x10) (1-Gbps, x8 Example) System Logic Serializer (x8) 125-MHz 1-GHz Clock Clock LVDS PLL (x10) 1-Gbps 1-Bit Data 100-MHz Clock APEX II Clock-Data Synchronization CDS Circuitry Synchronizes True-LVDS Channels to System Clock Performed Independently on All Channels Source-Synchronous Transfer Limited to 2 Devices Clock Must Be Forwarded with Data Chip-to-Chip Transfer with CDS Unlimited Chip-to-Chip Communication $3(;.( $3(;.( Clock Clock 5

6 APEX II Phase-Locked Loops PLL PLL TxPLL TxPLL (8 Global Clocks) G3 G7 G1 G5 G2 G4 8 G2 G6 G0 G4 G1 G3 PLL PLL RxPLL RxPLL PLL Applications True-LVDS Double Data Rate I/O Flexible-LVDS Internal Clock Management Frequency Synthesis External System Clock Management Physical Layer I/O Standards General-Purpose PLL Dedicated LVDS PLL I/O Standards Supported I/O Standard LVPECL PCML HyperTransport HSTL Class I, II SSTL-2 2 Class I, II SSTL-3 3 Class I, II PCI-X Performance 1 Gbps 1 Gbps 1 Gbps 250 MHz 332 Mbps 167 MHz 133 MHz Type Differential Differential Differential Single-Ended Single-Ended Single-Ended Single-Ended 6

7 Complete Memory Solution Internal RAM Blocks 4 Kbits per Block True Dual-Port RAM Mode Packing Mode Mixed Port Widths External Memory Interfacing Memory Type ZBT SRAM SDR SDRAMs DDR SRAMs QDR SRAMs DDR SDRAMs Performance 200 MHz 200 MHz 334 Mbps 668 Mbps 334 Mbps QDR ESB DDR ZBT Unparalleled Total Device Bandwidth 1-Gbps True-LVDS 624-Mbps Flexible-LVDS 334-Mbps General-Purpose I/O 36 Input Channels 88 Input Channels 270+ Input Channels Up to 366 Gbps EP2A70 36 Output Channels 88 Output Channels 270+ Output Channels Compare Device Bandwidths Device True-LVDS Previously EP20K1500E 27 Gbps Today EP2A70 72 Gbps Flexible-LVDS Gbps General-Purpose Gbps Gbps Totals 137 Gbps 366 Gbps 7

8 The Mercury Solution = 1.25-Gbit CDR + PLD 125 Mbps 1.25 Gbps Data 125 Mbps 1.25 Gbps Data CDR Receive Dedicated Circuitry CDR Transmit Comma Detect Custom Logic Bandwidth- Optimized Programmable Logic Encode/ Decode DSP 8

9 Mercury Product Offerings The Programmable ASSP Device CDR Channels Logic Elements RAM Bits Max. User I/O EP1M , K 303 EP1M , K 486 (306DPSOHV6KLSSLQJ Mercury Clock-Data Recovery Single-Ended I/O Standards Single-Ended Standards Hit Noise Limitations at ~250 MHz 100 MHz 250 MHz Differential I/O Standards (LVDS) 100 Mbps 250 Mbps 500 Mbps 750 Mbps 1 Gbps Clock Data Recovery (CDR) CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCKCLOCKCLOCK Clock Skew Overwhelms Differential I/O Standards at ~ 1 Gbps CDR Eliminates Barriers 1.25 Gbps & Beyond 100 Mbps 250 Mbps 500 Mbps 750 Mbps 1 Gbps

10 Mercury 1M120 Vs. APEX 20KC Mercury on a 0.15-um Copper Process Is the World s Fastest PLD Performance (MHz) APEX 20KC 46% Performance Advantage 0.0 Quartus II v1.1 B111, Synplify v6.2r83 EP1M120 5 vs. EP20K100C-7/EP20K200C-7200C 7 Design High-Speed Serial Backplanes High-End Systems Exceed PCI Capabilities CDR Enables Multi-Crystal Operation CDR Enables High-Speed Backplanes Standardized Common Protocols & Implementations Backplane Mercury Device Proprietary Differentiation & Value Proposition for System Architects Serial Backplane Connection Multiple Line Cards with Independent Clocks 10

11 s Supported by Altera Standard POS-PHY Level 4 UTOPIA IV RapidIO Hyper- Transport 1G Ethernet Fibre Channel OC-12/SDH-4 SONET CSIX Bandwidth (Gbps) 10G 10G 16G 16G 1.25G 1G 0.622G 32G * Control Signal, ** Overhead Included Number Of Channels * * * Any Any Any 128 Needed I/O Performance (Mbps) ** 1,000 1,000 1,250 1, MHz I/O Standard LVDS LVDS LVDS Hyper- Transport LVDS + CDR LVPECL + CDR LVDS + CDR HSTL Mercury APEX II 11

12 MAX 7000B: I/O Standards Two I/O Blocks Can Be Configured Separately Programmable I/O Blocks GTL+ SSTL-3 Class I & II SSTL-2 Class I & II LVCMOS LVTTL Individual Power Buses,QFUHDVHG,23HUIRUPDQFH Unique Advanced I/O Support I/O Standard GTL+ SSTL-2 Class I & II SSTL-3 Class I & II LVTTL LVCMOS 5.0 V 3.3 V 2.5 V 1.8 V 64-Bit, 66-MHz PCI MAX 7000A (3.3 V) MAX 7000B (2.5 V) 12

13 Applications Processor GTL+ SDRAM SSTL 2/-3 LVTTL 2.5 V MAX 7000B 3.3 V PCI High-Bandwidth Communications GTL/GTL+ SSTL-3 I/O Standard Applications High-Speed Processor High-Speed Backplane Driver 125 MHz High-Speed Memory Interfacing to SDRAMs 150 MHz 13

14 Increasing s Ethernet POS-PHY AMBA OCP Infiniband UTOPIA Core Connect VCI PCI Flexbus Core Frame USB DDR/ QDR IPbus FISPbus Board-to-Board Chip-to-Chip On-Chip Bridging s with Altera Multiple s on Board Need for Altera to Bridge Different s Example: POS-PHY Level 3 to PCI Bridge ASSP: Proprietary ASIC: Different X X Y Y PMC Sierra POS-PHY 3 PCI ASIC with PCI 14

15 Atlantic Atlantic Is an on-chip PLD Packet-Based Full-Duplex, Synchronous Bus Protocol High Performance Simple to Implement Scalable Specification Available Today Supported by AMPP SM Partners POS-PHY PHY Atlantic UTOPIA High-Speed Megafunctions Atlantic POS-PHY Level 2, 3 & 4 Flexbus Level 3 & 4 UTOPIA Level 2 & 3 CSIX-L1 IX-Bus RapidIO HyperTransport 15

16 Looking Forward High-Speed I/O Roadmap 10.0 )XWXUH,,, CDR 10 Gbps Data Rate (Gbps) CDR 1.25 Gbps )XWXUH CDR Gbps )XWXUH,, CDR 6.4 Gbps.( True-LVDS 840 Mbps,, True-LVDS 1 Gbps

17 Proven High-Speed I/O Design Expertise 2.5-Gbps CDR Test Chip Gbps Chip in Joint Development 7HVW &KLS 1H[W *HQHUDWLRQ Mbps 1.25 Gbps 2.5 Gbps Gbps Altera s Complete I/O Solution Altera Enables High-Speed Communication among Multiple Devices Using Multiple Standards ASSP POS-PHY Level 4 UTOPIA IV Flexbus LVDS with CDS Flexible-LVDS HSTL APEX II Mercury PLDs External Memory Quad Data Rate Double Data Rate Zero Bus Turnaround GTL+ SSTL-2 SSTL-3 Product- Term PLDs Processor RapidIO HyperTransport PCI-X LVDS with CDR Mercury 17

18 Summary Altera Offers the Most Complete I/O for Programmable Logic The Technologies Are Unique Mercury Is the Only PLD with CDR Shipping in Volume APEX II Has the Broadest Differential I/O Support MAX 7000B Is I/O Leader for Product-Term Devices We Have the Tools, IP & Tech Support Team to Help Make You Successful 18

APEX II The Complete I/O Solution

APEX II The Complete I/O Solution July 2002 Altera introduces the APEX II device family: highperformance, high-bandwidth programmable logic devices (PLDs) targeted towards emerging network communications