Discontinued IP. Slices LUTs FFs

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1 0 MCH_OPB Synchronous DRAM (SDRAM) Controller (v1.00a) DS492 April 4, Introduction The Xilinx Multi-CHannel-OPB(MCH_OPB) SDRAM controller provides a SDRAM controller that connects to the OPB bus and multiple channel interfaces, and provides the control interface for SDRAMs. It is assumed that the reader is familiar with SDRAMs and the IBM PowerPC. Features The MCH_OPB SDRAM Controller is a soft IP core designed for Xilinx FPGAs and contains the following features: Parameterizable number of channel interfaces - each channel can be configured with a Xilinx Cachelink (XCL) protocol Optional OPB interface Performs device initialization sequence upon power-up and reset conditions Supports SDRAM self-refresh mode Performs auto-refresh cycles Supports single-beat and burst transactions Supports target-word first XCL cache-line transactions of 1,4,8, and 16 words Supports cacheline latencies of 2 or 3 set by a design parameter Supports various SDRAM data widths (8, 16, and 32 bits) set by a design parameter Operating frequency >=100MHz MCH_OPB SDRAM Controller Design Parameters To allow the user to obtain a MCH_OPB SDRAM Controller that is uniquely tailored for their system, certain features are parameterizable in the MCH_OPB SDRAM Controller design. This allows the user to have a design that only utilizes the resources required by their system and runs at the best possible performance. The features that are parameterizable in the MCH_OPB SDRAM Controller are shown in Table 1. Core Specifics Supported Device Family LogiCORE Facts Virtex -II Pro, Virtex-II, Virtex, Virtex-E, Spartan -II, Spartan-IIE, Spartan-3, Virtex 4 Version of Core sdram v1.00a Resources Used. For Spartan-3, see Table 11; for Virtex-II Pro, see Table 12; for Virtex-4, see Table 13. Slices LUTs FFs Min Max Block RAMs N/A N/A Documentation Design File Formats Constraints File Verification Instantiation Template Reference Designs Xilinx Implementation Tools Verification Simulation Synthesis Provided with Core VHDL N/A N/A N/A None Design Tool Requirements ISE 6.1i or later N/A ModelSim SE/EE 5.8e or later XST/Synplify Pro 7.5 or later Support Support provided by Xilinx, Inc Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS492 April 4,

2 Table 1: MCH_OPB SDRAM Controller Design Parameters Grouping SDRAM Controller Features Feature / Description Include support for OPB bursts Parameter Name C_INCLUDE_OPB_BURST_SUPPO RT (1) Allowable Values 0 = don t include logic to support OPB bursts 1 = include logic to support OPB bursts Default Value VHDL Type 0 integer Number of external C_NUM_BANKS_MEM (2) 1 1 integer SDRAM banks which require Chip Selects Target FPGA family C_FAMILY spartan2 virtex2p string spartan2e spartan3 virtex virtexe virtex2 virtex2p virtex4 Use positive edge output registers for SDRAM interface signals C_USE_POSEDGE_OUTREGS 0 = don t use positive edge output registers (SDRAM interface signals clocked on negative edge) 1 = use positive edge output registers (SDRAM interface signals clocked on positive edge) 0 integer Include pipeline stage to increase operating frequency (increases latency by 1 clock) C_INCLUDE_HIGHSPEED_PIPE (3) 0 = don t include pipeline stage 1 integer 1 = include pipeline stage 2 DS492 April 4, 2005

3 Table 1: MCH_OPB SDRAM Controller Design Parameters (Continued) Grouping Feature / Description Include OPB Slave Interface Arbitration Mode between OPB and MCH interfaces Parameter Name C_INCLUDE_OPB_IPIF C_PRIORITY_MODE Allowable Values 0 = don t include OPB IPIF 1 = include OPB IPIF 0 = fixed priority mode Default Value VHDL Type 1 integer 0 integer Address Space SDRAM Device Features Data bus width for the C_MCH_OPB_DWIDTH integer channels and the OPB interface if included in the design Address bus width for C_MCH_OPB_AWIDTH integer the channels and the OPB interface if included in the design Clock period (ps) C_MCH_OPB_CLK_PERIOD_PS integer Base Address for C_MEMx_BASEADDR (4,5) Valid std_logic_vector External Memory address Bank x (x = 0 ) High Address for C_MEMx_HIGHADDR (4,5) Valid std_logic_vector External Memory address Bank x (x = 0) Load Mode Register C_SDRAM_TMRD 2 integer command cycle time (Tck) Write Recovery Time C_SDRAM_TWR integer (ps) Read/Write command C_SDRAM_TCCD 1 integer to Read/Write command (Tck) Delay after ACTIVE C_SDRAM_TRAS integer command before PRECHARGE command (ps) Delay after ACTIVE C_SDRAM_TRC integer command before another ACTIVE or AUTOREFRESH command (ps) C_SDRAM_TRFC integer Delay after AUTOREFRESH before another command(ps) DS492 April 4,

4 Table 1: MCH_OPB SDRAM Controller Design Parameters (Continued) Feature / Grouping Description Parameter Name Auto-calcul ated parameters Simulation only Parameter Multi-Chan nel (MCH) Interface 2048, 4096, Delay after ACTIVE C_SDRAM_TRCD integer command before READ/WRITE command(ps) Delay after ACTIVE C_SDRAM_TRRD integer command for a row before an ACTIVE command for another row (ps) Delay after a C_SDRAM_TRP (6) integer PRECHARGE command (ps) Refresh command C_SDRAM_TREF 64 integer interval (ms) Number of Rows in a C_SDRAM_REFRESH_ 8192 integer Refresh Period NUMROWS (7) 8192, Self-Refresh Exit C_SDRAM_TXSR integer delay before issuing an ACTIVE command CAS Latency C_SDRAM_CAS_LAT 2,3 3 integer Total data width of C_SDRAM_DWIDTH (8) integer devices SDRAM address C_SDRAM_AWIDTH (9) See Note integer width SDRAM column C_SDRAM_COL_AWIDTH (9) See Note 9. 8 integer address width SDRAM bank address width C_SDRAM_BANK_AWIDTH (9) See Note 9. 2 integer Average periodic C_SDRAM_TREFI (10) C_SDRAM_ integer refresh command TREF/C_SD interval (ps) RAM_REFR ESH_ NUMROWS SDRAM simulation initialization time in picoseconds Number of MCH channels Interface protocol for channel x (x = 0 to 3) Depth of the Access buffer for channel x (x = 0 to 3) C_SIM_INIT_TIME_PS (11) integer C_NUM_CHANNELS integer C_MCHx_PROTOCOL (12,13) C_MCHx_ACCESSBUF_DEPTH (13,1 4) 0 = XCL 0 integer protocol 4,8,16 16 integer Depth of the ReadData Buffer for channel x (x = 0 to 3) C_MCHx_RDDATABUF_DEPTH (13,15 ) Allowable Values Default Value 0,4,8,16 16 integer VHDL Type 4 DS492 April 4, 2005

5 Table 1: MCH_OPB SDRAM Controller Design Parameters (Continued) Grouping XCL Channels Feature / Description Size of the cacheline in number of 32-bit words for each channel x configured as an XCL channel Type of write transactions for each channel x configured as an XCL channel Include Timeout Counter Parameter Name C_XCLx_LINESIZE (16) C_XCLx_WRITEXFER (16,17) C_INCLUDE_TIMEOUT_CNTR (18) Allowable Values Cacheline size in number of 32-bit words. Allowed entries are 1,4,8,16 0 = no write transfers 1= single transfers only 2 = cacheline transfers only 0 = don t include an acknowledge timeout counter Default Value VHDL Type 4 integer 1 integer 0 integer DS492 April 4,

6 Table 1: MCH_OPB SDRAM Controller Design Parameters (Continued) Feature / Allowable Default Grouping Description Parameter Name Values Value VHDL Type Number of clocks to wait for a transfer acknowledge from the SDRAM controller before issuing a timeout error C_TIMEOUT (18) integer Notes: 1. Set C_INCLUDE_OPB_BURST_SUPPORT=1to support OPB sequential address transactions.if C_INCLUDE_OPB_IPIF=0, then this parameter is not used. 2. C_NUM_BANKS_MEM specifies the number of external SDRAM memory banks with identical device characteristics that require separate address space and chip select. Currently, only one external SDRAM memory bank is supported. The C_NUM_BANKS_MEM parameter specifies the size of the SDRAM_CSn signal(s). All the SDRAM device characteristics specified in the SDRAM Device Feature parameters are applicable for all memory banks. Note that the optimal performance is obtained when C_NUM_BANKS_MEM is Set this parameter to 0 if C_USE_POSEDGE_OUTREGS = This design can accommodate only one external SDRAM memory bank. Only C_MEM0_BASEADDR and C_MEM0_HIGHADDR are used. 5. The range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must comprise a complete, contiguous power of two range such that range = 2 m, and the m least significant bits of C_MEMx_BASEADDR must be zero. 6. Manual precharge timing numbers should be used for this parameter if the SDRAM data sheet has different timing numbers for manual and auto precharge. 7. This parameter is used to calculate the refresh command interval and therefore should be set to the number of rows in a refresh period, which is not always the same as the number of rows in the SDRAM device. Check the data sheet carefully for this parameter. 8. For this early access release, the only supported data width of SDRAM devices is 32. In future releases, the data width of SDRAM devices must be >= 8 and : a. = MCH_OPB data width OR b. = MCH_OPB data width/2 OR c. = MCH_OPB data width/4 9. C_SDRAM_AWIDTH + C_SDRAM_COL_AWIDTH + C_SDRAM_BANK_AWIDTH + log2(c_sdram_dwidth/8) must be < C_MCH_OPB_AWIDTH These parameters are automatically calculated by the system generation tool and are not input by the user. 11. This parameter is used to change the SDRAM time for simulation only. Note, the SDRAM requires ~300 ns after this initialization time to complete the initialization sequence. Also note that if this parameter is modified from the default of 100 us, simulation results will vary from hardware implementation. 12. Only the Xilinx Cachelink Protocol (XCL) is supported at this time. 13. This design can accommodate up to 4 channels. The generics associated with the MCH interfaces are designated with a C_MCHx prefix where x = 0 to The depth of the Access Buffer must be at least large enough to hold a cacheline write, i.e. C_MCHx_ACCESS_BUF_DEPTH must be >= C_XCLx_LINESIZE for optimal performance 15. If the master connecting to this channel can consume data as soon as its available (i.e. instruction cache masters), the ReadData buffer depth can be set to zero to save resources and eliminate the latency through the ReadData buffer. Otherwise, the ReadData buffer depth must be sized to accommodate any latency the master may have in reading data from this buffer. 16. This design can accommodate up to 4 channels. The generics associated with the channels configured with a XCL protocol are designated with a C_XCLx prefix where x = 0 to 3. If C_MCH_PROTOCOL_ARRAY(x)=XCL, then the generics with a C_XCLx prefix are used. If C_MCH_PROTOCOL_ARRAY(x) <> XCL, then the generics with a C_XCLx prefix are unused. 17. If the master connecting to channel x will only perform read transfers (i.e. instruction cache masters) set C_XCLx_WRITEXFER to 0 to save resources. 18. The timeout counter is not available in this release. The only allowed value for C_INCLUDE_TIMEOUT_CNTR is Allowable Parameter Combinations Note that it is assumed that all external memory banks are accessible through the MCH interfaces and are also accessible through the OPB interface if the design has been parameterized to include the OPB interface. The OPB slave interface is only included in this design if C_INCLUDE_OPB_IPIF is set to 1. When C_INCLUDE_OPB_IPIF = 0, the C_INCLUDE_OPB_BURST_SUPPORT is unused. 6 DS492 April 4, 2005

7 The only channel transfer protocol supported at this time is the Xilinx Cachelink (XCL) interface. The parameters to configure a Dynamic Address Generator (DAG) channel are unused and are only documented here for future reference. If an XCL channel is connected to a master that will only perform read transactions, then C_XCLx_WRITEXFER should be set to 0 indicating that no write transfers will be performed. This will reduce the channel logic to only contain logic for read transactions. Also, if an XCL channel is connected to a master that can consume data as soon as its available, then C_MCHx_RDDATABUF_DEPTH for that channel should be set to zero. This will eliminate the read data buffer and eliminate the latency that would normally exist in reading data from this buffer. If the master can not consume data as soon as its available, then C_MCHx_RDDATABUF_DEPTH for that channel should be set to accommodate any latency the master has in reading data from the ReadData Buffer. Optimal performance will be achieved when the buffer depth of the Access Buffer is set greater than or equal to the line size of the channel (C_MCHx_ACCESSBUF_DEPTH >= C_XCLx_LINESIZE). Table 2 provides a summary of all MCH_OPB SDRAM Controller input/output (I/O) signals, the interfaces under which they are grouped, and a brief description of the signals. Table 2: MCH_OPB Controller Pin Descriptions Grouping Signal Name Interface I/O System Signals SDRAM Signals Timer Interrupt Signal Initial State Description MCH_OPB_Clk System I XCL and OPB Clock MCH_OPB_Rst System I XCL and OPB Reset SDRAM_Clk SDRAM O 0 SDRAM Clock SDRAM_CKE SDRAM O 0 SDRAM Clock Enable SDRAM_CSn(0 to C_NUM_BANKS_MEM-1) SDRAM O 1 Active low SDRAM chip select SDRAM_RASn SDRAM O 1 Active low SDRAM row address strobe SDRAM_CASn SDRAM O 1 Active low SDRAM column address strobe SDRAM_WEn SDRAM O 1 Active low SDRAM write enable SDRAM_DQM SDRAM O 0 SDRAM data mask SDRAM_BankAddr SDRAM O 0 SDRAM bank address SDRAM_Addr SDRAM O 0 SDRAM address SDRAM_DQ_o SDRAM O 0 Output data to SDRAM SDRAM_DQ_i SDRAM I Input data from SDRAM SDRAM_DQ_t SDRAM O 0 3-state control for SDRAM data buffers SDRAM_Clk_in SDRAM I SDRAM clock feedback. If there is no feedback from the SDRAM clock output, connect to. SDRAM_Init_Done Preliminary System O Release 0 SDRAM initialization/wakeup has completed. DS492 April 4,

8 Table 2: MCH_OPB Controller Pin Descriptions (Continued) Grouping Signal Name Interface I/O SDRAM Self-Refre sh Mode Control (1) OPB Slave Signals (2,3) Initial State SDRAM_Sleep System I Rising edge on this signal enters the SDRAM self-refresh mode. A minimum period of 50uS after the assertion of SDRAM_Sleep is required before MCH_OPB_Rst can be asserted. SDRAM_WakeUp System I This signal indicates whether the SDRAM must go through the power-up initialization after reset, or if only the sequence to exit the self-refresh mode needs to be executed. This signal is sampled when reset negates and therefore should be asserted XXX before MCH_OPB_Rst negates. OPB_Select OPB I OPB select OPB_RNW OPB I OPB read,not write OPB_ABus[0:C_MCH_OPB_AWIDTH-1] OPB I OPB address bus OPB_DBus[0:C_MCH_OPB_DWIDTH-1] OPB I OPB data bus Description OPB_BE[0:C_MCH_OPB_DWIDTH/8-1] OPB I OPB byte enables OPB_seqAddr OPB I OPB sequential address Sl_xferAck OPB O 0 SDRAM Controller transfer acknowledge Sl_errAck OPB O 0 SDRAM Controller error acknowledge Sl_toutSup OPB O 0 SDRAM Controller timeout suppress Sl_retry OPB O 0 SDRAM Controller retry Sl_DBus[0:C_MCH_OPB_DWIDTH-1] OPB O 0 SDRAM Controller OPB slave data bus IP2INTC_IRPT OPB O 0 Interrupt output to microprocessor interrupt input or system interrupt controller. Registered level type, active high. 8 DS492 April 4, 2005

9 Table 2: MCH_OPB Controller Pin Descriptions (Continued) Grouping Signal Name Interface I/O MCH Interface MCHx_Access_Control (x = 0 to 3) MCHx_Access_Data(0:C_MCH_OPB_D WIDTH-1) (x = 0 to 3) MCHx_Access_Write (x = 0 to 3) MCHx_Access_Ful (x = 0 to 3)l MCHx_ReadData_Control (x = 0 to 3) MCHx_ReadData_Data(0:C_MCH_OPB _DWIDTH-1) (x = 0 to 3) MCHx_ReadData_Read (x = 0 to 3) MCHx_ReadData_Exists (x = 0 to 3) Parameter- Port Dependencies Initial State Description MCH I Control signal to the Access buffer of MCH interface x (x = 0 to 3). This signal indicates the type of access to be performed (read or write) and the size of the access (byte, halfword, or word). MCH I Write Data to the Access buffer of MCH interface x (x = 0 to 3). MCH I Write signal to the Access buffer of MCH interface x (x = 0 to 3). MCH O 0 Indicator that the Access buffer of MCH interface x is full (x = 0 to 3). MCH O 1 Control signal for the ReadData buffer of MCH interface x (x = 0 to 3). This signal indicates if the data from the ReadData buffer is valid. MCH O Zeros Read data from the ReadData buffer of MCH interface x ( x = 0 to 3). MCH I Read signal to the ReadData buffer of MCH interface x ( x = 0 to 3). MCH O 0 Indicator that the ReadData buffer of MCH interface x is non-empty (x = 0 to 3). Notes: 1. See the section, Supporting the SDRAM Self-Refresh Mode, for information on the use of these signals. 2. Please refer to the IBM OPB Bus Architecture Specification for more detailed information on these signals. 3. The signals in this section are unused if C_INCLUDE_OPB_IPIF=0. The inputs are ignored and the outputs are driven to zero. The dependencies between the MCH_OPB SDRAM Controller design parameters and I/O signals are shown in Table 3. It gives information about how the ports and parameters get affected by changing certain parameters. Table 3: MCH_OPB Parameter-Port Dependencies Parameter Affects Name Description C_SDRAM_AWIDTH Ports SDRAM_Addr C_SDRAM_BANK_AWIDTH Ports SDRAM_BankAddr C_SDRAM_DWIDTH Ports SDRAM_DQM SDRAM_DQ_o SDRAM_DQ_i SDRAM_DQ_t DS492 April 4,

10 Table 3: MCH_OPB Parameter-Port Dependencies (Continued) Parameter Affects Name Description C_NUM_BANKS_MEM Ports SDRAM_CSn Parameters C_MEMx_BASEADDR C_MEMx_HIGHADDR C_MEMx_CS_LEVEL C_USE_POSEDGE_OUTREGS Ports SDRAM_CSn Parameters C_INCLUDE_OPB_IPIF Ports OPB_Select OPB_RNW OPB_ABus OPB_DBus OPB_BE Parameters C_INCLUDE_HIGHSPEED_PIPE Sl_xferAck Sl_errAck Sl_toutSup Sl_retry Sl_DBus IP2Bus_IntrEvent IP2INTC_Irpt C_INCLUDE_OPB_BURST_SUP PORT C_NUM_CHANNELS Ports MCHx_Access_Control MCHx_Access_Data(0:C_MCH_ OPB_DWIDTH-1) MCHx_Access_Write MCHx_Access_Full MCHx_ReadData_Control MCHx_ReadData_Data(0:C_MC H_OPB_DWIDTH-1) MCHx_ReadData_Read MCHx_ReadData_Exists Parameters C_MCHx_PROTOCOL C_MCHx_ACCESSBUF_DEPTH C_MCHx_RDDATABUF_DEPTH If C_INCLUDE_OPB_IPIF=0, OPB Inputs are unused If C_INCLUDE_OPB_IPIF=0, OPB Outputs tied to logic 0 If C_INCLUDE_OPB_IPIF=0, IPIC interrupt inputs are unused and the OPB IPIF interrupt output is tied to logic 0 If C_INCLUDE_OPB_IPIF=0, this generic is unused. If x is > C_NUM_CHANNELS-1, then the inputs associated with MCH interface x are unused and the outputs are grounded. C_XCLx_LINESIZE C_XCLx_WRITEXFER If x is > C_NUM_CHANNELS-1, then the parameters associated with MCH interface x are unused DS492 April 4, 2005

11 Table 3: MCH_OPB Parameter-Port Dependencies (Continued) Parameter Affects Name Description C_MCHx_PROTOCOL Parameters C_XCLx_LINESIZE C_XCLx_WRITEXFER C_MCH_OPB_DWIDTH Ports MCHx_Access_Data(0:C_MCH_ OPB_DWIDTH-1) MCHs_ReadData_Data(0:C_MC H_OPB_DWIDTH-1) C_MCH_OPB_AWIDTH Ports OPB_ABus(0:C_MCH_OPB_AWI DTH-1) Connecting to Memory Memory Data Types and Organization If C_MCHx_PROTOCOL <> XCL, then generics with C_XCLx prefix are unused. SDRAM memory can be accessed as: byte (8 bits), halfword (2 bytes), or word (4 bytes)depending on the size of the bus to which the processor is attached.from the point of view of themch and OPBdata is organized as big-endian. The bit and byte labeling for the big-endian data types is shown below in Figure 1. DS492 April 4,

12 Figure 1: Big-Endian Data Types Memory to MCH_OPB SDRAM Controller Connections The data and address signals at the memory controller are labeled with big-endian bit labeling (for example, D(0:31), D(0) is the MSB), whereas most memory devices are either endian agnostic (they can be connected either way) or little-endian D(31:0) with D(31) as the MSB. SDRAM devices tend to use little-endian labeling. This distinction is important since the bits of the address bus actually contain the data value used to program the SDRAM mode register. Caution must be exercised with the connections to the external SDRAM memory devices to avoid incorrect data and address connections. Table 4 shows the correct mapping of SDRAM memory controller pins to SDRAM memory device pins DS492 April 4, 2005

13 Table 4: Example Signal to Device Pin Mapping (32M X 8) SDRAM Signal (Big-Endian) Memory Device Signal (Little-Endian) SDRAM_Addr(0) A12 SDRAM_Addr(1) A11 SDRAM_Addr(2) A10 SDRAM_Addr(3) A9 SDRAM_Addr(4) A8 SDRAM_Addr(5) A7 SDRAM_Addr(6) A6 SDRAM_Addr(7) A5 SDRAM_Addr(8) A4 SDRAM_Addr(9) A3 SDRAM_Addr(10) SDRAM_Addr(11) SDRAM_Addr(12) SDRAM_BankAddr(0) SDRAM_BankAddr(1) SDRAM_DQ(0) SDRAM_DQ(1) SDRAM_DQ(2) SDRAM_DQ(3) SDRAM_DQ(4) SDRAM_DQ(5) SDRAM_DQ(6) SDRAM_DQ(7) SDRAM_DQM(0) SDRAM_DQM(1) A2 A1 A0 BA1 BA0 D7 D6 D5 D4 D3 D2 D1 D0 DQMU DQML SDRAM Address Mapping An address offset is calculated based on the width of the SDRAM data bus and the MCH_OPBdata bus. The SDRAM column address is then mapped to the MCH_OPB address bus, followed by the row address and bank address. The difference in these offsets are set to zero. This sends the proper column address to the SDRAM. Since the SDRAM will always be accessed to provide data the width of the MCH_OPB bus, the column address starting bit is based on the SDRAM data width offset and the column address ending bit is based on the MCH_OPB data width offset. DS492 April 4,

14 The MCH_OPB address bus bit locations for the SDRAM column, row, and bank addresses are calculated as shown in Table 5 and Table 6. Table 5: SDRAM Address offset calculations Variable SDRAM_ADDR_OFFSET _ADDR_OFFSET COLADDR_STARTBIT COLADDR_ENDBIT NUM_ZEROADDR_BITS ROWADDR_STARTBIT ROWADDR_ENDBIT BANKADDR_STARTBIT BANKADDR_ENDBIT log2(c_sdram_dwidth/8) log2(c_ MCH_OPB_DWIDTH/8) Equation C_MCH_OPB_AWIDTH - (C_SDRAM_COL_AWIDTH+SDRAM_ADDR_OFFSET) C_MCH_OPB_AWIDTH-MCH_OPB_ADDR_OFFSET-1 MCH_OPB_ADDR_OFFSET-SDRAM_ADDR_OFFSET COLADDR_STARTBIT - C_SDRAM_AWIDTH ROWADDR_STARTBIT + C_SDRAM_AWIDTH-1 ROWADDR_STARTBIT - C_SDRAM_BANK_AWIDTH BANKADDR_STARTBIT + C_SDRAM_BANK_AWIDTH-1 Table 6: SDRAM - MCH_OPB Address Bus Assignments SDRAM Address Column Address Row Address Bank Address MCH_OPB Address Bus MCH_OPB_ABus(COLADDR_STARTBIT to COLADDR_ENDBIT) & NUM_ZEROADDR_BITS MCH_OPB_ABus(ROWADDR_STARTBIT to ROWADDR_ENDBIT) MCH_OPB_ABus(BANKADDR_STARTBIT to BANKADDR_ENDBIT) Table 7 and Table 8 show an example of the mapping between the MCH_OPB address and the SDRAM address when the data width of the SDRAM is 16 and the data width of the bus is 32, the column address width is 9, the row address width is 13, and the bank address width is 2. Note that since the MCH_OPB data width is 32, its address offset is 2 where the SDRAM address offset is 1. Therefore, the column address is MCH_OPB address bus bit 22 through bit 29 with a concatenated zero. Table 7: MCH_OPB Example SDRAM Address offset calculations Variable Value SDRAM_ADDR_OFFSET log2(16/8) = 1 MCH_OPB_ADDR_OFFSE T log2(32/8) = 2 COLADDR_STARTBIT 32 - (9+1) = 22 COLADDR_ENDBIT = 29 NUM_ZEROADDR_BITS 2-1 = 1 ROWADDR_STARTBIT = 9 ROWADDR_ENDBIT Preliminary = 21 Release BANKADDR_STARTBIT 9-2 = 7 BANKADDR_ENDBIT = DS492 April 4, 2005

15 Table 8: SDRAM - MCH_OPB Address Bus Assignments SDRAM Address OPB Address Bus Column Address MCH_OPB_ABus(22: 29) & 0 Row Address MCH_OPB_ABus(9:21) Bank Address MCH_OPB_ABus(7:8) SDRAM Controller Design Supporting the SDRAM Self-Refresh Mode The SDRAM controller can be instructed to place the SDRAM memory into Self-Refresh mode. This mode is useful because the SDRAM memory will maintain its data contents and issue its own refresh signals, allowing the controller and the rest of the system to be reset. Two inputs to the SDRAM controller are used to support the SDRAM Self-Refresh Mode, SDRAM_Sleep and SDRAM_WakeUp. These are discrete input signals and must be generated at the system level, they are not derived from the OPB or MCH interfaces. A rising edge of the SDRAM_Sleep signal will cause the SDRAM controller to execute the command sequence required to place the SDRAM into Self-Refresh. MCH_OPB_Rst is then asserted to place the entire system into reset. A minimum period of 50uS from the assertion of SDRAM_Sleep to the assertion of MCH_OPB_Rst is required to insure the SDRAM is in the Self-Refresh mode. Note that the SDRAM controller does not provide the timing for the reset assertion, this should be done at the system level. Please refer to Figure 2 for information on the timing relationships of these signals. MCH_OPB_Clk A=50 us minimum delay from asserting SDRAM_Sleep before MCH_OPB_Rst can be asserted A MCH_OPB_Rst SDRAM_Sleep SDRAM_Wakeup SDRAM_CMD NOP ACT NOP WRITE NOP PRE NOP RFSH NOP SDRAM_CKE SDRAM_CSn SDRAM_RASn SDRAM_CASn SDRAM_WEn Figure 2: Entering SDRAM Self-Refresh Mode The SDRAM_WakeUp signal is used to inform the SDRAM controller if the power-up intialization sequence needs to be performed, or if the sequence to instruct the SDRAM to exit Self-Refresh needs to be performed. If the SDRAM_WakeUp signal is negated when MCH_OPB_Rst Preliminary negates, the SDRAM controller will perform Release the SDRAM intialization sequence. If the SDRAM_WakeUp signal is asserted when MCH_OPB_Rst negates, the SDRAM controller will instruct the SDRAM to exit the Self-Refresh mode. Note that the SDRAM_WakeUp signal must be at its desired level at least 5 clock periods before DS492 April 4,

16 MCH_OPB_Rst negates. It is assumed that the clock is stable before MCH_OPB_Rst negates. Please refer tofigure 3 for information on the timing relationships of these signals. MCH_OPB_Clk A = SDRAM_Wakeup setup time to negation of reset Assumes clock is stable when reset is negated Txsr=Time to exit Self Refresh mode A Txsr MCH_OPB_Rst SDRAM_Sleep SDRAM_Wakeup SDRAM_CMD NOP RFSH SDRAM_CKE SDRAM_CSn SDRAM_RASn SDRAM_CASn SDRAM_WEn Block Diagram Figure 3: Exiting SDRAM Self-Refresh Mode The MCH_OPB SDRAM Controller consists of the MCH_OPB IPIF to provide the bus protocol and Multi-CHannel (MCH) interface, three state machines to control the SDRAM operation, an I/O module to instantiate the SDRAM I/O registers for the SDRAM data interface, and a clock generation module. The MCH_OPB SDRAM Controller block diagram is shown in Figure 4. The separation of the Command State Machine and the Data State Machine allows for the application of commands to the SDRAM while data reception/transmission is in progress. Overlapping the SDRAM commands with the data transfer when accessing data in the same row of the same bank allows for more optimal SDRAM operation. Note that if C_INCLUDE_HIGHSPEED_PIPE=1, then registers are inserted in the Command State Machine block to register the SDRAM interface signals between the state machine and the IO registers. If the IO Registers are clocked on the falling edge of the clock (C_USE_POSEDGE_OUTREGS=0), this stage of registers provides a positive-edge register to a falling-edge register path to help increase Fmax, but will increase latency. If the IO Registers are clocked on the positive-edge of the clock (C_USE_POSEDGE_OUTREGS=1), then the advantage of these registers is minimal, so for most systems, these registers should not be included to avoid the increase in latency DS492 April 4, 2005

17 MCH_0 MCH_1 Data State Machine Write_Data, Write_Data_EN Write_dqs_en, Write_data_mask SDRAM_DQ_o SDRAM_DQ_t MCH_n IPIC IP IF In te rfa ce Read_Data Read_Data_EN SDRAM_DQ_i SDRAM_DQM MCH_OPB_IPIF Command State Machine RASn,CASn,WEn Addr BankAddr IO Reg SDRAM_Addr SDRAM_BankAddr SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_CSn OPB SDRAM_Sleep High Speed Pipeline Regs SDRAM_WakeUp SDRAM_Init_done Init State Machine SDRAM_CKE Clk MCH_OPB_Clk SDRAM_Clk_in Clock Generation SDRAM_Clk OPTIONAL BLOCK SDRAM_CONTROLLER MCH_OPB_SDRAM Figure 4: MCH_OPB SDRAM Controller Block Diagram DS492 April 4,

18 MCH_OPB_IPIF The MCH_OPB_IPIF provides an interface to the MCH interfaces and an optional interface to the OPB. Please refer to the Xilinx MCH_OPB_IPIF (DS494) for detailed information of this module. Init State Machine SDRAMs must be powered up and initialized in a predefined manner specified in the SDRAM device data sheet. Once power has been applied and the clock is stable, the SDRAM requires a 100uS delay prior to issuing any command other than a COMMAND INHIBIT or a NOP. If the SDRAM is in a self-refresh mode, a specific sequence of commands is required to instruct the SDRAM to exit the self-refresh mode. The Init State Machine controls the SDRAM power-up initialization sequence as well as the command sequence required to instruct the SDRAM to exit the self-refresh mode. Figure 5 shows the state diagram of the Init State Machine. While RESET is asserted, the Init State Machine stays in the IDLE state. If the SDRAM_WAKEUP signal is asserted when RESET negates, the SDRAM needs to exit the self-refresh mode. The Init State Machine does not execute the normal SDRAM initialization sequence, but instead issues the sequence of commands to make the SDRAM properly exit the self-refresh mode. During the process of exitting the self-refresh mode, the MCH_OPB SDRAM will respond to accesses by asserting. The INIT_DONE signal is asserted when the SDRAM is no longer in the self-refresh mode. If the SDRAM_WAKEUP signal is negated when RESET negates, the Init State Machine provides the 100uS delay and the sequencing of the required SDRAM power-up commands. It instructs the Command State Machine to send the proper commands in the proper sequence to the SDRAM. This state machine starts execution after RESET and returns to the IDLE state when RESET is applied. For a typical SDRAM ~300 ns is required after the 100 us reset / power-up time to complete the power-up initialization sequence. During the initialization sequence, the MCH_OPB SDRAM Controller will respond to accesses by asserting. When the initialization sequence has been completed, the INIT_DONE signal asserts. Note that after RESET has been applied, the 100 us delay is again implemented before any commands are issued to the SDRAM. For simulation purposes, the 100 us reset / power-up delay can be modified by the parameter C_SIM_INIT_TIME_PS. Approximately 300 ns after delay specified by C_SIM_INIT_TIME_PS, the initialization sequence is complete DS492 April 4, 2005

19 Note: If C_SIM_INIT_TIME_PS is modified from (100 us), the simulation behavior will vary from the hardware implementation results during initialization. The simulation will no longer be reflecting the hardware behavior during this time. reset*sdram_wakeup* t100us_end IDLE reset*sdram_wakeup PRECHARGE1 cmd_done WAIT_TXSR REFRESH1 REFRESH2 cmd_done cmd_done txsr_end REFRESH_SNG cmd_done SET_OP_DONE reset Command State Machine Figure 5: MCH_OPB SDRAM Init State Machine The Command State Machine provides the address bus and commands signals to the SDRAM. It sends the Pend_write and Pend_Read signals to the Data State Machine to start the reception/transmission of data. When a rising edge is detected on the SDRAM_SLEEP signal, the Command State Machine will issue first close all rows in all banks by issuing a PRECHARGE ALL command. The REFRESH command is the issued with the SDRAM_CKE signal negated to put the SDRAM into the Self-Refresh mode. The SDRAM must remain in the Self-Refresh mode for a minimum of TRAS ns. The Command State Machine remains in the SELF_REFRESH state until RESET is asserted. RESET can not assert until at least 50uS after the SDRAM_SLEEP signal asserts to insure that the SDRAM has successfully entered the Self-Refresh mode. DS492 April 4,

20 A simplified version of the Command State Machine is shown in Figure 6. For readability, only the major state transitions are shown. Note that if C_INCLUDE_HIGHSPEED_PIPE=1, the SDRAM signals output from this state machine are registered, otherwise they are not to reduce latency. trp * trc_end load_mr IDLE trefi end + refresh LOAD_MR_CMD tmrd_end trfc_end REFRESH_CMD Burst * Read_op* Same_row trcd_end * read_state * data_done tcrd_end *(Pend_rdreq + Read_op) READ_CMD done * Same_row * Same_bank * trrd_end done * Same_row * Same_bank * trrd_end ACT_CMD Bus2IP_CS * INIT_DONE Bus2IP_CS trcd_end * (Pend_wrreq + Write_op) trrd_end done * Same_row * Same_bank * trrd_end WAIT_TRRD WRITE_CMD done * Same_row * Same_bank * tras_end done * twr_end done * Same_row * Same_bank * twr_end done * tras_end trfi_end * tras_end WAIT_TRAS SELF_REFRESH_CMD Write_op * Same_row Twr-end * tras_end WAIT_TWR done * Same_row * Same_bank * trans_end done * tras_end trfi_end * tras_end tras_end PRECHARGE_CMD twr_end * trass_end precharge Data State Machine Figure 6: MCH_OPB SDRAM Command State Machine The Data State Machine transfers the data to/from the SDRAM and determines when the specified SDRAM burst is complete. It monitors the PEND_READ and PEND_WRITE signals from the Command State Machine and BUS2IP_Burst from the IPIF to know if more data transmissions are required. It waits for CAS_LATENCY during read operations and signals when the SDRAM has completed the data transfer for both read and write operations. The Data State Machine is shown in Figure DS492 April 4, 2005

21 Figure 7: MCH_OPB SDRAM Data State Machine Clock Generation The Clock Generation module simply passes the SDRAM_Clk_in clock to the SDRAM_Clk output clock as shown in Figure 8. It also passes the MCH_OPB_Clk through to the Sys_Clk output to clock the rest of the SDRAM controller logic. DS492 April 4,

22 MCH_OPB_Clk Clk SDRAM_Clk_in SDRAM_Clk SDRAM Clocking Options Clock Generation Figure 8: Clock Generation To synchronize the SDRAM clock to the internal FPGA clock, the FPGA system design should include a DCM external to the SDRAM core that uses the SDRAM clock input as the feedback clock as shown in Figure 9. This means that the SDRAM clock output from the FPGA must be routed back to the FPGA on a clock pin with a connection to a DCM clock feedback input. The output from the DCM in the FPGA should be connected to the SDRAM_Clk_in input to the SDRAM controller core. Clk External Clock CLKIN CLK0 MCH_OPB_Clk CLKIN CLK0 SDRAM_Clk_in SDRAM_Clk CLKFB DCM CLK90 BUFG SDRAM_Clk_fb CLKFB DCM CLK90 OBUF FPGA SDRAM Core SDRAM_Clk Figure 9: SDRAM Clocked by FPGA output with feedback Clk SDRAM 22 DS492 April 4, 2005

23 If the SDRAM is clocked by the same external clock as the FPGA, or if the SDRAM clock feedback is not available, the DCM shown in Figure 10 or Figure 11 should be included in the FPGA external to the SDRAM core. The SDRAM_Clk_in input to the SDRAM core should be connected to MCH_OPB_Clk. NOTE: If DLLs are used, the designer must reference XAPP132 v2.4, "Using the Virtex Delay-Locked Loop" for the correct DLL implementation. Clk External Clock CLKIN CLK0 MCH_OPB_Clk SDRAM_Clk_in SDRAM_Clk CLKFB CLK90 BUFG OBUF DCM FPGA SDRAM Core Clk SDRAM Figure 10: SDRAM Clocked by external clock Clk External Clock CLKIN CLK0 MCH_OPB_Clk SDRAM_Clk_in SDRAM_Clk CLKFB CLK90 BUFG OBUF DCM FPGA SDRAM Core Clk SDRAM Figure 11: SDRAM clocked by FPGA output - no feedback available DS492 April 4,

24 I/O Registers Control Signals All control signals and the address bus to the MCH_OPB SDRAM are registered in the IOBs of the FPGA. Write Data Path The MCH_OPB SDRAM I/O registers are used to output the write data to the MCH_OPB SDRAM using either the rising or the falling edge of the clock as determined by the C_USE_POSEDGE_OUTREG parameter. Read Data Path The SDRAM I/O registers are used to input data from the SDRAM. These registers are always closed on the rising edge of the clock. MCH_OPB SDRAM Latency Table 9 shows the latency calculations for a 32-bit SDRAM. Table 9: MCH_OPB_SDRAM Latency calculation for 32-bit SDRAM Transaction Type XCL Single Write XCL Cacheline Write XCL Cacheline Read OPB Single Write OPB Single Read Parameter Address and First Data Word in Access Buffer To Transfer Complete Address and First Data Word in Access Buffer To Transfer Complete Address in Access Buffer To Transfer Complete OPB_select To Transfer Complete OPB_select To Transfer Complete MCH_OPB Latency (Number Of MCH_OPB Clocks) 5 + Trcd Clock Periods + Twr Clock Periods 4 + Trcd Clock Periods + Twr Clock Periods + cacheline_size 8 + CAS Latency + Trcd Clock Periods + cacheline_size 9 + Trcd Clock Periods + Twr Clock Periods 11 +Trcd Clock Periods + CAS Latency OPB (1) OPB (1) cacheline_size 11 + cacheline_size 8 + cacheline_size 12 + cacheline_size OPB (1) 9 + cacheline_size 13 + cacheline_size 24 DS492 April 4, 2005

25 Table 9: MCH_OPB_SDRAM Latency calculation for 32-bit SDRAM Transaction Type OPB Cacheline/ Burst Write OPB Cacheline/ Burst Read SDRAM Timing Diagrams Timing convention abreviations are shown in Table 10 Table 10: SDRAM Timing convention Timing Name Trcd Tref Trfc Trrd Tras Twr Trp Trc Parameter OPB_select To Transfer Complete OPB_select To Transfer Complete Description MCH_OPB Latency (Number Of MCH_OPB Clocks) 11 + Trcd Clock Periods + Twr Clock Periods + burst_size 10 + CAS Latency + Trcd Clock Periods + burst_size Notes: 1. Trcd = 20ns, Twr = 15ns, CAS Latency = 2 2. Arbitration time between XCL Channels and the OPB is not included. 3. Arbitration time on the OPB between multiple OPB Masters is not included. 4. Cacheline size as set by C_XCL_LINESIZE. 5. OPB burst size is the number of data beats in the sequential address transaction. ACTIVE TO READ or WRITE Delay REFRESH PERIOD AUTO REFRESH PERIOD ACTIVE BANK A TO ACTIVE BANK B COMMAND ACTIVE TO PRECHARGE COMMAND WRITE TO PRECHARGE PRECHARGE TO ACTIVE OPB (1) OPB (1) 13 + burst_size 15 + burst_size 16 + burst_size 13 + burst_size 14 + burst_size 15 + burst_size Time interval between successive ACTIVE commands in the same Bank OPB (1) DS492 April 4,

26 XCL Protocol Single Write Timing Diagram Figure 12 shows an XCL protocol channel performing a single write. Clock MCH_Access_Write MCH_Access_Control MCH_Access_Data[0:31] MCH_Access_Full MCH_ReadData_Read MCH_ReadData_Control MCH_ReadData_Data[0:31] MCH_ReadData_Exists SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM[0:3] SDRAM_DQ[0:31] SDRAM_CSn SDRAM_CKE 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400n A0 D0 Tras NOP ACT WRITE PC NOP BA(A0) Trcd RA(A0) CA(A0) FFF F 0 F D0 Twr RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 12: XCL Single Write Operation 26 DS492 April 4, 2005

27 XCL Protocol Cacheline Write Timing Diagram Figure 13 shows an XCL protocol channel performing a cacheline write. 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400n Clock MCH_Access_Write MCH_Access_Control MCH_Access_Data[0:31] A0 D0 D1 D2 D3 MCH_Access_Full MCH_ReadData_Read MCH_ReadData_Control MCH_ReadData_Data[0:31] MCH_ReadData_Exists Tras Trcd Twr SDRAM_Clk Command SDRAM_BankAddr[0:1] NOP ACT WRITE PC NOP BA(A0) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] RA(A0) CA(A0) D0 D1 D2 D3 FFF SDRAM_DQM[0:3] F 0 F SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 13: XCL Cacheline Write Operation DS492 April 4,

28 XCL Protocol Cacheline Read Timing Diagram Figure 14 shows an XCL protocol channel performing a cacheline read. 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400n Clock MCH_Access_Write MCH_Access_Control MCH_Access_Data[0:31] A0 MCH_Access_Full MCH_ReadData_Read MCH_ReadData_Control MCH_ReadData_Data[0:31] MCH_ReadData_Exists Tras Trcd CAS_Latency SDRAM_Clk D0 D1 D2 D3 Command SDRAM_BankAddr[0:1] NOP ACT READ PC NOP BA(A0) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] RA(A0) CA(A0) FFF D0 D1 D2 D3 SDRAM_DQM[0:3] F 0 F SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 14: XCL Cacheline Read Operation 28 DS492 April 4, 2005

29 XCL Protocol Two Cacheline Writes Timing Diagram Figure 15 shows an XCL protocol channel performing a cacheline write followed by another cacheline write operation. 0ns 100ns 200ns 300ns 400ns 500ns Clock MCH_Access_Write MCH_Access_Control MCH_Access_Data[0:31] MCH_Access_Full MCH_ReadData_Read MCH_ReadData_Control A0 D0 D1D2 D3 A1 D4 D5 D6 D7 MCH_ReadData_Data[0:31] MCH_ReadData_Exists SDRAM_Clk Command ACT NOP WRITE PC NOP ACT WRITE PC NOP SDRAM_BankAddr[0:1] BA(A0) BA(A1) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn FFF FFF SDRAM_DQ[0:31] D0D1 D2 D3 D4D5 D6 D7 SDRAM_DQM[0:3] F 0 F 0 F 0 SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 15: Two XCL Cacheline Write Operations DS492 April 4,

30 XCL Protocol Cacheline Write-Read Timing Diagram Figure 16 shows an XCL protocol channel performing a cacheline write followed by a cacheline read operation. 0ns 100ns 200ns 300ns 400ns 500ns Clock MCH_Access_Write MCH_Access_Control MCH_Access_Data[0:31] MCH_Access_Full MCH_ReadData_Read MCH_ReadData_Control A0 D0D1D2D3 A1 MCH_ReadData_Data[0:31] MCH_ReadData_Exists D0 D1D2D3 SDRAM_Clk Command ACT NOP WRITE PC NOP ACT READ PC NOP SDRAM_BankAddr[0:1] BA(A0) BA(A1) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn FFF FFF SDRAM_DQ[0:31] D0D1 D2D3 D0D1D2D3 SDRAM_DQM[0:3] F 0 F 0 F SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 16: XCL Cacheline Write-Read Operation 30 DS492 April 4, 2005

31 XCL Protocol Cacheline Write-Read Timing Diagram - Two XCL Channels Figure 17 shows two XCL protocol channels performing cacheline writes followed by cacheline read operations. 0ns 100ns 200ns 300ns 400ns 500ns 600ns 700n Clock MCH_Access_Write(0) MCH_Access_Control(0) MCH_Access_Data[0:31] MCH_Access_Full(0) MCH_ReadData_Read(0) MCH_ReadData_Control A0 D0D1 D2D3 A1 MCH_ReadData_Data[0:31] D0D1 D2D3 MCH_ReadData_Exists(0) Clock MCH_Access_Write(1) MCH_Access_Control(1) MCH_Access_Data[32:63] MCH_Access_Full(1) MCH_ReadData_Read(1) MCH_ReadData_Control A2 D4D5 D6D7 A3 MCH_ReadData_Data[32:63] D4 D5D6 D7 MCH_ReadData_Exists(1) SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] SDRAM_DQM[0:3] SDRAM_CSn SDRAM_CKE ACT NOP WRITE PC NOP ACT READ PC NOP BA(A0) D0D1D2 D3D4D5 D6D7 FFF BA(A1) FFF D0 D1D2D3 D4D5D6D7 F 0 F 0 F RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Note: RA(A0) = RA(A2) BA(A0) = BA(A2) RA(A1) = RA(A3) BA(A1) = BA(A3) Figure 17: XCL Cacheline Write-Read Operation - Two XCL Channels DS492 April 4,

32 OPB Single Read Timing Diagram - 8-Bit SDRAM Figure 18 shows an OPB single read operation to an 8-bit SDRAM. OPB_Clk OPB_select 0ns 100ns 200ns 300ns 400ns OPB_DBus[0:31] D0 OPB_ABus[0:31] OPB_BE[0:3] A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd CAS_Latency SDRAM_Clk Command SDRAM_BankAddr[0:1] NOP ACT READ NOP PC NOP BA(A0) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn RA(A0) CA(A0) FFF SDRAM_DQM SDRAM_DQ[0:7] D0(0:7) SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to READ Figure 18: OPB Single Read Operation - 8-Bit SDRAM 32 DS492 April 4, 2005

33 OPB Single Read Timing Diagram - 16-Bit SDRAM Figure 19 shows an OPB single read operation to an 16-bit SDRAM. OPB_Clk OPB_select 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns OPB_DBus[0:31] D0 OPB_ABus[0:31] OPB_BE[0:3] A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd CAS_Latency SDRAM_Clk Command SDRAM_BankAddr[0:1] NOP ACT READ NOP PC NOP BA(A0) SDRAM_Addr[0:12] SDRAM_RASn SDRAM_CASn SDRAM_WEn RA(A0) CA(A0) 1FFF SDRAM_DQ[0:15] SDRAM_DQM[0:1] D0(0:15) SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to READ Figure 19: OPB Single Read Operation - 16-Bit SDRAM DS492 April 4,

34 OPB Single Read Timing Diagram - 32-Bit SDRAM Figure 20 shows an OPB single read operation to an 32-bit SDRAM. OPB_Clk OPB_select 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns OPB_DBus[0:31] D0 OPB_ABus[0:31] OPB_BE[0:3] A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd CAS_Latency SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] NOP ACT READ PC NOP BA(A0) RA(A0) CA(A0) FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] SDRAM_DQM[0:3] F 0 F D0 SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to READ Figure 20: OPB Single Read Operation - 32-Bit SDRAM 34 DS492 April 4, 2005

35 OPB Single Write Timing Diagram - 8-Bit SDRAM Figure 21 shows an OPB single write operation to an 8-bit SDRAM. OPB_Clk OPB_select 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns OPB_DBus[0:31] OPB_ABus[0:31] OPB_BE[0:3] D0 A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd Twr SDRAM_Clk Command SDRAM_BankAddr[0:1] NOP ACT WRITE NOP PC NOP BA(A0) SDRAM_Addr[0:11] SDRAM_RASn SDRAM_CASn SDRAM_WEn RA(A0) CA(A0) FFF SDRAM_DQM SDRAM_DQ[0:7] D0(0:7) D0(8:15) SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to WRITE Twr = Write Recovery Figure 21: OPB Single Write Operation - 8-Bit SDRAM DS492 April 4,

36 OPB Single Write Timing Diagram - 16-Bit SDRAM Figure 22 shows an OPB single write operation to an 16-bit SDRAM. OPB_Clk OPB_select 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns OPB_DBus[0:31] OPB_ABus[0:31] OPB_BE[0:3] D0 A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd Twr SDRAM_Clk Command SDRAM_BankAddr[0:1] NOP ACT WRITE NOP PC NOP BA(A0) SDRAM_Addr[0:12] SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:15] RA(A0) CA(A0) D0(0:15) 1FFF SDRAM_DQM[0:1] SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to WRITE Twr = Write Recovery Figure 22: OPB Single Write Operation - 16-Bit SDRAM 36 DS492 April 4, 2005

37 OPB Single Write Timing Diagram - 32-Bit SDRAM Figure 23 shows an OPB single write operation to an 32-bit SDRAM. OPB_Clk OPB_select 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns OPB_DBus[0:31] OPB_ABus[0:31] OPB_BE[0:3] D0 A0 F OPB_RNW OPB_seqAddr Sln_xferAck Tras Trcd Twr SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] NOP ACT WRITE PC NOP BA(A0) RA(A0) CA(A0) FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] SDRAM_DQM[0:3] F 0 F D0 SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Tras = ACTIVE to PRECHARGE Trcd = ACTIVE to WRITE Twr = Write Recovery Figure 23: OPB Single Write Operation - 32-Bit SDRAM DS492 April 4,

38 OPB Burst (Sequential Address) Read Timing Diagram - 8-Bit SDRAM Figure 24 shows an OPB burst read operation to an 8-bit SDRAM. OPB_Clk OPB_select 0ns 100ns 200ns 300ns 400ns 500ns 600ns 700ns OPB_DBus[0:31] OPB_ABus[0:31] OPB_BE[0:3] D0 D1 D2 A0 A1 A2 F OPB_RNW OPB_seqAddr Sln_xferAck SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] ACT NOP NOP NOP NOP PC BA(A0) FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM SDRAM_DQ[0:7] SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 24: OPB Burst Read Operation - 8-Bit SDRAM 38 DS492 April 4, 2005

39 OPB Burst (Sequential Address) Read Timing Diagram - 16-Bit SDRAM Figure 25 shows an OPB burst read operation to an 16-bit SDRAM. OPB_Clk OPB_select 0ns 100ns 200ns 300ns 400ns 500ns 600ns OPB_DBus[0:31] OPB_ABus[0:31] OPB_BE[0:3] D0 D1 D2 A0 A1 A2 F OPB_RNW OPB_seqAddr Sln_xferAck SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:12] ACT NOP NOP NOP NOP PC NOP BA(A0) 1FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:15] SDRAM_DQM[0:1] SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 25: OPB Burst Read Operation - 16-Bit SDRAM DS492 April 4,

40 OPB Burst (Sequential Address) Read Timing Diagram - 32-Bit SDRAM Figure 26 shows an OPB burst read operation to an 32-bit SDRAM. OPB_Clk OPB_select 0ns 100ns 200ns 300ns 400ns 500ns OPB_DBus[0:31] OPB_ABus[0:31] A0 D0 D1 D2 A1 A2 OPB_BE[0:3] F OPB_RNW OPB_seqAddr Sln_xferAck SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] NOP ACT READ PC NOP BA(A0) FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQ[0:31] SDRAM_DQM[0:3] D0 D1 D2 F 0 F SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 26: OPB Burst Read Operation - 32-Bit SDRAM 40 DS492 April 4, 2005

41 OPB Burst (Sequential Address) Write Timing Diagram - 8-Bit SDRAM Figure 27 shows an OPB burst write operation to an 8-bit SDRAM. OPB_Clk OPB_select 0ns 100ns 200ns 300ns 400ns 500ns 600ns OPB_DBus[0:31] OPB_ABus[0:31] D0 A0 D1D2 A1 A2 OPB_BE[0:3] F OPB_RNW OPB_seqAddr Sln_xferAck SDRAM_Clk Command SDRAM_BankAddr[0:1] SDRAM_Addr[0:11] ACT NOP NOP NOP NOP PC NOP BA(A0) FFF SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_DQM SDRAM_DQ[0:7] SDRAM_CSn SDRAM_CKE RA(x) = Row Address CA(x) = Column Address BA(x) = Bank Address PC = Precharge Figure 27: OPB Burst Write Operation - 8-Bit SDRAM DS492 April 4,