SDR SDRAM Controller. User Guide. 10/2012 Capital Microelectronics, Inc. Beijing, China

Transcription

1 SDR SDRAM Controller User Guide 10/2012 Capital Microelectronics, Inc. Beijing, China

2 Contents Contents Introduction SDRAM Overview Pin Description Mode register SDRAM commands... 5 ACTIVE... 5 READ... 6 WRITE... 6 PRECHARGE... 6 BURST TERMINATE... 6 AUTO REFRESH Timing requirements SDRAM controller Design Block Diagram Pin Description Functional Description SDRAM initialization SDRAM read&write&refresh control SDRAM bank management Interface Timing Write interface timing Read interface timing Write and read burst terminate timing Write and read burst timing of page boundary Automatic refresh interface timing Load mode register interface timing SDRAM initialization timing Performance analysis Simulating your design Generate File Directory Structure Revision History

3 1 Introduction This document mainly describes the usage of the single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller IP. The IP provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL and optimized for the CME-M5 architecture. The SDR SDRAM Controller supports the following features: Support interface with SDRAM at up to 133MHz, single data rate Burst lengths of 1, 2, 4, 8 or full page burst Support user burst terminate. For burst length of 2, 4, 8 and full page, support any burst length that not exceed burst length, user can implement different burst length through control user_burst_end, when user want to terminate the burst operation, active the usr_burst_end for 1 cycle CAS latency of 2 or 3 clock cycles Support internal automatic refresh, the refresh period can be programmed Support external automatic refresh request, user can control the auto refresh process Supports the NOP, READ, WRITE, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_TERMINATE and LOAD_MR commands Support for data-path widths of 4, 8, 16, 32, 64 and 72 bits Support user change mode register value through load mode register request, do not support change CAS latency through load mode register request Support user DQM control Device family support: CME-M5, CME-HR3 3

4 2 SDRAM Overview 2.1 Pin Description Table 2-1 SDRAM Interface for x16, 32MB (32-Megabit, 4x512Kx16bit) Interface Name Direction Width Description SDRAM Interface CLK Input 1 Clock input CS# Input 1 Chip select CKE Input 1 Clock enable RAS# Input 1 SDRAM row address strobe CAS# Input 1 SDRAM column address strobe WE# Input 1 SDRAM write enable A Input 11 SDRAM address BA Input 2 SDRAM bank address DQ Inout 16 SDRAM data bus DQML, DQMH Input 1 SDRAM data mask for lower and upper bytes 2.2 Mode register The Mode Register defines the specific SDRAM mode of operation, including the selection of burst length, burst type, cas latency, operation mode etc. Table 2.1 shows a mode register definition example of 32MB SDRAM. The Mode Register, programmed via the LOAD MODE REGISTER command, retains stored information until it is reprogrammed or the device loses power. Mode Register bits M[2:0] specify burst length. M3 specifies the Wrap Type of burst (sequential or interleaved), M[6:4] specify the CAS Latency, M7 and M8 are used on some SDRAMs to specify the operation mode. M9 specifies the Write Burst Mode on some SDRAMs, and M10 and M11 are reserved for future use. The Mode Register must be loaded when all banks are idle, and the controller must wait a specified length of time (tmrd) before initiating any subsequent operation. The results of violating these requirements are unpredictable. 4

5 Table 2-2 Mode register definition of 32MB SDRAM Mode Register Field Value Description M[2:0] 1, 2, 4, 8, full_page Burst length M3 Sequential, interleaved Burst type M[6:4] 2,3 CAS latency M[8:7] Standard operation Operation mode M9 Programmed burst length Write burst mode Single location access M[11:10] Reserved Reserved Different SDRAM product, the mode register definitions have a little difference. 2.3 SDRAM commands Table 2-3 SDRAM command truth table Command CS# RAS# CAS# WE# ADDR NOTES INHIBT H X X X X NOP L H H H X ACTIVE L L H H Bank/Row 2 READ L H L H Bank/Col 3 WRITE L H L L Bank/Col 3 BURST TERMINATE L H H L X PRECHARGE L L H L Code 4 Auto Refresh or L L L H X 5 Self Refresh Load Mode Register L L L L Op-code 6 NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 3. ADDR provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 4. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are Don t Care. 5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 6. ADDR defines the op-code written to the mode register. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent 5

6 access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs except A10 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs except A10 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (trp) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum trp has been met after the PRECHARGE command. For auto refresh, the addressing is generated by the internal refresh controller. 6

7 2.4 Timing requirements Table 2-4 SDRAM timing requirements Timing requirements tac tcl tras trcd trrd trp trfc tref twr tmrd Description Access time from CLK CAS latency, from read command to read data out delay Active to precharge delay Active to read/write delay Active bank a to active bank b delay Precharge command period Auto refresh period Refresh period (typical is 64ms) Write recovery time Load mode register to active or refresh command 7

8 3 SDRAM controller Design 3.1 Block Diagram The figure below shows the block diagram of SDR SDRAM controller IP. usr_bank_addr usr_col_addr sdram_bankman sdram_refresh usr_wr_req usr_rd_req usr_lmr_req usr_req_ack usr_op_busy usr_burst_len sdram_ctrl ctrl address SDRAM usr_data_in usr_data_out usr_data_valid sdram_data data Figure 3-1 SDRAM controller IP block diagram The SDRAM controller IP includes 4 sub modules: sdram_ctrl, sdram_data, sdram_bankman, sdram_refresh. sdram_ctrl module sdram_ctrl module is the core control module, which includes the SDRAM power on initialization and main control state machine. It receives the user request, address and generates SDRAM control related signal. sdram_data module sdram_data module is the data path module. It receives user input data or SDRAM data and bases on state information from sdram_ctrl module to generate data to write to SDRAM or data and data valid signal for user. sdram_bankman module sdram_bankman module s function is to do bank management. It records the current row and bank access status information and generates indication signal for sdram_ctrl module. sdram_ctrl module bases on these signals to decide what kind of command need to be implemented. sdram_refresh module sdram_refresh module is for internal auto refresh control. This IP provides two ways for SDRAM refresh control. First is to implement refresh through internal auto refresh controller. The other way is that user controls refresh and generates the refresh request for IP. sdram_refresh module generates auto_ref_req periodically based on automatic refresh cycle. The refresh cycle can be programmed by user. 8

9 3.2 Pin Description The pin descriptions are outlined in the table below, organized according to user or SDRAM interface. Table 3-1 SDRAM controller IP pin description Interface Name Direction Width Description System Input 1 IP clock input rst_n Input 1 IP reset input, low active User usr_rd_req Input 1 User read request input Interface usr_wr_req Input 1 User write request input usr_ref_req Input 1 User refresh request input usr_lmr_req Input 1 User load mode register request input usr_burst_end Input 1 User burst terminate request input usr_col_addr Input col_addr_width User input column address Input row_addr_width User input row address usr_bank_addr Input bank_addr_width User input bank address usr_data_valid Output 1 Output to indicate output data valid usr_wr_req_ack Output 1 User write request acknowledge output usr_rd_req_ack Output 1 User read request acknowledge output usr_ref_req_ack Output 1 User refresh request acknowledge output usr_lmr_req_ack Output 1 User load mode register request acknowledge output usr_data_in Input data_width User input data for SDRAM write usr_data_valid Output 1 Output to indicate output data valid usr_data_out Output data_width User output data from SDRAM read SDRAM sdr_cke Output 1 SDRAM clock enable Interface sdr_csn Output 1 SDRAM chip select sdr_rasn Output 1 SDRAM row address strobe sdr_casn Output 1 SDRAM column address strobe sdr_wen Output 1 SDRAM write enable sdr_a Output row_addr_width SDRAM address sdr_ba Output bank_addr_width SDRAM bank address sdr_dq Inout data_width SDRAM data bus sdr_dqm Output dqm_width SDRAM data mask for lower and upper bytes SDRAM IP programmed parameter list As is shown in the table below, the SDRAM IP parameters can be separated into 6 groups: 9

10 System, Mode register setting, Bus width setting, power on initialization setting, auto refresh setting and SDRAM AC timing setting Table 3-2 SDRAM controller IP parameter description Group Name Type Value Description System sys_ int up to 133Mhz SDRAM clock frequency Mode Register Setting Bus Width Setting Initial Setting Auto Refresh Setting SDRAM AC Timing Setting burst_length string 1, 2, 4, 8, SDRAM burst length full_page burst_type string Sequential SDRAM burst type interleaved op_mode string standard SDRAM operation mode write_burst_mode string prog_length single_access User write burst mode data_width int 4, 8, 16, 32, 64, SDRAM data width 72 col_addr_width int 8,9,10,11,12,13 SDRAM column address width row_addr_width int 11,12,13,14,15 SDRAM row address width bank_addr_width int 1, 2, 4 SDRAM bank address width sdram_init_time int 0~999(us) SDRAM initialization time (us) sdram_init_arfnum int 1~16 SDRAM initialization autorefresh numbers auto_gen_refresh Int 0, 1 set 0.976us as fundamental count sdram_ref_time Int 16,32,64,128 Refresh command interval (ms) ranged tcl int 2, 3 SDRAM cas latency tmrd Int 1, 2, 3,4 LMR to active/refresh command delay trp int 1~8 Precharge command period trfc int 1~16 Auto refresh period trcd int 1~8 Active to read/write delay twr int 1~8 Write recovery time tras int 1~16 Active to precharge command 3.3 Functional Description This sector mainly describes the function of SDRAM controller IP 10

11 3.3.1 SDRAM initialization 200us trp 8*tRFC INIT_NOP INIT_PRE INIT_ARF INIT_LMR tmrd INIT_DONE Figure 3-2 SDRAM initialization state machine SDRAM read&write&refresh control The core control state machine receives user request and controls SDRAM s read&write and refresh. trfc ARF tmrd LMR wr_req rd_req arf_req IDLE wr_req&row_same &bank_open ~row_same trp PRE ~bank_open rd_req&row_same &bank_open WR_ACK trcd RD_ACK arf_req wr_req ACT rd_req arf_req WDATA RDATA usr_bt & ~usr_wr_req_ack BT usr_bt & ~usr_rd_req_ack Figure 3-3 SDRAM control state machine For SDRAM write control: After initialization, system enters into IDLE state and can accept new request. When get write request (usr_wr_req) and address, if the bank need to access is open and the row is same as last operation, 11

12 system directly enters into WR_ACK status and generates user_req_ack signal then gets into WDATA state to finish data write. If the bank need to access is not open, system need to first get into ACT state to active the row then to write. If the bank is open and the row need to access is not the same with last operation, system need to first get into PRE state to precharge current row and get to ACT to active the new row then to write. When system is in the WDATA state, if finish the burst write operation, system then enter into IDLE state, if get user burst terminate request, system enter into BT state to terminate the write burst operation For full page burst mode, when finish write burst operation or get user burst terminate request system all need to get to BT state and send out the Burst Terminate command. For SDRAM read control: When get read request, if the bank need to access is open and the row is same as last operation, system directly enters into RD_ACK status and generates user_req_ack signal then gets into RDATA state to finish data read. If the bank need to access is not open, system need to first get into ACT state to active the row then to read. If the bank is open and the row need to access is not the same with last operation, system need to first get into PRE state to precharge current row and get to ACT to active the new row then to read. When system is in the RDATA state, if finish the read burst operation, system then enter into IDLE state, if get user burst terminate request, system enter into BT state to terminate the read burst operation For full page burst read mode, when finish read burst operation or get user burst terminate request system all need to get to BT state and send out the Burst Terminate command. For SDRAM refresh control: This IP supports both internal SDRAM refresh control or external user control When internal refresh request come, if system is not busy with other command, it will get into PRE state immediately, after precharge all banks then to finish auto refresh command. If the system is busy with read or write, it will wait read&write end and then repose to the refresh request. If user controls the refresh themselves, system accept the external refresh request and follow the same procedure with internal refresh. The refresh request can not disturb the read or write burst operation. The IP can response to refresh request only when system finish the write or read burst SDRAM bank management The IP supports bank management. It records the bank s open and close information of last operation. For current operation, according to the accessed bank address can output the bank status bank_open signal. It also records the accessed row information of last operation. For current operation, if current operation access the same bank and the same row, it will output positive row_same signal, or else output negative row_same signal to the core control state machine 12

13 3.4 Interface Timing Write interface timing Burst length = 1, write timing, user interface usr_wr_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_wr_req_ack usr_data_in data2 data3 burst_len + 2 clock cycle Figure 3-4 Write timing of user interface When is high, the system can accept new request. User send write request, address and data at the same time and wait for ack. When get usr_wr_req_ack, user need to put the next data and address 1 cycle after the usr_wr_req_ack. The address, data and usr_wr_req need to keep unchanged until get the ack signal. When usr_wr_req_ack is positive, user can send another write request. For two continuous write of the same bank and row, the latency between two write operations is 2 clock cycles. Burst length = 1, write timing of SDRAM interface usr_wr_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_wr_req_ack usr_data_in data2 data3 ctrl_cs IDLE PRE ACT WR_ACK WDATA IDLE PRE ACT WR_ACK WDATA IDLE WR_ACK WDATA IDLE cmd_line PRE ACT NOP WRITE NOP PRE ACT NOP WRITE NOP NOP WRITE sdr_a addr row0 col0 addr row0 col2 col3 sdr_dq cmd_line: {cs,ras,cas,we} data2 2 clock cycle 2 clock cycle 2 clock cycle Figure 3-5 Write timing of SDRAM interface data3 13

14 As is shown in the figure above, when user get usr_wr_req_ack and put the write data on the usr_data_in bus, the data are not immediately write to SDRAM. The data are written to SDRAM 2 cycles after write acknowledge. Burst length = 4, write timing, user interface usr_wr_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col1 col2 usr_wr_req_ack usr_data_in data1 data2 data3 data1 data2 data3 data1 data2 data3 Figure 3-6 Write timing user interface of burst length=4 Support sequential write of burst length 1, 2, 4, 8. If the accessed locations are in the same bank and same row, there are 2 clock cycles latency between two sequential write commands. Burst length = full page, write timing, user interface usr_wr_req usr_bank_addr BA0 BA1 row0 row1 row1 usr_col_addr col0 col1 col2 usr_wr_req_ack usr_data_in data1 datan datan data1 datan NOTE: n is the full page burst length Read interface timing Figure 3-7 Write timing user interface of burst length=full page Burst length=1, read timing of user interface 14

15 usr_rd_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_rd_req_ack usr_data_valid usr_data_out tcl+2 tcl+2 data2 burst length + 2 clock cycle data3 Figure 3-8 Read timing of user interface When is high, the system can accept new request. User send read request and address at the same time and wait for ack. When get usr_rd_req_ack, user can put the another read request 1 cycle after the usr_rd_req_ack. The address and usr_wr_req need to keep unchanged until get the ack signal. User can get read data when usr_data_valid is active. For two continuous read of the same bank and same row, the latency between two read operations is 2 clock cycles. Burst length=1, read timing of SDRAM interface usr_wr_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_rd_req_ack usr_data_valid usr_data_out data2 data3 ctrl_cs IDLE PRE ACT RD_ACK RDATA IDLE PRE ACT RD_ACK RDATA IDLE RD_ACK RDATA IDLE cmd_line PRE ACT NOP READ NOP PRE ACT NOP READ NOP READ sdr_a addr row0 col0 addr row1 col2 col3 sdr_dq cmd_line: {cs,ras,cas,we} tcl+2 tcl+2 data2 data3 burst length + 2 clock cycle Figure 3-9 Read timing of SDRAM interface As is shown in the figure above, when usr_rd_req_ack is active, user can t get read data immediately. From usr_rd_req_ack valid, user need to wait 2 cycles+tcl to get read data. User can wait usr_data_valid to get read data. Burst length=4, read timing of user interface 15

16 usr_rd_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_rd_req_ack usr_data_valid usr_data_out data1 tcl+2 burst length + 2 clock cycle data2 data3 data1 data2 data3 tcl+2 data1 data2 data3 Figure 3-10 Read timing user interface of burst length=4 Support sequential read of burst length 1, 2, 4, 8. If the accessed locations are in the same bank and same row, there is no latency between two sequential read commands. Burst length=full page, read timing of user interface usr_rd_req usr_bank_addr BA0 BA1 row0 row1 usr_col_addr col0 col2 col3 usr_rd_req_ack usr_data_valid usr_data_out tcl+2 data1 datan data1 datan tcl+2 tcl+2 data1 data3 Figure 3-11 Read timing user interface of burst length=full page Write and read burst terminate timing After set burst length through load mode register command, user can issue read and write command of any burst length through usr_burst_end signal The following timing diagram show full page burst write and read terminate by sending out the usr_burst_end signal along with the last write data 16

17 usr_wr_req 8 clock cycle usr_bank_addr BA0 row0 usr_col_addr col0 usr_burst_end usr_wr_req_ack usr_data_in data1 data2 data3 data4 data5 data6 data7 Figure 3-12 Full page write terminate through usr_burst_end As is shown in the figure above, this is an example of full page burst write. If only needs to write 8 data, user need to send out the usr_burst_end signal along with the last write data. When get the usr_burst_end signal, the controller will automatic send out the BT(Burst Terminate) command to terminate the write burst. usr_rd_req 8 clock cycle usr_bank_addr BA0 usr_col_addr row0 col0 usr_rd_req_ack usr_burst_end usr_data_valid usr_data_out tcl+2 data1 data2 data3 data4 data5 data6 data7 Figure 3-13 Full page read terminate through usr_burst_end As is shown in the figure above, this is an example of full page burst read. If only needs to read 8 data, user needs to send out the usr_burst_end signal along with the last data read request. When get the usr_burst_end signal, the controller will automatic send out the BT(Burst Terminate) command to terminate the read burst. 17

18 3.4.4 Write and read burst timing of page boundary For SDRAM, when issue a burst operation, it will automatically wrap to column 0 and continue if the address hit the boundary. In order to protect the data that already written to column 0 and the following address, when get to the page boundary controller will automatically send out the burst terminate command to terminate this burst and de-active the usr_rd_req_ack/usr_wr_req_ack outputs, as is shown in the diagrams below. usr_wr_req usr_bank_addr BA0 row0 Send new address again row1 usr_col_addr usr_wr_req_ack col0 Get to page boundary col1 usr_data_in data1 data2 data3 data1 data2 data3 Figure 3-14 Write interface timing when get to page boundary (full_page burst) The figure above shows an example of full page burst write, when get to the page boundary, the usr_wr_req_ack become negative. If user needs to continue write, the usr_wr_req need to keep active and the new address need to provide again. The new address can be the same row or different row, depends on user requirements. In the case shown in above, when get to the boundary, user provides new row and column to issue a new write burst, after write 4 data, user issues the usr_burst_end to terminate this burst. usr_rd_req usr_bank_addr usr_col_addr BA0 row0 col0 Send new address again row1 col1 usr_rd_req_ack usr_burst_end Get to page boundary usr_data_valid usr_data_out data1 tcl+2 burst length + 2 clock cycle data2 data3 data1 data2 data3 18

19 Figure 3-15 Read interface timing when get to page boundary (full_page burst) The figure above shows an example of full page burst read, when get to the page boundary, the usr_rd_req_ack becomes negative. If user needs to continue read, the usr_rd_req need to keep active and the new address need to be provided again. The new address can be the same row or different row, depends on user requirements. In the case shown in above, when get to the boundary, user provide new row and column to issue a new read burst, after read out 4 data, user issues the usr_burst_end to terminate this burst Automatic refresh interface timing usr_ref_req usr_ref_req_ack ctrl_cs IDLE PRE REF IDLE cmd_line Precharge NOP Refresh NOP cmd_line: {cs,ras,cas,we} Figure 3-16 SDRAM refresh user interface timing User can send refresh request signal(usr_ref_req) after SDRAM initialization finished, the request signal need to continue until get acknowledge (usr_ref_req_ack). usr_ref_req usr_ref_req_ack ctrl_cs IDLE PRE REF REF REF cmd_line Precharge NOP Refresh NOP Refresh NOP Refresh NOP cmd_line: {cs,ras,cas,we} trfc trfc trfc Figure 3-17 Sequential user refresh interface timing 19

20 3.4.6 Load mode register interface timing usr_lmr_req usr_lmr_req_ack ctrl_cs IDLE PRE LMR IDLE cmd_line Precharge NOP LMR NOP Mode Register Value cmd_line: {cs,ras,cas,we} Figure 3-18 SDRAM load mode register interface timing User can send load mode register request signal(usr_lmr_req) after SDRAM initialization finished, the request signal need to continue until get ack (usr_lmr_req_ack). Please note that this load mode register can change burst length, burst type, but can not change CAS latency SDRAM initialization timing Programmed init time Programmed Refresh cycles rst_n usr_op_busy ctrl_cs INIT_NOP INIT_PRE INIT_ARF INIT_LMR INIT_DONE cmd_line Inhibit Nop Precharge Nop Refresh Nop Refresh Nop LMR Nop lmr a10 init_done cmd_line: {cs,ras,cas,we} Figure 3-19 SDRAM initialization timing SDRAM initialization sequence: Maintain stable power, stable clock, and a NOP condition for a period, this period can be set by user, the typical initialize time is 200us Issue precharge commands for all banks of the device Issue 8 or more auto-refresh commands, this refresh cycles can also be set by user Issue a mode register set command to initialize the mode register 20

21 3.5 Performance analysis Resource usage Table 3-3 SDR SDRAM Controller IP resource usage and performance on Primace4.0 Bank Row Data Col Example Device Width Width Width Width LUT4 Reg Clk Actual MT48LC2M32B MHz MT48LC4M16A MHz MT48LC4M32B MHz MT48LC8M8A MHz MT48LC8M16A MHz mt48lc8m32b MHz mt48lc16m4a MHz mt48lc16m8a MHz mt48lc16m16a MHz mt48lc16m32s MHz mt48lc32m8a MHz mt48lc32m16a MHz mt48lc64m4a MHz mt48lc64m8a MHz mt48lc128m4a MHz hyx39s256160fx MHz hyx39s256080fx MHz hyx39s256040fx MHz hyx39s256160fx MHz hyx39s256080fx MHz Summary: LUT4: 320~350, REGs: 250~350 Throughput analysis Maximum throughput is achieved with page bursts. For random operation throughput is given by: Throughput = 1/clock period (ns) data path width (bytes) burst length of access/number of clock cycles per access Write burst (length=8) through put: For example, if data path width = 32 bits (4 bytes), burst length of access = 8, trp=3, trcd=3 Clock cycles to finish write burst = 17(consider the worst case, the accessed address need to be first precharge, active then to write) (1 generate request + 3 for precharge + 3 for active + 1 for ack + 8 burst write + 1 pipe line delay) throughput = 1/10 4 8/17 = 188 Mbytes/s Read burst (length=8) through put: For example, if data path width = 32 bits (4 bytes), burst length of access = 8, trp=3, trcd=3, tcl=3 Clock cycles to finish write burst = 20(consider the worst case, the accessed address need to be first 21

22 precharge, active then to write) (1 generate request + 3 for precharge + 3 for active + 1 for ack + 8 burst write + 1 pipe line delay + 3 clock cycle for tcl) throughput = 1/10 4 8/20 = 160 Mbytes/s 22

23 4 Simulating your design When using Primace IP wizard, the SDR SDRAM Controller IP s source RTL and simulation related file will be generated. User can directly use these source codes to do simulation. Under the \ip_core\sdr_sdram_ctrl\sim directory (as is shown in Table 5-1), user can find the testbench file, basic SDRAM simulation model of Micron and Hynix. If these SDRAM simulation model can not satisfy your requirements, you can directly download the model from the Micron and Hynix s website. Besides, the Modelsim.do script for simulation is provided. 23

24 5 Generate File Directory Structure The SDR SDRAM controller IP wizard generate code includes source files(src), simulation files(sim) and example design files. The detailed design directory structure is as below Project src outputs ip_core ip_top.v (define by user) sdr_sdram_ctrl_v1 src sim doc example sdr_sdram_top.v sdr_sdram_ctrl.v sdr_sdram_bankman.v sdr_sdram_refresh.v sdr_sdram_data.v sdr_tb.v sdr_sdram.f hyx39s256080fx.v mt48lc16m16a2.v sdr_tb.do src_vp CME_sdr_sdram_ ctrl_user_guide_e N01.pdf = directory = source RTL code demo_sdram_top. zip CME_sdr_sdram_ ctrl_example_user _guide_en01.pdf = simulation related files = documentation *.vp (Protected RTL) Figure 5-1 SDRAM directory structure Table 5-1 Design Directory structure Directory src\ ip_core\ \sdr_sdram_ctrl_v1 \doc\sdr_sdram_ctrl_user_guide.doc Description Directory for project source code, including IP wizard generate code, for example: Ip_top.v, which instantiate the IP and define related parameters The directory specially for all IPs Directory for SDR SDRAM controller IP (Encrypted) User guide for SDR SDRAM controller IP 24

25 \src IP Design RTL \sim \sim\sdr_tb.v \sim\mt48lc8m16a2.v \sim\ hyx39s256800fx.v \sim\sdr_sdram.f \sim\sdr_ top.do \sim\src_vp\*.vp Design functional verification Test bench Micron SDRAM behavior model Hynix SDRAM behavior model File list of simulation related file For modelsim simulation Protected RTL for Modelsim simulation \example demo_sdram_top.zip CME_sdr_sdram_ctrl_example_ user_guide_en01.pdf example design User guide of example design 25

26 Revision History Revision Date Comments Initial release Interface/timing diagram update Performance and resource usage update 26