Reference System: Determining the Optimal DCM Phase Shift for the DDR Feedback Clock for Spartan-3E Author: Ed Hallett

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1 XAPP977 (v1.1) June 1, 2007 R Application Note: Embedded Processing Reference System: Determining the Optimal DCM Phase Shift for the DDR Feedback Clock for Spartan-3E Author: Ed Hallett Abstract This application note describes how to build a Spartan -3E embedded system that is used to determine the optimal phase shift of a DDR (Double Data Rate) memory feedback clock. In this system, the DDR memory is controlled by a controller that is attached to the OPB (On-chip Peripheral Bus) and is used in an embedded microprocessor application. This reference system also uses a Digital Clock Manager (DCM) that is configured so that the phase of its output clock can be changed while the system is running. A GPIO (General Purpose Input/Output) core together with a custom control logic core and the included software application dynamically control the phase shift. The GPIO output is controlled by a software application that runs on a MicroBlaze microprocessor, while this application runs out of an internal FPGA BRAM. The application starts with an initial phase shift value, then decrements and increments to find the entire passing phase shift range. At each phase shift value, the application performs memory tests, then records if the tests have passed or failed. The passing range and optimal phase shift value for the given system board are reported by printing them to a HyperTerminal through a UART. The optimal phase shift value is calculated by choosing the center of the passing range. Included Systems Introduction Included with this application note is one reference system (s3e1600e_mb_dcm_phase_shift) built for the Xilinx Spartan-3E 1600E Edition Development board. The reference system is available for downloading at: When building a new circuit board that uses an FPGA and a DDR memory, the optimal phase shift for the DDR feedback clock must be determined, because double data rate memory controllers write and read data at both the rising and falling edges of the controller clock. The optimal time to sample the data is at the midpoint of each of the half clock cycles, or at 90 and 270 degrees as shown in Figure 1. To ensure that the sampling of the read data occurs at these desired times, it is necessary to account for the routing delay of the DDR feedback clock and adjust the clocks to the DDR input data registers appropriately. In a Xilinx FPGA system this can be simply accomplished with the help of a DCM. The DCMs that are available in most Xilinx FPGAs have a built in phase shifter component. If the DDR feedback clock is fed into a DCM, the phase of the output clocks can be adjusted so that the 90 and 270 degree shifted clocks rise at the midpoint of the controller clock half periods. The only difficult part with this approach is knowing exactly how much to shift the phase. This amount is dependent not only on how much routing delay there is from the DDR chip to the FPGA, but also on how much delay there is from the FPGA input pin to the DCM. This application note explains how to create a simple system to experimentally find this optimal phase shift without having to know anything about the routing delays Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at PowerPC is a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. XAPP977 (v1.1) June 1,

2 R Hardware and Software Requirements DDR_Clk_fb DDR_Data_at_FPGA DDR_DQS_at_FPGA t CLK_90_PS DO D1 DDR_Clk_fb_90 DDR_RdData Figure 1: DDR Data Capture DO D1 X977_01_ Hardware and Software Requirements Reference System Specifics The hardware and software requirements are: Xilinx Spartan-3E 1600E Edition development board Xilinx Platform USB programming cable RS232 null-modem serial cable Serial Communications Utility Program (e.g. HyperTerminal) Xilinx Platform Studio i Xilinx Integrated Software Environment (ISE ) i The included reference system targets the Spartan-3E 1600E Edition development board. The system uses the MicroBlaze embedded processor. As shown in the system block diagram in Figure 2, the system also includes the MCH (Multi-Channel) OPB DDR (Dual Data Rate) memory controller, the OPB GPIO IP core, the OPB UART Lite IP core, and a DCM Phase Shift custom logic core. The address map for this reference system is shown in Table 1. MicroBlaze Processor DCM Phase Shift Logic OPB_Clk GPIO_Data DCM OPB GPIO OPB MCH OPB DDR FB_Clk OPB UART Lite Figure 2: Reference System Block Diagram X977_02_ XAPP977 (v1.1) June 1, 2007

3 Reference System Specifics R Address Map Table 1: Reference System Address Map Peripheral Instance Version Base Address High Address opb_mdm debug_module 2.00.a 0x x4140FFFF lmb_bram_if_cntlr dlmb_cntlr 1.00b 0x x00001FFF lmb_bram_if_cntlr ilmb_cntlr 1.00.b 0x x00001FFF opb_uartlite RS232_DTE 1.00.b 0x x4060FFFF mch_opb_ddr DDR_SDRAM_ 32Mx c 0x x23FFFFFF opb_gpio opb_gpio_ b 0x x4000FFFF The bitstream for this system, download.bit, is available in the ready_for_download/ directory under the project root directory. Although the supplied reference system is specifically targeted to work on the Spartan-3E 1600E Edition development board, it can be modified to work on any other board that contains an FPGA and a DDR memory chip. Due to slightly different functionality of the DCMs from other architectures, it is necessary to review the DCM section of the data sheet for the architecture being targeted and the appropriate modifications made. This application note describes how to go through the process of building a Spartan-3E system through the Base System Builder (BSB), that is available through the Embedded Development Kit (EDK), then modifying that system to find the optimal phase shift for the DDR feedback clock. Building the Initial System Through BSB 1. Start the BSB wizard to create a new EDK project. 2. Either choose one of the boards supported by BSB or create a project for a custom board. Choose the FPGA that is available on the board and define whether the system will use a PowerPC or a MicroBlaze soft processor (the reference system that accompanies this application note provides examples with a MicroBlaze). 3. Choose the frequencies for the reference, processor, and bus clocks (for example, the supplied Spartan-3E reference system has the reference, processor, and OPB clocks set to MHz and the DDR clock set to MHz). If MHz is chosen for the reference frequency, then the DDR clock will be set to MHz. Note: The methodology used here for determining the optimum phase shift value is dependent on the clock period of the DDR, so any variation in DDR clock period will require recalculation of the VARIABLE phase shift steps and MIN and MAX valid phase shift range. This is explained in more detail in a later section. 4. Although no debug module is needed for this system, it can be added if desired. 5. Add a BRAM block on OPB or PLB or LMB. The supplied reference systems uses 16KB of BRAM on the LMB. Note: The reason why it is imperative that this application is run out of local BRAM is that at certain phase shifts the data reads from the DDR memory will fail. If the application resided in DDR memory, the microprocessor would not be able to fetch instructions and the application would hang. 6. The other peripherals that are needed to run this application are a DDR memory controller, a UART, and a GPIO core. a. Set up the DDR controller parameters so that they correspond to the parameters of the DDR chip. XAPP977 (v1.1) June 1,

4 R Reference System Specifics b. This reference system uses a UART Lite attached to the OPB. The sole purpose of the UART is to communicate the optimal phase shift value and passing range to the user through a HyperTerminal. c. The GPIO core is used to control and determine the status of the DCM phase shift logic via the software application. Note: More details for setting up the parameters and ports for each core will be provided in the next section. 7. Additional peripherals can also be added to the system, but are not necessary to run the phase shifting application. 8. Direct STDIN and STDOUT to the UART receive and transmit ports. 9. Select the Memory test option to have Base System Builder create a sample application and a linker script. 10. Make sure that the instructions, data and the stack for the application program are all contained within the processor local memory block or BRAM. 11. Review the summary of the system created and select Generate. 12. The initial base system has been created and can be modified to run the application that determines the optimal phase shift for the DDR memory feedback clock. Note: If the system was created for a custom board, be sure to edit the system constraints file, data/system.ucf, to lock down the UART and DDR pins. Additionally, the correct position number of the FPGA in the JTAG chain in etc/download.cmd (default is 1) may have to be set. Although not necessary, it is a good idea to build this initial system and run the sample Memory application built by BSB to make sure that the system is set up correctly and all the location constraints are what they should be. Modifications Required to the Initial System The initial build does not have to be identical to the one described in the previous section, however it must have a processor, local memory, a DDR controller, a UART, and a GPIO core. This section describes what is needed to modify a BSB generated Spartan-3E system. It describes what must be modified to add in the logic, cores, parameters, and connections needed for the optimum phase shift application and that are not selectable through the BSB. It involves changing the clocking so that the phase shifting of the DCM, which is fed by the DDR feedback clock, is variable and connects the DCM phase shifting control inputs/outputs of the DCM to the ports of the GPIO core and the custom phase shift logic core. The next section will detail how to change the sample application so that it performs the phase shifting by controlling the outputs of the GPIO. Note: Because of the high fanout for OPB_Rst, the BSB-generated system may fail timing for some of the reset paths. It is recommended to use the Processor System Reset Module because this helps with fanout of the resets to the buses and the peripheral cores. The included reference design uses the Processor System Reset Module core to provide a more robust reset strategy. This core is available in the EDK tools in the IP Catalog Library under Reset Control. The inclusion of this core is not described in this document but the user can refer to the included reference design for example port connections and parameter settings for this core. How to Modify the Clocking Structure and Other Related Hardware There is a custom core included in the design project that has logic for controlling the DCM Phase Shifter which must be incorporated into the design. Also, there is miscellaneous utility logic that must be added to connect signals from the GPIO to the DCMs. Adding the Custom Phase Shifter Control Logic Core to the Design 1. To modify the clocking structure, copy the entire DCM Phase Shift Logic core, dcm_phase_shift_logic_v1_00_a, from the <project>/pcores/ area of the included reference system to the <project>/pcores/ area of the user project. 4 XAPP977 (v1.1) June 1, 2007

5 Reference System Specifics R 2. In the IP Catalog tab of the Project Information Area window under the Project Repository Section, add the dcm_phase_shift_logic core by right clicking and selecting the Add IP option as shown in Figure 3. If dcm_phase_shift_logic does not appear in the list of available cores, XPS must be re-synced by selecting Project -> Re-scan User Repository. Figure 3: Adding the DCM Phase Shift Logic Core to the Design X977_3_ Adding the Utility Logic to the Design 1. The utility logic that is needed consists of an AND function, which is added when using the Utility Reduced Logic core, and an INVERTER using a Utility Vector Logic core. 2. Go to the IP Catalog tab of the Project Information Area window under the Utility Section and add the util_reduced_logic core by right clicking and selecting the Add IP option. Add in the util_vector_logic in the same way as shown in Figure 4. Figure 4: Adding the Utility Logic Cores to the Design X977_4_ Connecting the Modules for Dynamic Phase Shifting The diagram in Figure 5 illustrates how the connections are made between the various modules to control the DCM phase shifter. This configuration is representative of the supplied XAPP977 (v1.1) June 1,

6 R Reference System Specifics SP3E1600E reference system. Use this diagram as an aid to make the proper connections between the modules in the following sections. DCM Phase Shift Logic CH1 CH2 GPIO DOUT_0 DOUT_1 DOUT_2 DOUT_3 DIN_0 DIN_1 DIN_2 DIN_3 GPIO CH1 Data Reg = 0x GPIO CH2 Data Reg = 0x sys_clk_s Gnd PSIn PSInDec PSDone_Rst PSDone_Reg PSDONE CLK (dps_sw_rst) dcm_1_lock PS_En PSINCDEC AND PSEN PSINCDEC PSDONE PSCLK RST DCM_2 LOCK X977_05_ Figure 5: DCM Phase Shift Logic Control for the SP3E1600E Design Configuring and Adding Ports to the DCM for Phase Shifting This reference design uses three DCMs to supply clocks and control signals to the following embedded components: DCM 0 - MicroBlaze clock, bus clocks for the OPB and LMB, peripheral clocks for all peripherals, except for the MCH OPB DDR and the custom DCM Phase Shift Logic core DCM 1 - clocks to the MCH OPB DDR controller DCM 2 - DDR clocks for the 90 and 270 degree phase shifted clocks, the DDR feedback clock, and the Phase Shifter is used for this DCM Note: In this reference system a MCH OPB DDR memory controller is used. The DDR Clock Period is set to 7.5ns. For clocking structure and supported clock configurations of the MCH OPB DDR memory controller, refer to the DDR Clocking section of the MCH OPB DDR SDRAM Controller Product Specification. For DCM 2, the parameters needed to set up the dynamic phase shifting capability are as shown in Table 2. Table 2: Clocks Module Parameters Parameter C_CLKOUT_PHASE_SHIFT Description This sets the phase shifter in VARIABLE mode which allows the user to adjust the phase shift of this DCM on-the-fly, in this case using a software application running on the MicroBlaze embedded processor. 6 XAPP977 (v1.1) June 1, 2007

7 Reference System Specifics R Table 2: Clocks Module Parameters (Contd) Parameter C_PHASE_SHIFT Description This parameter pre-loads the DCM Phase Shifter with a starting phase shift value which must align with the starting value of the phase shift counter in the software application so that the code will remain synchronized with the Phase Shifter. To set these parameters using the GUI, right click on the dcm_2 module to open the Configure IP menu option for the DCM module. Use the pull-down menu selections to set the parameters correctly as shown in Figure 6. Figure 6: DCM Phase Shift Parameter Settings X977_06_ The ports and descriptions for the DCM Phase Shifter that must be connected are shown in Table 3 and are also highlighted in Figure 7 for the DCM and in Figure 15 for the DCM Phase Shift Logic core. XAPP977 (v1.1) June 1,

8 R Reference System Specifics Table 3: DCM Phase Shifter Ports and Connections DCM Port Name DCM Phase Shift Logic Port Name Description PSEN PS_En This signal enables the Phase Shifter for either increment or decrement operation and must be asserted coincident with the PSINCDEC signal. PSINCDEC PSINCDEC This signal tells the Phase Shifter whether to increment or decrement on each enabled PSCLK signal. PSCLK sys_clk_s The slowest synchronous clock for incrementing or decrementing the Phase Shifter one phase shift step at a time. PSDONE PSDONE This signal needs to be polled by the software application to determine when the Phase Shifter has completed each increment or decrement operation and is stable at the updated phase shift value. LOCKED GPIO2_in This signal needs to be polled by the software application to determine when the DCM is locked, after the SW Reset. Note: The Spartan-3E and Spartan-3A DCM Phase Shifter does not have a PHASE-SHIFT OVERFLOW status bit. Other Xilinx FPGAs do have this status bit which can be used to determine if the Phase Shifter has gone outside it s valid MIN or MAX phase shift range. For the Spartan-3E implementation the phase shifter count is monitored in the software application. See the Spartan-3E FPGA Family: Complete Data Sheet for more information. Figure 7: DCM Phase Shifter Port Connections X977_7_ XAPP977 (v1.1) June 1, 2007

9 Reference System Specifics R Configuring and Adding Ports to the GPIO for Phase Shifting Control GPIO Channels 1 and 2 are used in this application. Channel 1 is used to output control signals to the custom DCM Phase Shift Control Logic. Four bits from this channel are used for control. Channel 2 is used as input only to sense the control signals from the DCM Phase Shift Control Logic. Only two of the four bits for Channel 2 are used as inputs. The other two unused inputs are tied to ground. See Figure 5 for the connection details. Some GPIO core parameters differ from a basic BSB build. Set the GPIO parameters as shown in Table 4. Table 4: GPIO Core Parameters Parameter Description C_IS_DUAL Set to 1: Sets GPIO to use both channels 1 and 2. C_GPIO_WIDTH C_IS_BIDIR_2 C_ALL_INPUTS_2 Set to 4: The channel width parameter applies to both channels even though Channel 2 is only using 2 of the 4 I/Os. Set to 0: Channel 2 is not Bi-directional in this case. Set to 1: Channel 2 is set to input only mode in this case. To set these parameters through the GUI, right click on the opb_gpio core to open the Configure IP menu option for the GPIO core. Select Common under the User tab and check the box for Enable Channel 2. Use the pull-down menu selection to set the GPIO Data Bus Width parameter to 4 as shown in Figure 8. Figure 8: GPIO Common Parameter Settings XAPP977 (v1.1) June 1,

10 R Reference System Specifics Select Channel 1 under the User tab and use the pull-down menu to select the parameters as shown in Figure 9. Then click OK. Figure 9: GPIO Channel 1 Parameter Settings X977_09_ Select Channel 2 under the User tab and use the pull-down menu to select the parameters as shown in Figure 10. Then click OK. Figure 10: GPIO Channel 2 Parameter Settings X977_10_ XAPP977 (v1.1) June 1, 2007

11 Reference System Specifics R Connect the GPIO_d_out and GPIO2_in Ports as shown in Figure 11, and click OK. Note: Tie last two opb_gpio input signals (gpio_din2 & gpio_din3) to ground by using the signal name format 0b0 for each input as shown by the arrows.. Figure 11: GPIO Port Connections X977_11_ Configuring and Connecting Ports for the Utility Logic Set up the util_reduced_logic core parameters to create a 2-bit AND function are as shown in Table 5. Table 5: Utility Logic (util_reduced_logic) Parameters Parameter Description C_OPERATION C_SIZE Set to and function. Set to 2: for 2 inputs. XAPP977 (v1.1) June 1,

12 R Reference System Specifics To set these parameters through the GUI, right click on the util_reduced_logic core to open the Configure IP menu option. Use the pull-down menu to select the The Vector Operation to Perform parameter to and, and set the Size of The Vector parameter to 2 as shown in Figure 12. Then click OK. Figure 12: Utility Reduced Logic Core Parameters X977_12_ Set up the util_vector_logic core parameters to create an INVERTER function are as shown in Table 6. Table 6: Utility Logic (util_vector_logic) Parameters Parameter Description C_OPERATION C_SIZE Set to not function. Set to 1: for 1 input XAPP977 (v1.1) June 1, 2007

13 Reference System Specifics R To set these parameters through the GUI, right click on the util_vector_logic core to open the Configure IP menu option. Use the pull-down menu selection to set the The Vector Operation to Perform parameter to not, and set the Size of The Vector parameter to 1 as shown in Figure 13. Then click OK. Figure 13: Utility Vector Logic Core Parameters X977_13_ The Ports and descriptions for the util_vector_logic that must be connected are shown in Table 7 and highlighted in Figure 14. Table 7: Utility Logic (util_vector_logic) Ports and Connections Utility Logic Port Name Connects to Port Description Op1 GPIO_d_out gpio_dout3 port: This is also the dps_sw_rst signal (software reset to DCM 2). Res Op1 Input on the util_reduced_logic core: This signal is the inverted signal, dps_sw_rst_n. The Ports and descriptions for the util_reduced_logic that must be connected are shown in Table 8 and are also highlighted in Figure 14. XAPP977 (v1.1) June 1,

14 R Reference System Specifics Table 8: Utility Logic (util_reduced_logic) Ports and Connections Utility Logic Port Name Connects to Port Description Op1 Res 1st input of 2-input vector connecting dps_sw_rst_n from util_vector_logic. Op1 LOCK 2nd input of 2-input vector connecting dcm_1_lock from DCM 1. Res RST RST on DCM 2 (dcm_2_rst) - This logic allows DCM 2 to be reset by either dcm_1_lock or the software reset signal dps_sw_rst Figure 14: Utility Logic Cores Port Connections X977_14_ Port Connections of the DCM Phase Shift Logic Core for Phase Shifting Control A custom logic core, dcm_phase_shift_logic, was created to use in conjunction with the GPIO core for controlling the DCM Phase Shifter with the software application. See Figure 5 for the connection details. Connect the remaining ports listed below in Table 9 for the dcm_phase_shift_logic core as shown in Figure 15. Table 9: DCM Phase Shift Logic Core Ports and Connections Utility Logic Port Name Connects to Port Description PS_In GPIO_d_out Connects to gpio_dout0 on the opb_gpio core PSIncDec GPIO_d_out Connects to gpio_dout1 on the opb_gpio core PSDONE_Rst GPIO_d_out Connects to gpio_dout2 on the opb_gpio core PSDONE_Reg GPIO2_in Connects to gpio_din0 on the opb_gpio core 14 XAPP977 (v1.1) June 1, 2007

15 Reference System Specifics R Table 9: DCM Phase Shift Logic Core Ports and Connections Utility Logic Connects to Port Description Port Name Sys_clk sys_clk_s OPB clock from the DCM Sys_reset sys_rst_s If not using a Processor System Reset Module in the design, use BSB-generated sys_rst_s for the Port connection of Sys_reset Figure 15: DCM Phase Shift Logic Core Port Connections X977_15_ DCM Phase Shifter Specifics This section provides a brief overview of the operation of the DCM Phase Shifter as it applies to this application. The Phase Shifter unit provides fine phase shift control of the nine DCM outputs. The PS unit accomplishes this by introducing a fine phase shift delay (TPS) between the CLKFB and CLKIN signals inside the DLL unit. There are 2 modes of operation, FIXED phase shift mode and VARIABLE phase shift mode. As stated before, this application uses VARIABLE phase shift mode so that the Phase Shifter can be controlled dynamically. Several of the parameters of the Phase Shifter are applicable to this discussion to better understand the interaction between the software application and the hardware which controls the phase of the DDR clocks relative to the feedback clock. 1. The C_PHASE_SHIFT parameter value configured in the design for the DDR feedback DCM must match the StartingValue entered in the software application, otherwise the DCM Phase Shifter value will not be synchronized with the application. 2. Xilinx does not guarantee correct phase shifter operation outside the phase shift range defined by the MIN and MAX calculations. 3. Be aware that the VARIABLE phase shift feature could operate differently from architecture to architecture. Always refer to the Data Sheet for the specific Xilinx FPGA Family being used in the design. A C_PHASE_SHIFT value of 0 indicates that there is no phase delay between the feedback clock going to the DDR and the clocks output from the DDR at the DCM. XAPP977 (v1.1) June 1,

16 R Reference System Specifics For this reference system it has been determined, through experimentation, that the optimum Phase Shift value for the SP3E1600E Development board is approximately 50. This value is pre-loaded into the attached reference design under the C_PHASE_SHIFT parameter for the DDR feedback DCM. It is best to start with a value as close as possible to the midpoint of the passing range for a given system board. If the Starting Phase Shift value is not within the passing range for the system board being tested, the software application may not be able to function correctly. For help in calculating the approximate value for the board being tested, consult Answer Record #19385, How do I Determine EDK DDR Controller Timing?. When the DCM is configured in a variable phase-shift mode, the phase can be dynamically shifted in the positive or negative direction. With each phase increment the phase-shift unit adds one DCM_DELAY_STEP of phase-shift to all nine DCM outputs. With each phase decrement, the phase-shift unit subtracts one DCM_DELAY_STEP of phase-shift from all nine DCM outputs. The maximum number of DCM_DELAY_STEPs allowed in each direction is a function of the frequency and can be derived from the following formula taken from the Spartan-3E and Spartan-3A Data Sheets: MAX_STEPS = +/-[INTEGER(20 * (TCLKIN - 3 ns))] For the included Spartan-3E reference system, operating at a DDR clock period of 7.5 ns, the MAX_STEPS = +/- 90. These values are used in the software application to keep track of end-ofrange limits for the phase shift counters. The maximum and minimum variable phase-shift (in picoseconds) in each direction is a function of the MAX_STEPS and the minimum/ maximum value of one phase-shift unit, or DCM_DELAY_STEP. The min and max phase-shift range is defined as: FINE_SHIFT_RANGE_MIN = +/-[MAX_STEPS * DCM_DELAY_STEP_MIN] FINE_SHIFT_RANGE_MAX = +/-[MAX_STEPS * DCM_DELAY_STEP_MAX] The phase shift step in VARIABLE mode is 20 ps and 40 ps, for the DCM_DELAY_STEP_MIN and DCM_DELAY_STEP_MAX, respectively, as per the Spartan-3E FPGA Family: Complete Data Sheet. Using these numbers in the above equations yields values of: FINE_SHIFT_RANGE_MIN = +/ ps or 1.8 ns FINE_SHIFT_RANGE_MAX = +/ ps or 3.6 ns For this design running at a DDR clock frequency of MHz on the SP3E1600E Development board, the FIXED mode Phase Shift value of 50 represents approximately 1.5 ns of positive delay between the feedback clock and the DDR clock output, as per the following equation: Tdelay50(ns) = (NUMSTEPS / MAXSTEPS) * Tddrclk = (50 / 256) * 7.5 = 1.46 ns The Software Application It is assumed that the initial system has been built and that it has a sample memory test application that accompanies it. Also, the compiler options are assumed to be set so that the BRAMs are initialized at build time. If the initial system was created through BSB and a sample application was created (as instructed in the building of the initial system section), this is not a concern as a linker script is created automatically. The linker script sets up all the compile and link time options. If a linker script does not already exist, it is necessary to either set the compiler options or create a linker script to make sure that the application is compiled correctly and that it is initialized into the correct area of the BRAM XAPP977 (v1.1) June 1, 2007

17 Executing the Reference System R The sample application that was created by BSB must be either modified or replaced by the software application from the reference system that accompanies this application note. To replace the BSB software application source code with the completed one, copy PhaseShift_Memory/src/PhaseShift_App.c from the included reference system to the TestApp_Memory/src/ area of the new project. Remove the TestApp_Memory.c file that was created by BSB by right clicking on the source file under the Sources menu option and selecting Remove. Add the new C file to the project by right clicking on the Sources option, then clicking on the Add Existing File option, and selecting the proper file. The software application described above is executed out of internal BRAM. Phase Shift Software Application Flow The Phase Shift software application source code is simple to follow and it is fully commented so that the user knows what is being done at each step in the program. The following steps outline the basic flow of the MAIN section of the software application: 1. Set the Starting Phase value to match the parameter set in the DCM Phase Shifter at configuration and as close to the midpoint of the passing range as possible Note: In the case of the SP3E1600E Development board the value is set to Reset the DDR feedback clock DCM to load in the post configuration phase shift value a. Wait for the DCM to lock 3. Loop searching for Low End of passing range by decrementing the phase shift value and testing DDR memory at each iteration until reaching either the first failing value or the Minimum Low Range value a. Decrement the Phase Shifter by one and wait for PSDone to be set b. Run the simple DDR memory test suite (the application performs 32-bit, 16-bit and 8- bit memory tests) c. If memory tests all pass decrement until a failure occurs or the Minimum Low Range value is reached 4. Reset the DDR feedback clock DCM to load in the post configuration phase shift value a. Wait for the DCM to lock 5. Loop searching for the High End of the passing range by incrementing the phase shift value and testing DDR memory at each iteration until reaching either the first failing value or the Maximum High Range value a. Increment the Phase Shifter by one, then wait for PSDone to be set b. Run the simple DDR memory test suite (the application performs 32-bit, 16-bit and 8- bit memory tests) c. If memory tests all pass, increment until a failure occurs or the Maximum High Range value is reached 6. Calculate the Optimum phase shift value 7. Decrement to the Optimum phase value for the DDR feedback clock DCM to leave the Phase Shifter in the optimum condition 8. Print out the passing range and the recommended Optimum phase shift value for this system board to the HyperTerminal Executing the Reference System Follow these steps to set up the HyperTerminal to monitor the process of the software application. 1. Using HyperTerminal or a similar serial communications utility, map the utility's operation to the physical COM port to be used. 2. Connect the board's serial DTE port to this COM port. XAPP977 (v1.1) June 1,

18 R Executing the Reference System 3. Set the HyperTerminal to the Bits per second of , Data Bits to 8, Parity to None, and Flow Control to None. Refer to Figure 16 for the proper settings. X977_16_ Figure 16: HyperTerminal Settings Executing the Reference System using the Pre-Built Bitstream and the Compiled Software Applications Use the following steps to execute the system using files inside the ready_for_download/ directory under the project root directory. 1. Change directories to the ready_for_download/ directory. 2. Use impact to download the bitstream by using the following command: impact -batch xapp977.cmd 3. Invoke XMD and connect to the MicroBlaze processor by using the following command: xmd -opt xapp977.opt 4. Download the executable by using the following command: dow executable.elf Executing the Reference System from EDK Use the following steps to execute the system using EDK. 1. Open system.xmp inside EDK. 2. Use Hardware Generate Bitstream to generate a bitstream for the system. 3. Download the bitstream to the board with Device Configuration Download Bitstream. 4. Launch XMD with Debug Launch XMD Download the executable by using the following command: 18 XAPP977 (v1.1) June 1, 2007

19 References R dow executable.elf Running the Software Application Use the run command, inside XMD, to run the software application. The status and results of the software application are displayed in the HyperTerminal data screen shown in Figure 17. Figure 17: Phase Shift Software Application Output X977_17_ As can be seen by the output of the software application in Figure 17, the passing range is -4 to 90 and the optimum Phase Shift value is 43, for this case. It is recommended that the FIXED Phase Shift value be set to the value reported. This should be the optimum phase shift value for the system board on which the above application has been run. References Conclusion UG331, Spartan-3 Generation FPGA User Guide (v1.0) DS312, Spartan-3E FPGA Family: Complete Data Sheet (v3.4) Product Specification DS496, MCH OPB DDR SDRAM Controller (v1.0) Product Specification XAPP806, Determining the Optimal DCM Phase Shift for the DDR Feedback Clock (v1.0) This application note describes how to build or modify an embedded processor system that is used for determining the optimal phase shift for the DDR memory feedback clock. The accompanying reference system is built for the Xilinx Spartan-3E 1600E Edition Development board and includes one stand-alone software application. XAPP977 (v1.1) June 1,

20 R Revision History Revision History The following table shows the revision history for this document. Date Version Revision 4/30/ Initial Xilinx release. 6/1/ Updated EDK GUI images XAPP977 (v1.1) June 1, 2007