ESDRAM/SDRAM Controller For 80 MHz Intel i960hd Processor

Transcription

1 ESDRAM/SDRAM Controller For 80 MHz Intel i960hd Processor AN-113 Enhanced Memory Systems Enhanced SDRAM (ESDRAM) is the memory of choice for high performance i960hx systems. The Enhanced Memory Systems ESDRAM is 100% pin and function compatible with standard SDRAM. Therefore, a memory controller can be designed to support both memory types to allow the user a high performance upgrade option over standard SDRAM. Introduction The Intel i960hd processor is popular for high performance embedded applications. The i960hd has an internal 32-bit architecture, a 32-bit address bus and a 32-bit data bus. The processor clock operates at 80 MHz while the external bus operates at 40 MHz. The fast access times of ESDRAM allow read and write hit cycles to be performed in zero wait states without the need for external cache or bank interleaving. This high level of performance is achieved with a single non-interleaved memory bank consisting of as few as two 1Mx16, SM2404T-10 ESDRAM components. Standard SDRAM components must run with a CAS latency of two and with a longer RAS to CAS delay, cycle time delay, and precharge delay. The ESDRAM and SDRAM cycle times are shown in Table 1. Transaction -10 ESDRAM -10 SDRAM Single Read Miss 4 6 Burst Read Miss 4:1:1:1 6:1:1:1 Single Read Hit 3 4 Single Write Hit 2 2 Single Write Miss 3 4 Burst Write Miss 3:1:1:1 4:1:1:1 Auto Refresh (CBR) 4 6 Table 1 - Performance Comparison at a 40 MHz Bus Speed A single CPLD and optional data bus buffers can interface 4 to 16 Mbytes of Enhanced Memory Systems ESDRAM or SDRAM memory to the i960hd processor as shown in Figure 1. This design will support a 40 MHz external bus speed by using the -10 ns version of ESDRAM/SDRAM. This application note will describe the design of this single chip ESDRAM/SDRAM controller. ESDRAM/SDRAM Controller Design The objective of this single CPLD controller design is to support all i960hd memory transactions with minimum memory wait states. The controller is designed to support from 4 to 16 Mbytes of ESDRAM/SDRAM using either individual components or a single DIMM module. The timing is based on the i960hd-80 specification, however this application note could also apply to the other versions of the Intel i960hx family. Two 11-bit page detect registers, TAG_A and TAG_B, are used to indicate when either a read or write cycle is a page hit or a page miss. One tag register is used for each internal bank or ESDRAM/SDRAM. The i960hd operates at 3.3V and is tolerant to +5V inputs on any pin. Therefore the CPLD can drive a +5V output into the i960hd. Both ESDRAM and SDRAM are not tolerant to +5V inputs. If a +5V CPLD is used for the controller, then voltage translation using bus switches must be used to prevent driving more than +3.6V into the address or control inputs. This application note describes a design concept that has not been 100% tested and verified in hardware. Enhanced Memory Systems does not warranty the use of this information and cannot assume responsibility for any errors which may appear in the document. Revision 1.4

2 RESET# CLKIN ADS# Intel i960hd BLAST# W/R# BE(3:0) READY# A(31:2) ESDRAM/SDRAM CPLD Controller D(31:0) TIMER ESDRAM DATA BUFFERS CLK CS# RAS# CAS# WE# DQM(3-0)# A(11) A(10) A(9-0) Vcc CKE D(31:0) ESDRAM/SDRAM Figure 1 - Intel i960hd System Block Diagram The i960hd supports the following memory transactions: Single Read Cycle Burst Read Cycle Single Write Cycle Burst Write Cycle In order to support these bus operations, the ESDRAM/SDRAM controller must interface with the following processor signals and other inputs: CLKIN - External Clock A(31:2) - Address Bus W/R# - Write/Read BLAST# - Last transfer of a cycle ADS# - Address Strobe BE(3:0) - Byte Enables RESET# - System Reset READY# - Data is valid TIMER Timer Input ESDRAM - Tied High if ESDRAM is present The controller generates the following signals to control the ESDRAM memory: RAS# - Row Enable CAS# - Column Address Latch WE# - Write Enable CS# - Chip Select MA(11:0) - Multiplexed Row/Column Address Lines DQM(3:0)# - Data Output Mask Lines Rev

3 The DQM(3:0)# outputs serve as byte selects on partial read or write cycles. The BE(3:0) bits specify whether the transfer size is one, two, or four bytes. Only write cycles need to decode these bits. During read cycles an entire 32-bit word is returned even for partial reads. MRS IDLE AUTO REFRESH ACTV Write-AP Read-AP ESDRAM/SDRAM ESDRAM ONLY PWR ON PRE Figure 2 - Simplified ESDRAM/SDRAM Controller State Machine The state diagram for the ESDRAM/SDRAM memory sequences is shown in Figure 2. A memory sequence is initiated when the ADS# input is sampled at the rising edge of CLKIN. The State Machine implements the following ESDRAM/SDRAM control sequences on the rising edge of CLKIN: Reset Sequence - When the RESET# input is low, the processor is in its reset state. The ESDRAM/SDRAM controller performs a 200 µs delay, a precharge to all banks, eight auto-refreshes, and an MRS cycle. When RESET# is released, the controller enters its idle state waiting for memory transactions. Single Read Miss Sequence - When ADS# is low, W/R# is low, and the tag register for the bank being accessed does not match the current row address, a single read miss sequence begins. The READY# signal is held high to hold off the processor until the data is valid. An ACTV and Read-AP command are issued. The data is returned one cycle after the Read-AP command. A manual precharge command is issued to terminate the burst. Rev

4 Single Read Hit Sequence - When ADS# is low, W/R# is low, and the tag register for the bank being accessed matches the current row address, a single read hit sequence begins. The READY# signal is held high to hold off the processor until the data is valid. A Read-AP command is issued. The data is returned one cycle after the Read-AP command. A manual precharge command is issued to terminate the burst. Single Write Hit Sequence - When ADS# is low, W/R# is high, and the tag register for the bank being accessed does match the current row address, a single write hit sequence begins. The READY# signal is held high to hold off the processor until the data is valid. A Write-AP command is issued. The data is written coincident with the Write-AP command. A manual precharge command is issued to terminate the burst. Single Write Miss Sequence - When ADS# is low, W/R# is high, and the tag register for the bank being accessed does not match the current row address, a single write miss sequence begins. The READY# signal is held high to hold off the processor until the data is valid. An ACTV and then a Write-AP command are issued. The data is written coincident with the Write-AP command. A manual precharge command is issued to terminate the burst. Burst Read Miss Sequence - When ADS# is low, W/R# is low, and the tag register for the bank being accessed does not match the current row address, a single burst read miss sequence begins. The READY# signal is held high to hold off the processor until the data is valid. An ACTV and then a Read-AP command is issued. The first word of data is returned one cycle after the Read-AP command. The last data word is signaled by the assertion of BLAST#. Burst Write Miss Sequence - When ADS# is low, W/R# is high, and the tag register for the bank being accessed does not match the current row address, a burst write miss sequence begins. The READY# signal is held high to hold off the processor until the data is valid. An ACTV and a Write- AP command is issued. The first word of data is written coincident with the Write-AP command. The last data word is signaled by the assertion of BLAST#. Auto-Refresh Sequence - The refresh sequence is started when the external timer pulses high every 32 µs. Any memory cycles that are in progress will be completed prior to beginning the refresh sequence. Idle State - When no read, write, or refresh cycles are in progress, the state machine returns to the idle state. Initialization Sequence - Immediately after reset, a 200 µs delay, a precharge to all banks, eight auto-refreshes, and an MRS cycle is executed. Then the state machine enters the idle state waiting for a memory transaction. Mode Register Set (MRS) Sequence - The MRS sequence programs the ESDRAM/SDRAM for the proper latencies, burst length, and operation mode as part of the initialization sequence. For this design, CAS latency is set to 1, Burst Length to 4, Burst Type to Interleaved. The attached timing sequences demonstrate the timing of the ESDRAM controller in a 80 MHz Intel i960hd system with the -10 ns speed grade of ESDRAM. The worst case timing analysis is performed using Chronology s Timing Designer TM software with ESDRAM timing parameters entered from the datasheet. ESDRAM/SDRAM controller parameters are based on a 7ns Vantis MV128_68 CPLD. The Vantis MV128_68 CPLD was selected because of its fast propagation delay and clock-to-output delay. Other CPLD or FPGA devices with similar performance would also be useful for this ESDRAM/SDRAM controller design. Rev

5 Conclusion An ESDRAM/SDRAM controller for the 80 MHz Intel i960hd processor can be implemented using a small to medium size CPLD such as the Vantis MV128_68. This controller supports a single noninterleaved bank of 4 to 16 Mbytes of ESDRAM/SDRAM. The ESDRAM improves i960hd system performance by reducing the latencies over standard SDRAM. The controller supports both ESDRAM and SDRAM to provide the user with a high performance upgrade option over standard SDRAM. Rev

6 0ns 50ns 100ns 150ns Intel i960 Read Hit Cycle - 40 MHz COMMAND Read-AP PRE CLKIN trp A(31:4), BE(3:0) A(3:2) address addr ADS# BLAST# W/R CS# A(11) - BS BS A(10) MA(9:0) col WE# RAS# CAS# D(31:0) DATA READY# DQM(3:0) Notes: 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length = 4, CL=1. Rev

7 0ns 50ns 100ns Intel i960 Read Miss Cycle - 40 MHz COMMAND CLKIN A(31:4), BE(3:0) A(3:2) ADS# BLAST# W/R CS# A(11) - BS A(10) ACTV Read-AP PRE addr trcd address addr BS trp MA(9:0) WE# RAS# CAS# row col D(31:0) DATA READY# DQM(3:0) Notes: 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length = 4, CL=1. Rev

8 0ns 50ns 100ns Intel i960 Write Hit Cycle - 40 MHz COMMAND Write-AP PRE CLKIN trp A(31:4), BE(3:0) A(3:2) address address ADS# BLAST# W/R CS# A(11) - BS BS A(10) MA(9:0) col WE# RAS# CAS# D(31:0) DATA READY# DQM(3:0) Notes: 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length = 4, CL=1. Rev

9 0ns 50ns 100ns Intel i960 Write Miss Cycle - 40 MHz COMMAND ACTV Write-AP PRE CLKIN A(31:4), BE(3:0) A(3:2) address address ADS# BLAST# W/R# CS# A(11) - BS BS A(10) MA(9:0) WE# RAS# CAS# D(31:0) READY# DQM(3:0) Notes: row col DATA 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length = 4, CL=1. Rev

10 0ns 50ns 100ns 150ns 200ns Intel i960 Burst Read Miss Cycle - 40 MHz COMMAND CLKIN ACTVRead-AP trcd trp A(31:4), BE(3:0) A(3:2) address address ADS# BLAST# W/R CS# A(11) - BS A(10) MA(9:0) WE# RAS# CAS# addr row BS col D(31:0) D1 D2 D3 D4 READY# DQM(3:0) Notes: 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length = 4, CL=1. Rev

11 0ns 50ns 100ns 150ns Intel i960 Burst Write Miss Cycle - 40 MHz COMMAND CLKIN A(31:4), BE(3:0) A(3:2) ADS# BLAST# W/R# CS# A(11) - BS A(10) ACTV Write-AP address addr addr trcd BS trp MA(9:0) WE# RAS# CAS# D(31:0) READY# DQM(3:0) Notes: row col D1 D2 D3 D4 1. Based on -10 ns ESDRAM and 7 ns CPLD. 2. Burst length =4, CL = 1. Rev

12 AC Timing Parameters Name Type Min Max Comment tac1 D 15 Clock Access Time, CL=1 (ESDRAM) tah C 1 Address Hold Time (ESDRAM) tas C 2.5 Address Setup Time (ESDRAM) tch C 1 Command Hold Time (ESDRAM) tco D 3 5 Clock to Output Delay tcs C 2.5 Command Setup Time (ESDRAM) tdh D 1 Data Hold Time (ESDRAM) tds D 2.5 Data Setup Time (ESDRAM) tih1 D 2.5 Input Hold Time tih2 C 2.5 Input Hold Time READY# tis1 C 2.5 Input Setup Time tis2 C 2.5 Input Setup Time READY# toh D 2.5 Data Out Hold Time (ESDRAM) tov1, toh1 D Synchronous Output Valid Delay/Hold tov3, toh3 D Synchronous Output Valid Delay/Hold BLAST# tov5, toh5 D Synchronous Output Valid Delay/Hold A(3:2) tras C Active Command Period trc G Bank Cycle Time trcd G 20 /RAS to /CAS Delay trp G 20 Precharge Time ts C 5.5 Input Setup to Clock Rev

13 " ESDRAM/SDRAM i960hd-80, 40 MHz Bus CPLD Equations " Revision 1.2 " Enhanced Memory Systems " " Notes: " Uses (2) 11-bit page detect registers to optimize performance. " The ESDRAM No Write Transfer Mode is not supported. " TAG_B[11..0] is used when A[21] = 1, TAG_A[11..0] is used when A[21] = 0 " Supports a single bank of either 4, 8, or 16 Mbytes of ESDRAM or SDRAM. " ESDRAM = 1 for ESDRAM, ESDRAM = 0 for SDRAM. " Burst Length = 4, Burst Type = Interleaved INPUT CLKIN; LOW_TRUE INPUT RESET; LOW_TRUE INPUT ADS; LOW_TRUE INPUT BLAST; INPUT WR; INPUT BE[3..0]; INPUT TIMER; INPUT ESDRAM; INPUT A[23..2]; LOW_TRUE OUTPUT READY; LOW_TRUE OUTPUT RAS; LOW_TRUE OUTPUT CAS; LOW_TRUE OUTPUT CS[1..0]; LOW_TRUE OUTPUT WE; LOW_TRUE OUTPUT DQM[3..0]; OUTPUT MA[11..0]; D_FLOP NODE REF_PENDING CLOCKED_BY CLKIN; D_FLOP NODE TAG_A[10..0] CLOCKED_BY ADS; D_FLOP NODE TAG_B[10..0] CLOCKED_BY ADS; NODE q4..q0 CLOCKED_BY CLKIN; NODE COUNT[12]; NODE BANKA; NODE BANKB; "Macros MACRO ON 1; MACRO OFF 0; " Equations " We need to store the current cycle state to generate ESDRAM timings STATE_MACHINE ESDRAM_SDRAM STATE_BITS [q4..q0] CLOCKED_BY CLKIN; STATE POWER_ON: RAS = OFF; CAS = OFF; CS[1] = OFF; CS[0] = OFF; DQM[3..0] = OFF; MA[11..0] =.X.; COUNT = 4000; GOTO INIT_DELAY; STATE INIT_DELAY: RAS = OFF; CAS = OFF; CS[1] = OFF; CS[0] = OFF; Rev

14 DQM[3..0] = OFF; MA[11..0] =.X.; COUNT = COUNT.-. 1; IF COUNT <= 0 THEN GOTO INIT_PALL; GOTO INIT_DELAY; STATE INIT_PALL: RAS = ON; CAS = OFF; WE = ON; DQM[3..0] = OFF; MA[11] =.X.; MA[10] = ON; MA[9..0] =.X.; COUNT = 8; BANKA = OFF; BANKB = OFF; GOTO INIT_REFRESH; STATE INIT_REFRESH: RAS = ON; CAS = ON; DQM[3..0] = OFF; MA[11..0] =.X.; COUNT = COUNT.-. 1; IF COUNT <= 0 THEN GOTO INIT_REFRESH; GOTO INIT_MRS; STATE INIT_MRS: RAS = ON; CAS = ON; WE = ON; DQM[3..0] = OFF; IF (ESDRAM) THEN MA[11..0] = 1Ah; MA[11..0] = 2Ah; GOTO IDLE; STATE IDLE: REF_PENDING = TIMER + REF_PENDING; RAS = OFF; CAS = OFF; Rev

15 CS[1] = OFF; CS[0] = OFF; DQM[3..0] = ON; MA[11..0] =.X.; IF (REF_PENDING) THEN GOTO AUTO_REFRESH; ELSIF (RESET) THEN GOTO POWER_ON; ELSIF (ADS) THEN IF (A[21] * (A[20..10] = TAG_B[10..0])) + (/A[21] * (A[20..10] = TAG_A[10..0])) THEN IF ((A[21] * BANKB) + (/A[21] * BANKA)) THEN IF (/WR) THEN GOTO READ_AP; ELSIF (WR) THEN GOTO WRITE_AP; GOTO ACTIVATE_BANK; GOTO IDLE; STATE AUTO_REFRESH: REF_PENDING= OFF; RAS = ON; CAS = ON; DQM[3..0] = OFF; MA[11..0] =.X.; GOTO IDLE; STATE ACTIVATE_BANK: REF_PENDING= TIMER + REF_PENDING; RAS = ON; CAS = OFF; DQM[3..0] = ON; MA[11..0] = A[21..10]; IF A[21] THEN BANKB = ON; TAG_B[10..0] = A[20..10]; BANKA = ON; TAG_A[10..0] = A[20..10]; IF (RESET) THEN GOTO POWER_ON; ELSIF (REF_PENDING + TIMER) THEN GOTO AUTO_REFRESH; ELSIF (/ESDRAM) THEN GOTO TRCD_DELAY; Rev

16 ELSIF (/WR) THEN GOTO READ_AP; ELSIF (WR) THEN GOTO WRITE_AP; GOTO IDLE; STATE TRCD_DELAY: RAS = OFF; CAS = OFF; DQM[3..0] = ON; MA[11..0] =.X.; IF (RESET) THEN GOTO POWER_ON; ELSIF (/WR) THEN GOTO READ_AP; ELSIF (WR) THEN GOTO WRITE_AP; GOTO IDLE; STATE CL2_DELAY: RAS = OFF; CAS = OFF; DQM[3..0] = ON; MA[11..0] =.X.; IF (RESET) THEN GOTO POWER_ON; GOTO WAIT_FOR_BLAST; STATE WAIT_FOR_BLAST: READY = ON; RAS = OFF; CAS = OFF; DQM[3..0] = ON; MA[11..0] =.X.; IF (RESET) THEN GOTO POWER_ON; IF (BLAST) THEN GOTO IDLE; GOTO WAIT_FOR_BLAST; Rev

17 STATE READ_AP: REF_PENDING= TIMER = REF_PENDING; READY= OFF; RAS = OFF; CAS = ON; DQM[3..0] = ON; MA[11] = A[21]; MA[10] = ON; MA[9..8] = A[23..22]; MA[7..0] = A[9..2]; IF A[21] THEN BANKB = ON; BANKA = ON; IF (RESET) THEN GOTO POWER_ON; ELSIF (/ESDRAM) THEN GOTO CL2_DELAY; GOTO WAIT_FOR_BLAST; STATE PRE: RAS = ON; CAS = OFF; WE = ON; DQM[3..0] = OFF; MA[10] = OFF; MA[9..0] =.X.; IF A[21] THEN BANKB = ON; BANKA = ON; IF (RESET) THEN GOTO POWER_ON; ELSIF (REF_PENDING + TIMER) THEN GOTO AUTO_REFRESH; GOTO IDLE; STATE WRITE_AP: REF_PENDING= TIMER + REF_PENDING; READY = ON; RAS = OFF; CAS = ON; Rev

18 WE = ON; MA[11] = A[21]; MA[10] = ON; MA[9..8] = A[23..22]; MA[7..0] = A[9..2]; IF A[21] THEN BANKB = ON; BANKA = ON; CASE BE[3..0] WHEN 0=> DQM[3..0] = 0; WHEN 1=> DQM[3..0] = 1; WHEN 2=> DQM[3..0] = 2; WHEN 4=> DQM[3..0] = 4; WHEN 8=> DQM[3..0] = 8; END CASE; IF (RESET) THEN GOTO POWER_ON; GOTO WAIT_FOR_BLAST; END ESDRAM_SDRAM; Rev