INTERFERENCE FROM GPU SYSTEM SERVICE REQUESTS
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1 INTERFERENCE FROM GPU SYSTEM SERVICE REQUESTS ARKAPRAVA BASU, JOSEPH L. GREATHOUSE, GURU VENKATARAMANI, JÁN VESELÝ AMD RESEARCH, ADVANCED MICRO DEVICES, INC.
2 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo 2
3 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo CPUs 2
4 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo CPUs Video Decode 2
5 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo CPUs Video Decode Video Encode 2
6 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo CPUs Video Decode Video Encode GPU 2
7 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo Accelerators from Industry and Academia CPUs Video Decode Video Encode GPU 2
8 MODERN SYSTEMS ARE POWERED BY HETEROGENEITY 6 th Gen. AMD A-Series Processor Carrizo Accelerators from Industry and Academia Machine Learning Databases Computer Vision Regular Expressions Physics Graph Analytics Finite State Machines CPUs Video Decode Video Encode GPU Genome Sequencing Reconfigurable (e.g., FPGA) 2
9 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
10 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
11 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
12 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
13 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
14 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
15 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
16 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
17 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator 3
18 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator Work launched by the CPU to accelerators 3
19 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator Work launched by the CPU to accelerators Data marshalled by the CPU 3
20 TRADITIONAL HETEROGENEOUS COMPUTING DRIVEN BY CPUS CPU Data Transfer Accelerator Work launched by the CPU to accelerators Data marshalled by the CPU Communication and computation are coarse-grained 3
21 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
22 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
23 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
24 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
25 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
26 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
27 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
28 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
29 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
30 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
31 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
32 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator 4
33 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator Accelerators and CPUs can launch work to one another (and themselves) 4
34 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator Accelerators and CPUs can launch work to one another (and themselves) Data transfer implicit based on usage 4
35 MODERN ACCELERATORS ARE EQUAL PARTNERS CPU Data Transfer Accelerator Accelerators and CPUs can launch work to one another (and themselves) Data transfer implicit based on usage Communication and computation are fine-grained 4
36 ACCELERATORS CAN NOW REQUEST OS SERVICES 5
37 ACCELERATORS CAN NOW REQUEST OS SERVICES GPU-to-CPU Callbacks (Owens et al., UCHPC 2010) 5
38 ACCELERATORS CAN NOW REQUEST OS SERVICES GPU-to-CPU Callbacks (Owens et al., UCHPC 2010) Page Faults / Demand Paging (Veselý et al., ISPASS 2016) 5
39 ACCELERATORS CAN NOW REQUEST OS SERVICES GPU-to-CPU Callbacks (Owens et al., UCHPC 2010) Page Faults / Demand Paging (Veselý et al., ISPASS 2016) GPU-Initiated Network Requests (GPUnet, USENIX 2014) 5
40 ACCELERATORS CAN NOW REQUEST OS SERVICES GPU-to-CPU Callbacks (Owens et al., UCHPC 2010) Page Faults / Demand Paging (Veselý et al., ISPASS 2016) GPU-Initiated Network Requests (GPUnet, USENIX 2014) GPU-Initiated File System Requests (GPUfs, ASPLOS 2013) 5
41 ACCELERATORS CAN NOW REQUEST OS SERVICES GPU-to-CPU Callbacks (Owens et al., UCHPC 2010) Page Faults / Demand Paging (Veselý et al., ISPASS 2016) GPU-Initiated Network Requests (GPUnet, USENIX 2014) GPU-Initiated File System Requests (GPUfs, ASPLOS 2013) Generic System Calls (Genesys, ISCA 2018) ioctl() for other devices Memory management (e.g., sbrk(), mmap()) Signals 5
42 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 GPU Memory 6
43 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 Step 1: Set up request arguments in memory GPU Memory 6
44 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 Step 1: Set up request arguments in memory GPU 1 Memory 6
45 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU GPU 1 Memory 6
46 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU 2 GPU 1 Memory 6
47 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 CPU 1 CPU 0 Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU Step 3: (a) Schedule bottom-half handler 2 GPU 1 Memory 6
48 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU Step 3: (a) Schedule bottom-half handler 2 GPU 1 Memory 6
49 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU Step 3: (a) Schedule bottom-half handler (b) ACK request to GPU 1 2 GPU Memory 6
50 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 3b Step 1: Set up request arguments in memory Step 2: Send request interrupt to a CPU Step 3: (a) Schedule bottom-half handler (b) ACK request to GPU 1 2 GPU Memory 6
51 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 3b Step 4: (a) Set up kernel work queue arguments 2 GPU 1 Memory 7
52 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 3b Step 4: (a) Set up kernel work queue arguments 2 GPU 4a 1 Memory 7
53 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 3a CPU 1 CPU 0 3b Step 4: (a) Set up kernel work queue arguments (b) Queue worker thread 2 GPU 4a 1 Memory 7
54 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 4b 3a CPU 1 CPU 0 3b Step 4: (a) Set up kernel work queue arguments (b) Queue worker thread 2 GPU 4a 1 Memory 7
55 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 4b 3a CPU 1 CPU 0 3b Step 5: Perform SSR 2 GPU 4a 1 Memory 8
56 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 4b 3a CPU 1 CPU 0 3b Step 5: Perform SSR 2 GPU 5 4a 1 Memory 8
57 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 4b 3a CPU 1 CPU 0 3b 2 GPU 5 Step 5: Perform SSR Step 6: Send response to GPU 4a 1 Memory 8
58 HOW A GPU SYSTEM SERVICE REQUEST IS HANDLED CPU 2 4b 3a CPU 1 CPU 0 3b 6 2 GPU 5 Step 5: Perform SSR Step 6: Send response to GPU 4a 1 Memory 8
59 SYSTEM SERVICE REQUESTS CAN LEAD TO DIFFICULTIES 9
60 SYSTEM SERVICE REQUESTS CAN LEAD TO DIFFICULTIES GPUs and accelerators can request OS (system) services 9
61 SYSTEM SERVICE REQUESTS CAN LEAD TO DIFFICULTIES GPUs and accelerators can request OS (system) services These SSRs can interfere with unrelated CPU-based work 9
62 SYSTEM SERVICE REQUESTS CAN LEAD TO DIFFICULTIES GPUs and accelerators can request OS (system) services These SSRs can interfere with unrelated CPU-based work Unrelated CPU-Based work can slow down GPU SSR handling 9
63 SYSTEM SERVICE REQUESTS CAN LEAD TO DIFFICULTIES GPUs and accelerators can request OS (system) services These SSRs can interfere with unrelated CPU-based work Unrelated CPU-Based work can slow down GPU SSR handling CPUs lose opportunity to sleep because of GPU SSRs 9
64 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work a 1 10
65 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work a 1 10
66 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work a 1 10
67 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work a 1 10
68 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch 10
69 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch 10
70 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch Kernel Task Operation 10
71 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU0 2 3 CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch Kernel Task Operation 10
72 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch Kernel Task Operation 10
73 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch Kernel Task Operation 10
74 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a CPU1 CPU2 4b 3a 3b CPU User Work GPU User Work 5 6 4a 1 2 Mode/Task Switch Kernel Task Operation 10
75 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a CPU1 CPU2 10 4b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
76 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a 4 CPU1 CPU2 10 4b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
77 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a 4 CPU1 4b CPU2 10 4b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
78 MODES OF INTERFERENCE FROM GPU SSRS GPU CPU a 4 CPU1 4b CPU2 10 4b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
79 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. 3a 4 CPU1 4b CPU2 10 4b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
80 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
81 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b b 3a 3b a 1 CPU User Work GPU User Work Mode/Task Switch Kernel Task Operation Low-Performance User-Mode Operation
82 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b 5 11
83 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b Direct CPU Overheads 5 11
84 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b Direct CPU Overheads Indirect CPU Overheads 5 11
85 GPU CPU0 MODES OF INTERFERENCE FROM GPU SSRS 2 3 GPU Stalls. CPU1 CPU2 3a 4 4b Direct CPU Overheads Indirect CPU Overheads GPU Overheads 5 11
86 TEST PLATFORM USED TO DEMONSTRATE THIS 12
87 TEST PLATFORM USED TO DEMONSTRATE THIS AMD A K APU 4x 3.7 GHz CPU cores. AMD Family 15h Model 30h 720 MHz AMD GCN 1.1 ( Sea Islands, gfx700) GPU, 8 CUs 32 GB Dual-Channel DDR
88 TEST PLATFORM USED TO DEMONSTRATE THIS AMD A K APU 4x 3.7 GHz CPU cores. AMD Family 15h Model 30h 720 MHz AMD GCN 1.1 ( Sea Islands, gfx700) GPU, 8 CUs 32 GB Dual-Channel DDR Ubuntu LTS (AMD64) Linux kernel with HSA Drivers (amdkfd 1.6.1) 12
89 TEST PLATFORM USED TO DEMONSTRATE THIS AMD A K APU 4x 3.7 GHz CPU cores. AMD Family 15h Model 30h 720 MHz AMD GCN 1.1 ( Sea Islands, gfx700) GPU, 8 CUs 32 GB Dual-Channel DDR Ubuntu LTS (AMD64) Linux kernel with HSA Drivers (amdkfd 1.6.1) PARSEC benchmarks for CPU work 12
90 TEST PLATFORM USED TO DEMONSTRATE THIS AMD A K APU 4x 3.7 GHz CPU cores. AMD Family 15h Model 30h 720 MHz AMD GCN 1.1 ( Sea Islands, gfx700) GPU, 8 CUs 32 GB Dual-Channel DDR Ubuntu LTS (AMD64) Linux kernel with HSA Drivers (amdkfd 1.6.1) PARSEC benchmarks for CPU work OpenCL benchmark applications modified to create SSRs (page faults) BPT [Veselý et al., ISPASS 2016] XSBench [Veselý et al., ISPASS 2016] SHOC BFS SHOC SpMV Pannotia SSSP µbenchmark 12
91 CPU PERFORMANCE W/ SSR-USING GPU APPLICATIONS 13
92 INDIRECT CPU OVERHEADS FROM GPU SSRS 14
93 GPU PERFORMANCE W/ CONCURRENT CPU APPS 15
94 GPU PERFORMANCE W/ CONCURRENT CPU APPS CPU cores avoid going to sleep, which can increase responsiveness to GPU requests 15
95 Interrupt Coalescing Mitigation Strategies Interrupt Steering TAKE INSPIRATION FROM OTHER DOMAINS (E.G. HIGH PERFORMANCE NETWORKING) Merged SSR Handlers Driver for Enforcing CPU QoS 16
96 GPU CPU0 2 3 MITIGATION: INTERRUPT COALESCING GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b
97 GPU CPU0 2 3 MITIGATION: INTERRUPT COALESCING GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b 1 2 Wait until multiple SSR requests arrive before interrupting CPU core 17
98 GPU CPU0 2 3 MITIGATION: INTERRUPT COALESCING 3a 4 GPU Stalls. Take fewer interrupts and see less indirect user-level overhead But more likely to stall the GPU CPU1 CPU2 4b b 4a 3a 3b 1 2 Wait until multiple SSR requests arrive before interrupting CPU core 17
99 GPU CPU0 2 3 MITIGATION: INTERRUPT COALESCING 3a 4 GPU Stalls. Take fewer interrupts and see less indirect user-level overhead But more likely to stall the GPU CPU1 CPU2 4b b 4a 3a 3b 1 2 Wait until multiple SSR requests arrive before interrupting CPU core 17
100 GPU CPU0 2 3 MITIGATION: INTERRUPT STEERING GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b
101 GPU CPU0 2 3 MITIGATION: INTERRUPT STEERING GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b 1 2 Ensure that all interrupts go to the same core, rather than round-robin to all cores 18
102 GPU CPU0 2 3 MITIGATION: INTERRUPT STEERING GPU Stalls. Limit how many cores are affected. Reduce global indirect overheads. CPU1 CPU2 3a 4 4b b 4a 3a 3b 1 2 Ensure that all interrupts go to the same core, rather than round-robin to all cores 18
103 GPU CPU0 2 3 MITIGATION: INTERRUPT STEERING 3a 4 GPU Stalls. Limit how many cores are affected. Reduce global indirect overheads. But harms fairness! CPU1 CPU2 4b b 4a 3a 3b 1 2 Ensure that all interrupts go to the same core, rather than round-robin to all cores 18
104 GPU CPU0 2 3 MITIGATION: MERGED SSR HANDLER GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b
105 GPU CPU0 2 3 MITIGATION: MERGED SSR HANDLER GPU Stalls. CPU1 CPU2 3a 4 4b b 4a 3a 3b 1 2 Merge SSR pre-proceeding (4) with interrupt handler (3) 19
106 GPU CPU0 2 3 MITIGATION: MERGED SSR HANDLER GPU Stalls. Fewer interrupts and less indirect overhead. Handle GPU requests with much less latency. CPU1 CPU2 3a 4 4b b 4a 3a 3b 1 2 Merge SSR pre-proceeding (4) with interrupt handler (3) 19
107 GPU CPU0 2 3 MITIGATION: MERGED SSR HANDLER 3a 4 GPU Stalls. Fewer interrupts and less indirect overhead. Handle GPU requests with much less latency. But runs more CPU code in high-priority context! CPU1 CPU2 4b b 4a 3a 3b 1 2 Merge SSR pre-proceeding (4) with interrupt handler (3) 19
108 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS 20
109 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS 20
110 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS Merged Handler Interrupt Steering + Interrupt Coalescing Interrupt Steering + Merged Handler 20
111 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS Merged Handler Interrupt Steering + Interrupt Coalescing Interrupt Steering + Merged Handler Default 20
112 DRIVER MODIFICATIONS TO ENSURE CPU QOS CPU 2 4b 3a CPU 1 CPU 0 3b 6 2 GPU 5 4a 1 Memory 21
113 DRIVER MODIFICATIONS TO ENSURE CPU QOS CPU 2 4b 3a CPU 1 CPU 0 3b 2 GPU 4a 1 Memory 22
114 DRIVER MODIFICATIONS TO ENSURE CPU QOS CPU 2 4b 3a CPU 1 CPU 0 3b 5 Governor in Driver 2 GPU 4a 1 Memory 22
115 DRIVER MODIFICATIONS TO ENSURE CPU QOS CPU 2 4b 3a CPU 1 CPU 0 3b 5 Governor in Driver 6 Step 5: Track SSR overheads + delay step 6 to stall the GPU 2 GPU 4a 1 Memory 22
116 GOVERNOR TO CONTROL CPU QOS 23
117 GOVERNOR TO CONTROL CPU QOS CPU Cycles Handling SSRs > Threshold 23
118 GOVERNOR TO CONTROL CPU QOS CPU Cycles Handling SSRs > Threshold N Delay 0 23
119 GOVERNOR TO CONTROL CPU QOS CPU Cycles Handling SSRs > Threshold N Delay 0 Service SSR and Return GPU Result 23
120 GOVERNOR TO CONTROL CPU QOS Delay == 0? Y CPU Cycles Handling SSRs > Threshold N Delay 0 Service SSR and Return GPU Result 23
121 GOVERNOR TO CONTROL CPU QOS Delay == 0? Y Y CPU Cycles Handling SSRs > Threshold N Delay 0 Delay 10 µsec Service SSR and Return GPU Result 23
122 GOVERNOR TO CONTROL CPU QOS Delay == 0? Y Y CPU Cycles Handling SSRs > Threshold N Delay 0 Delay 10 µsec Sleep Delay µsec Service SSR and Return GPU Result 23
123 GOVERNOR TO CONTROL CPU QOS Delay Delay*2 N Delay == 0? Y Y CPU Cycles Handling SSRs > Threshold N Delay 0 Delay 10 µsec Sleep Delay µsec Service SSR and Return GPU Result 23
124 CPU PERFORMANCE AT DIFFERENT QOS LEVELS 24
125 GPU PERFORMANCE SUFFERS FOR CPU QOS 25
126 SUMMARY Heterogeneous systems can include increasingly more accelerators GPUs and accelerators now request system services These can cause interference between accelerators & unrelated CPU work Problem may worsen in the future Existing mitigation strategies help, but are not complete solution 26
127 QUESTIONS? Disclaimer The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Linux is a registered trademark of Linus Torvalds. OpenCL is a trademark of Apple Inc. used by permission by Khronos. Other names used herein are for identification purposes only and may be trademarks of their respective companies. 27
128 BACKUP SLIDES 28
129 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS
130 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS
131 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS Default
132 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS Merged Handler Interrupt Steering + Interrupt Coalescing Merged Handler + Interrupt Coalescing Merged Handler + Interrupt Steering + Coalescing Default
133 PARETO CURVE OF MITIGATION STRATEGY TRADEOFFS Merged Handler Merged Handler + Interrupt Coalescing Merged Handler + Interrupt Steering + Coalescing Interrupt Coalescing Interrupt Steering + Interrupt Coalescing Merged Handler + Interrupt Steering Default Interrupt Steering
134 SSRS LIMIT LOW-POWER SLEEP STATES 30
135 MITIGATION EFFECT ON SLEEP STATES 31
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