High-Level Synthesis with LabVIEW FPGA

Transcription

1 High-Level Synthesis with LabVIEW FPGA National Instruments

2 Agenda Introduction NI RIO technology LabVIEW FPGA & IP Builder RIO Hardware Platform Application 2

3 An Ideal Embedded Architecture Processor FPGA Floating-point processing Communications Multicore technology High-speed control & processing Reconfigurable hardware Reliability Low-level access to hardware Custom timing & triggering Modular 3

4 The Challenge Processor FPGA Multicore programming challenge Low-level tools Verilog & VHDL Fixed-point algorithms Custom drivers and middleware Custom digital interface/buses Custom timing for different types of 4

5 Build vs. Buy Build Custom HW/SW solution Use a lot of in-house resources Ability to get exactly what you want Buy Off-the-shelf HW/SW solution Use less resources because systems are prebuilt Often get more than you need 5

6 Cost Build vs. Buy Buy Build Volume per year Now with new versions of sbrio: Gives the BUILD customer a cheaper OTS solution Gives the BUY customer a more flexible OTS solution 6

7 NI RIO Technology Platform Processor FPGA Enet USB RTOS Analysis IP Control IP Analog Digital Analysis Multicore Timing IP Comm IP Comm Motion Logging Comm IPNet 3 rd party IP 3 rd party NI RIO Hardware Packaged Board-Level 7

8 NI RIO Software Processor FPGA Enet USB RTOS Analysis Control Logging Comm Bus Analysis IP Control IP Timing IP Comm IP IPNet 3 rd party IP IP Analog Digital Comm Motion 3 rd party LabVIEW, LabVIEW Real-Time Multicore programming Built-in functions for analysis, control and communications Ability to integrate C code and text-based math LabVIEW FPGA Fixed-point processing Built-in functions for analysis, control and communications Ability to integrate VHDL Drivers and middleware Pre-built and communication drivers DMA, single-point communication between processor and FPGA Ability to create custom 8

9 NI RIO Software Benefits Graphical programming for multicore/real-time processors and FPGAs Advanced signal processing and control algorithms Built-in drivers and middleware for and communication Open for integration of existing code/ip 9

10 HLS(High-Level Synthesis) LabVIEW C, C++ LabVIEW FPGA VHDL Programming Vivado HLS 10

11 LabVIEW FPGA Counter Analog with DMA LabVIEW FPGA VHDL 66 Pages ~4000 lines 11

12 LabVIEW FPGA Translation Optimization Synthesis Bit Stream VHDL Generation Analysis Logic Reduction Place and Route Timing Verification Generation Download/Run LabVIEW FPGA Code FPGA Logic Implementation 12

13 LabVIEW FPGA IP Builder Add-on Tool for LabVIEW FPGA Rapidly develop high performance algorithms for FPGAs Quickly explore design tradeoffs using directives Reuse IP to meet new design requirements LV FPGA VI LV FPGA IP Builder VI Manual optimization required Optimization using high-level synthesis 13

14 LabVIEW FPGA IP Builder User Flow Create Algorithm VI Specify Directives Generate performance estimation Generate Design Use within top-level LV FPGA VI Use dataflow programming Limited functions palette 14

15 LabVIEW FPGA IP Builder User Flow Create Algorithm VI Specify Directives Generate performance estimation Generate Design Use within top-level LV FPGA VI 15

16 LabVIEW FPGA IP Builder User Flow Create Algorithm VI Specify Directives Generate performance estimation Generate Design Use within top-level LV FPGA VI 16

17 LabVIEW FPGA IP Builder User Flow Create Algorithm VI Specify Directives Generate performance estimation Generate Design Use within top-level LV FPGA VI Choose VI and Directives Generate HDL Create IP VI 17

18 LabVIEW FPGA IP Builder User Flow Create Algorithm VI Specify Directives Generate performance estimation Generate Design Use within top-level LV FPGA VI Integrate into Single-Cycle Timed Loop Add, DMA FIFOs, Host Communication, etc. 18

19 NI RIO Hardware Benefits Reconfigurable, off-the-shelf hardware Breadth of high-quality (analog, motion, vision, RF, ) Variety of packaged and board-level form factors Open platforms for integration with 3rd-party hardware NI RIO Hardware Packaged Board-Level 21

20 NI RIO Technology Curve PXI / FlexRIO Performance Processor FPGA Custom PC RIO / R Series Multicore CompactRIO Single-Board RIO CompactRIO Deploy 22

21 CompactRIO Processor FPGA (Real-Time, Freescale) (Xilinx Virtex/Spartan Class) (Industrial/Embedded Class) VxWorks RTOS Enet Analysis IP Control IP Analog Digital USB Analysis Control Timing IP Comm IP Comm Motion Logging Comm IPNet 3 rd party IP 3 rd party Packaging -40 to 70 deg C Hardware and OEM Services Rugged Certifications/Ratings Up to 8 Slots Most rugged platform Compact size, -40 to 70 ⁰C Industrial and Embedded Analog, digital, motion, communication, Integrated FPGA in chassis 23

22 CompactRIO 24

23 CompactRIO Modules 센서의쉬운연결신호조절기능내장 Real-Time Processor 신뢰할수있는측정, 분석, 제어, 연결성을제공 (Maximum Specification) CPU Intel i GHz RAM 2 GB DDR3 Storage 32 GB Enet, RS232, USB Reconfigurable FPGA 40MHz 고속클럭의사용자정의가능한제어및 구성 Xilinx Spartan-6 LX150 아날로그 디지털 모션드라이버통신모듈 Extreme Ruggedness -40 to 70 C temperature range 50g shock, 5g vibration Low Power Consumption 9 to 35 VDC power, 7-10W 25

24 Single-Board RIO RIO 기본구성 Real-Time 프로세서프로그래밍가능한 FPGA FPGA 디지털입출력 작은사이즈 10.3 x 9.7cm 보드입출력전원 USB Ethernet RS232 CAN RIO Mezzanine Card (RMC) FPGA 디지털입출력 USB 프로세서입출력 26

25 Smart Grid Renewables Life Sciences Industrial Control RIO Architecture & NI LabVIEW Processor FPGA NI Single-Board RIO NI CompactRIO PC RIO/R Series PXI RIO/FlexRIO 27

26 NI RIO Applications and Industries Embedded Design Embedded prototyping a Medical devices Renewable Energy Robotics Industrial Control & Measurements Machine prototyping Industrial control Optimized automation Test & Communications RF, wireless and custom test Hardware-in-the loop (HIL) 28

27 NI LabVIEW RIO Evaluation Kit RIO Evaluation hardware 400 MHz Real-Time Controller Ethernet, CAN, USB, SDCard, RS232 & RS485 serial ports AI, AO, DIO, LCD Screen Step-by-Step Tutorials Cables and accessories 90-day extended evaluation version of NI LabVIEW, Real-Time and FPGA 29