WP 14 and Timing Sync

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2 WP 14 and Timing Sync Eiscat Technical meeting Leif Johansson National Instruments

3 Eiscat Syncronisation

4 Signal vs. Time-Based Synchronization Signal-Based Share Physical Clocks / Triggers Time-Based Generate Signals Share Time Ethernet (1588) IRIG GPS Etc. 4 Generate Signals

5 Cooperation: NI and CERN White Rabbit Partnering with CERN in developing White Rabbit (WR) Performance Distance: > 10 km Scale: > 2000 nodes Accuracy: < 1ns skew, < 100 ps jitter o Compensates for propagation delay (cable length, temperature variation, etc.) Leverage Industry standards (802.x, IEEE 1588, SyncE) Gigabit Ethernet communication with deterministic capability Generally Applicable 5

6 White Rabbit PXI_Clk10 Disciplining Performance

7 NI FlexRIO PXI/ PXIe NI FlexRIO Adapter Module NI FlexRIO FPGA Module PXI Platform Interchangeable I/O Digital or analog NI FlexRIO Adapter Module Development Kit (MDK) Virtex-5 FPGA 132 digital I/O lines Up to 512 MB of DRAM Peer-to-peer data streaming Data transfer Synchronization Clocking/triggers Power/cooling

8 Setup Master PXI Chassis PXI-6685 White Rabbit Master PXI_Clk10 Att Att Ch0 Ch1 Slave PXI Chassis PXI-6685 White Rabbit Slave PXI_Clk10 White Rabbit Fiber Optic Connection PXIe-5186 Simultaneously sampled 8-bit vertical resolution 6.25 GS/s sampling rate 8

9 Measurement PXI systems will be allowed to warm up with free running PXI_Clk10 s for an hour When Systems have warmed up the PXI_Clk10 s are attach to the corresponding Time Keepers, initiating PXI_Clk10 Disciplining. Measurements While logging the phase of the master and slave is aligned by changing Phase lock offset on the slave. For an hour the time delay is measured every 250ms. For 72 hours the time delay is measured every 10sec. 9

10 PXI_Clk10 Phase alignment Fine adjustment Initial Adjustment 10

11 PXI_Clk10 Stability first hour 11

12 PXI_Clk10 Stability over 72 hours 12

13 White Rabbit Absolute Time Based Triggering Performance October 2013

14 Absolute Time Absolute time is maintained by the Time Keeper on each device. This absolute time resolution is 10ns (100MHz). When White Rabbit is enabled absolute time is locked between master and slave. The absolute time difference between master and slave is constant but not necessary zero. The absolute time is used for: Hardware Time Stamping of events (signal edges) Scheduling Future Timed Events (FTE s) 14

15 Aligning Absolute Time Align 100ns (10MHz) multiples of absolute time to PXI_Clk10 edges on master and slave. Generate a FTE from the Master trough a coax cable and time stamp this on the Slave. When sending an FTE on an 100ns multiple we can remove propagation delay when the cable propagation delay is <100ns. PXI_Clk10 s are aligned and thus the 100ns multiples of absolute time are also aligned in previous step. Share the FTE time with the Slave over UDP This allows the slave to calculate it s offset from the master and adjust it s absolute time to match the masters absolute time. Round Slave time-stamp down to nearest 100ns multiple. Adjustment = FTE Time rounded time stamp 15

16 Sample Clock Generation The NI-5761R requires a 100MHz external clock. This can be generate using the DDS of a PXI-6653 in slot 3. The DDS is clocked with PXI_Clk10. To make sure the sample clocks are phase aligned the update is triggered using a FTE trigger. PXI-6685 White Rabbit Slave PXI_Clk10 Master PXI Chassis PXI_Clk10 FTE Trigger White Rabbit Connection DDS Slave PXI Chassis FTE Trigger DDS Sample Clock Sample Clock 16

17 Sample Clock Performance 17

18 Triggering NI-5761R Setup Master PXI Chassis PXI MHz PXI-6653 NI-5761R Ch0 Ch0 White Rabbit Connection Slave PXI Chassis PXIe MS/s, 16bit Arbitrary Waveform generator Generating 1MHz Sine 100MHz PXI-6685 PXI-6653 NI-5761R Ch0 18

19 Triggering NI-5761R Performance Measurement The systems are allowed to warm up and white rabbit PXI_Clk10 Disciplining enabled and phases aligned phase. Absolute time is aligned as described. Sample Clock Generation is started using a FTE trigger. Measurement The NI-5761R s acquires 1024 sample of channel 0 when it detects a FTE Trigger on the Trigger bus. The master collects the records and calculates the delay between master and slave. The time delays are logged to disk. 19

20 Triggering NI-5761R Performance one hour 20

21 Triggering NI-5761R Performance 72 hours *This is filtered data see notes 21

22 PXI_Clk10 Stability over 72 hours for Compare 22

23 WP 14

24 Cost estimate Example Electronics for beam former

25 Possible cost reduction Configurable vs Modular (Mechasnical design) FPGA cost optimisation Channel density Delay lines Component prices reduction Specification adjustment 25

26 System Engineering

27 Prototype System example PXIe 1085 Chassis Capabilities 60 AI channels/chassis 10 Gb/s (1.25 GB/s) per hop Each FPGA module sources & sinks a 10 Gb/s stream To RMC-8355 with 10 GbE PCIe card Each green hop is 10 Gb/s sustained and 4-5 us of latency 1085 Chassis Configuration (1) PXIe-8381 Gen2 x8 MXI (1) PXIe-8384 Gen2 x8 MXI (1) PXIe-???? T&S Module (15) PXIe-7976R FlexRIO (15) NI 5734 Digitizer FAMs 27

28 What we need to consider

29 Manufacturing Products Access to chip suppliers Roadmap visibility Lifetime buy options Reliability / availability Volume manufacturing Reliability testing Specialty testing Radiation, magnetic field, altitude Lifecycle management Long term availability Compliance / Certifications ITAR and others CE, ROHS, China ROHS, WEEE Environmental conditions 29

30 Environmental Testing System Reliability

31 System Reliability NI System Reliability Lab Mission: Assess the reliability of National Instruments product-based systems and drive product improvements Created to focus on system reliability for the o Compact RIO and PXI / PXIe hardware platforms o LabVIEW software platform MTTF for PXIe-1075 is >20yrs MTTF for crio system (controller and chassis) is about 38yrs 31

32 System Reliability PXI/PXIe Reliability Testing 22 systems 20 systems at room temperature and 2 systems in temperature chamber (cycles between 5 C and 50 C three times per day) 5 systems running on dirty power 3 different hardware configurations 32 test applications running on Windows and RT 24/7 execution during missions 32

33 System Reliability crio Reliability Testing 40 systems 32 systems at room temperature and 8 systems in temperature chamber (cycles between -40 and 70 C three times per day) 8 systems running on dirty power 4 unique crio applications written for RT and FPGA (10 systems for each) 24/7 execution during mission We run one or two missions per year Mission time ranges from 3 to 12 months 33

34 System Reliability Temperature Chamber Cycle Temperature three times per dayfor months 2 to 8 Systems run for months at time in this environment PXI / PXIe 5 C to 50 C crio - 40 C to 70 C 34

35 System Reliability Dirty Power Test Station [Simulates a bad power grid] 5 to 8 Systems run for months at time in this environment Vary frequency from 47 to 63 Hz Vary voltage level from 90 to 264 V 35

36 RASM

37 RASM = Reliability, Usability Availability, Serviceability, Manageability Customers require a continual output of features and innovation Features RASM Customers highly value stability, reliability, and availability 37

38 RASM Defined Reliability A system operates as intended, without failure or down time, and satisfies the desired performance requirements. Availability The measure of how often a systems is able to perform its intended function, even in the midst of failures. Features and aspects of the system design contributing to ease of diagnosis and repair. Serviceability The extent to which a system can be controlled, supervised and monitored. Manageability 38

39 Approaches to Maximizing Uptime Supplier quality Reliability lab testing Simplified design Site surveys Eliminate the failure Convert failure to a planned outage Predictive failure analysis/alerts Planned maintenance Replacement inventories Redundancy Remote diagnostics ECC, event logs, etc. Tolerate the failure 39

40 Life Cycle Management

41 Sustainment-Dominated Life Cycle Long operation and support phases Operation & Support Component A.1 Component A.2 Component A.3 Component A.4 41

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