Building Interfaces with Arria 10 High-Speed Transceivers

Transcription

1 Building Interfaces with Arria 10 High-Speed Transceivers Course Description In this course, you will learn how you can build high-speed, gigabit interfaces using the 20- nm embedded transceivers found in Arria 10. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design. Lastly, you will be made aware of common gotchas that occur in transceiver designs and what steps you can take to avoid them. The course contains hands-on labs to experience with Arria 10 transceiver IP cores configuration, simulation, using the transceiver Toolkit (optional), and enabling Arria 10 transceiver reconfiguration in the Native PHY IP core. Course Duration 2 days

2 Goals 1. Implement high-speed serial protocols in Altera 20-nm embedded transceivers 2. Optimize analog settings to improve behavior using Altera tools 3. Employ transceiver reconfiguration to dynamically change transceiver behavior insystem 4. Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations Intended Users Hardware engineers who develop with Arria 10 and would like to build gigabit interfaces Previous Knowledge FPGA design Quartus and TimeQuest Modelsim SignalTap II Note: familiarity with high-speed interfaces and transmission protocols is helpful, nut not required Course Material 1. Synthesizer and Place & Route: Quartus Prime 2. Course book (including labs) 3. Stratix V or Arria 10 Evaluation board (optional)

3 Table of Contents Day #1 Transceiver Design Creation Introduction to Altera s Transceivers o What is a transceiver? o Definition: MAC, PCS, PMA o Arria 10 FPGAs & SoC transceivers families Transceiver Design Creation o Arria 10 transceiver documentation o Transceiver design creation o Transceiver locations o Transceiver layout o Non-bonded versus bonded o Aria 10 GX versus GT channels o Aria 10 GT device: 72 transceiver device example RX Datapath o Receiver path definition o Receiver PMA blocks o RX PMA functional block descriptions o RX polarity inversion o Receiver simplified block diagram o RX PCS architecture support o Example transceiver PCS layout o RX standard PCS functional blocks and support o RX standard PCS functional block descriptions o RX standard PCS low latency mode o RX enhanced PCS functional blocks and support o RX 10G PCS functional block descriptions o RX enhanced PCS low latency mode o RX PCS direct mode o RX PCIe GEN3 PCS functional blocks o RX PCIe GEN3 PCS functional block descriptions TX Datapath o Transmitter path definition o Transmitter block diagram o TX PCS architecture support o TX standard PCS functional blocks o TX PCS functional block descriptions o TX standard PCS low latency mode o TX enhanced PCS functional blocks

4 o TX 10G functional PCS block descriptions o TX enhanced PCS low latency mode o TX PCS direct mode o TX PCIe Gen3 PCS functional blocks o TX PCIe Gen3 PCS functional block descriptions o TX polarity inversion o Transmitter simplified block diagram o Transmitter PMA functional blocks o Which blocks/configuration do I need? Clocking o Transceiver clocking o Receive path clock generation and example o Transmit path clock generation and example o ATX PLLs o Fractional PLLs o CMU PLLs o Local CGB o Master CGB o Input reference clock sources o Input reference clock pins o Reference clock network o PLL cascading o RX pins o FPGA fabric clocks Reset o Transceiver reset o Transceiver reset control signals Building a Arria 10 PHY layer o Introduction o Aria 10 PHY layer implementation diagram o Transceiver design flow o IP parameter editors o IP output files for compilation o PHY IP output files for simulation o Using Qsys to build system references o Transceiver PHY IP cores o Available PHY IP cores o Arria 10 native PHY IP core o Native PHY IP interfaces o Primary clock signals o Parallel data interfaces o Parallel data interface bit assignment o PCS/PMA control and status interface o Serial interface o Reset control and status interfaces o Transceiver PLL IP

5 o Steps to configuring transceiver PLL IP o Transceiver PLL IP parameters o ATX PLL IP parameter editor o fpll IP parameter editor o CMU PLL parameter editor o Transceiver PLL clock signals o Transceiver PLL status/control signals o Transceiver PHY reset controller IP core o Transceiver PHY reset controller parameter editor o Transceiver PHY reset controller signals o Interconnecting the transceiver IP cores o External transceiver IP core connections Lab #1: Configuring Arria 10 Transceiver IP Cores Day #2 Link Bring-Up Setting Static Analog Parameters o RX buffer analog SI features o CTLE o DFE o Adaptive parametric tuning engine o TX buffer analog SI features o Setting static Analog parameters Link Analysis & Simulation using JNEye Tool o Transceiver link simulation o Altera JNEye technology o JNEye overview o JNEye user interface and correlations o JNEye device and link component support o Simulation modes in JNEye tool o JNEye link simulation o Automatic link optimization and adaptation Transceiver Toolkit o Quartus Prime transceiver toolkit o Transceiver toolkit GUI o Features overview o Auto sweep o EyeQ o EyeQ heat display

6 o Enabling transceiver Toolkit support o ADME o Example user flow Set up board(s) Open transceiver Toolkit Load design Link hardware resources Identify channels Run tests o BER reports o Manual PMA control Lab #2: Using the Transceiver Toolkit Transceiver Reconfiguration Introduction o What is transceiver reconfiguration? o Transceiver reconfiguration uses o So I have to employ transceiver reconfiguration? o Reconfiguration features, tools and concepts overview o Reconfiguration interface o Arbitration o Configuration files o Selecting configuration files (native PHY) o Reconfiguration profiles o Adding reconfiguration profiles (native PHY) o Embedded reconfiguration streamer o Transceiver reconfiguration flow Performing Transceiver Reconfiguration o Performing transceiver reconfiguration Turning on transceiver reconfiguration Connect reconfiguration interface to master Place channels/plls in reset Perform Avalon-MM transactions Recalibrate channels and PLLs Release resets Transceiver Reconfiguration Examples o Calibration overview o Calibration register controls o Example arbitration registers o PMA reconfiguration o Configurable PMA settings o Example PMA register addresses o Analog settings in configuration files o Channel and PLL reconfiguration overview

7 o Steps for channel and PLL reconfiguration Configure the native PHY and transceiver PLL for base instance(s) Configure the native PHY and transceiver PLL for modified instance(s) Use reconfiguration profiles and a single.qsys file for base and each modification Use separate.qsys file for each base and modified instance o Using IP guided reconfiguration flows o Unsupported reconfiguration Lab #3: Transceiver Reconfiguration Profiles Transceiver Design Best Practices Resource Optimization o Choosing the best TX PLL (ATX PLL/fPLL/CMU PLL) o Merging TX PLLs o Why is understanding clocking important? o Transceiver clocking o Reference clocks o Reference clock pin recommendations o Internal clocking (TX clock network x1/x6/xn) o PLL feedback compensation path bonding o GT clock network o Native PHY IP channel clocks o Native PHY FPGA-transceiver interface clocks o Sharing FPGA-Transceiver clocks o Additional FPGA clocking o Channel placement guidelines o Introducing the BluePrint Platform Designer o Manual placement restrictions o Non-bonded channel placement restrictions o GT transceiver bank layout o Example GT triplet configurations o PMA vs PMA and PCS bonding o x6/xn vs. PLL feedback compensation PMA bonding o PMA and PCS bonding o Channel merging Planning Reset Control o Reset solutions review o When is transceiver resetting required? o Using the reset controller IP o Possible additional reset connection Debugging o Loopback o Loopback types

8 PHY IP Versions Pin Connection Guidelines o Pin connection example (RREF pin)