Physical View of the Stratix 10 L-Tile Transceiver Registers

Transcription

1 Physical View of the Stratix 10 L-Tile Transceiver Registers MNL Subscribe Send Feedback

2 Contents Contents 1 Physical View of the L-Tile Transceiver Registers ATX_PLL Physical Register Map ATX_PLL_0 Register map ATX_PLL_103 Register map ATX_PLL_106 Register map ATX_PLL_108 Register map ATX_PLL_109 Register map ATX_PLL_10C Register map ATX_PLL_10D Register map ATX_PLL_10E Register map ATX_PLL_10F Register map ATX_PLL_110 Register map ATX_PLL_11F Register map ATX_PLL_400 Register map ATX_PLL_401 Register map ATX_PLL_402 Register map ATX_PLL_403 Register map ATX_PLL_404 Register map ATX_PLL_405 Register map ATX_PLL_410 Register map ATX_PLL_480 Register map ATX_PLL_4E0 Register map ATX_PLL_540 Register map ATX_PLL_541 Register map CMU_PLL Physical Register Map CMU_PLL_0 Register map CMU_PLL_100 Register map CMU_PLL_11D Register map CMU_PLL_132 Register map CMU_PLL_133 Register map CMU_PLL_134 Register map CMU_PLL_135 Register map CMU_PLL_136 Register map CMU_PLL_137 Register map CMU_PLL_138 Register map CMU_PLL_139 Register map CMU_PLL_13A Register map CMU_PLL_13B Register map CMU_PLL_13C Register map CMU_PLL_141 Register map CMU_PLL_142 Register map CMU_PLL_14F Register map CMU_PLL_152 Register map CMU_PLL_153 Register map CMU_PLL_154 Register map CMU_PLL_155 Register map CMU_PLL_156 Register map

3 Contents CMU_PLL_166 Register map CMU_PLL_16A Register map CMU_PLL_16B Register map CMU_PLL_16C Register map CMU_PLL_16D Register map CMU_PLL_16E Register map CMU_PLL_16F Register map CMU_PLL_170 Register map CMU_PLL_172 Register map CMU_PLL_175 Register map CMU_PLL_404 Register map CMU_PLL_405 Register map CMU_PLL_410 Register map CMU_PLL_480 Register map CMU_PLL_4E0 Register map CMU_PLL_540 Register map CMU_PLL_541 Register map FPLL Physical Register Map FPLL_0 Register map FPLL_10A Register map FPLL_10B Register map FPLL_10D Register map FPLL_10E Register map FPLL_10F Register map FPLL_110 Register map FPLL_111 Register map FPLL_114 Register map FPLL_117 Register map FPLL_118 Register map FPLL_119 Register map FPLL_11A Register map FPLL_11B Register map FPLL_11C Register map FPLL_11D Register map FPLL_11E Register map FPLL_11F Register map FPLL_120 Register map FPLL_121 Register map FPLL_12A Register map FPLL_12B Register map FPLL_12C Register map FPLL_133 Register map FPLL_135 Register map FPLL_141 Register map FPLL_142 Register map FPLL_400 Register map FPLL_401 Register map FPLL_402 Register map FPLL_403 Register map FPLL_404 Register map FPLL_405 Register map

4 Contents FPLL_410 Register map FPLL_480 Register map FPLL_4E0 Register map FPLL_540 Register map FPLL_541 Register map PCS Physical Register Map PCS_0 Register map PCS_6 Register map PCS_7 Register map PCS_8 Register map PCS_A Register map PCS_B Register map PCS_C Register map PCS_D Register map PCS_E Register map PCS_F Register map PCS_13 Register map PCS_15 Register map PCS_18 Register map PCS_19 Register map PCS_21 Register map PCS_22 Register map PCS_24 Register map PCS_28 Register map PCS_29 Register map PCS_2C Register map PCS_2D Register map PCS_2E Register map PCS_2F Register map PCS_30 Register map PCS_31 Register map PCS_32 Register map PCS_33 Register map PCS_34 Register map PCS_35 Register map PCS_36 Register map PCS_37 Register map PCS_38 Register map PCS_39 Register map PCS_3A Register map PCS_3B Register map PCS_3C Register map PCS_3D Register map PCS_3E Register map PCS_3F Register map PCS_40 Register map PCS_41 Register map PCS_42 Register map PCS_43 Register map PCS_44 Register map PCS_45 Register map

5 Contents PCS_46 Register map PCS_47 Register map PCS_48 Register map PCS_49 Register map PCS_4A Register map PCS_4B Register map PCS_4C Register map PCS_4D Register map PCS_4E Register map PCS_4F Register map PCS_50 Register map PCS_51 Register map PCS_52 Register map PCS_53 Register map PCS_54 Register map PCS_55 Register map PCS_56 Register map PCS_57 Register map PCS_58 Register map PCS_59 Register map PCS_5A Register map PCS_5B Register map PCS_60 Register map PCS_63 Register map PCS_64 Register map PCS_65 Register map PCS_70 Register map PCS_71 Register map PCS_72 Register map PCS_73 Register map PCS_74 Register map PCS_75 Register map PCS_76 Register map PCS_77 Register map PCS_78 Register map PCS_79 Register map PCS_7A Register map PCS_7B Register map PCS_7C Register map PCS_7D Register map PCS_7E Register map PCS_7F Register map PCS_80 Register map PCS_81 Register map PCS_82 Register map PCS_84 Register map PCS_85 Register map PCS_86 Register map PCS_87 Register map PCS_88 Register map PCS_8A Register map

6 Contents PCS_8B Register map PCS_8C Register map PCS_8E Register map PCS_8F Register map PCS_91 Register map PCS_96 Register map PCS_97 Register map PCS_A0 Register map PCS_A2 Register map PCS_A3 Register map PCS_A6 Register map PCS_A7 Register map PCS_AA Register map PCS_AC Register map PCS_AE Register map PCS_AF Register map PCS_B0 Register map PCS_B2 Register map PCS_B3 Register map PCS_B8 Register map PCS_BD Register map PCS_C2 Register map PCS_C3 Register map PCS_C4 Register map PCS_C5 Register map PCS_C7 Register map PCS_D1 Register map PCS_D2 Register map PCS_D3 Register map PCS_D4 Register map PCS_D5 Register map PCS_D6 Register map PCS_D7 Register map PCS_D8 Register map PCS_DC Register map PCS_DD Register map PCS_DE Register map PCS_DF Register map PCS_E0 Register map PCS_E1 Register map PCS_E2 Register map PCS_E3 Register map PCS_E4 Register map PCS_E7 Register map PCS_200 Register map PCS_201 Register map PCS_202 Register map PCS_203 Register map PCS_204 Register map PCS_205 Register map PCS_206 Register map

7 Contents PCS_207 Register map PCS_208 Register map PCS_209 Register map PCS_20A Register map PCS_20B Register map PCS_20C Register map PCS_20D Register map PCS_20E Register map PCS_20F Register map PCS_210 Register map PCS_211 Register map PCS_212 Register map PCS_213 Register map PCS_214 Register map PCS_215 Register map PCS_216 Register map PCS_217 Register map PCS_218 Register map PCS_219 Register map PCS_21A Register map PCS_21B Register map PCS_21C Register map PCS_21D Register map PCS_21E Register map PCS_21F Register map PCS_220 Register map PCS_221 Register map PCS_222 Register map PCS_223 Register map PCS_224 Register map PCS_225 Register map PCS_226 Register map PCS_227 Register map PCS_22D Register map PCS_22E Register map PCS_22F Register map PCS_230 Register map PCS_232 Register map PCS_233 Register map PCS_234 Register map PCS_32B Register map PCS_32C Register map PCS_32D Register map PCS_32E Register map PCS_330 Register map PCS_331 Register map PMA Physical Register Map PMA_0 Register map PMA_100 Register map PMA_103 Register map PMA_104 Register map

8 Contents PMA_105 Register map PMA_106 Register map PMA_107 Register map PMA_108 Register map PMA_109 Register map PMA_10A Register map PMA_10C Register map PMA_10D Register map PMA_10F Register map PMA_110 Register map PMA_111 Register map PMA_112 Register map PMA_114 Register map PMA_117 Register map PMA_118 Register map PMA_119 Register map PMA_11A Register map PMA_11B Register map PMA_11C Register map PMA_11D Register map PMA_11F Register map PMA_120 Register map PMA_121 Register map PMA_123 Register map PMA_124 Register map PMA_12F Register map PMA_132 Register map PMA_133 Register map PMA_135 Register map PMA_136 Register map PMA_137 Register map PMA_138 Register map PMA_139 Register map PMA_13A Register map PMA_13B Register map PMA_13C Register map PMA_140 Register map PMA_141 Register map PMA_142 Register map PMA_143 Register map PMA_144 Register map PMA_145 Register map PMA_148 Register map PMA_149 Register map PMA_14C Register map PMA_14D Register map PMA_14E Register map PMA_14F Register map PMA_150 Register map PMA_151 Register map PMA_152 Register map

9 Contents PMA_153 Register map PMA_154 Register map PMA_155 Register map PMA_156 Register map PMA_157 Register map PMA_158 Register map PMA_159 Register map PMA_15A Register map PMA_15B Register map PMA_15E Register map PMA_160 Register map PMA_163 Register map PMA_166 Register map PMA_167 Register map PMA_168 Register map PMA_169 Register map PMA_16A Register map PMA_16B Register map PMA_16C Register map PMA_16D Register map PMA_16E Register map PMA_16F Register map PMA_170 Register map PMA_173 Register map PMA_174 Register map PMA_175 Register map PMA_176 Register map PMA_177 Register map PMA_178 Register map PMA_179 Register map PMA_17A Register map PMA_17B Register map PMA_17C Register map PMA_17D Register map PMA_17E Register map PMA_17F Register map PMA_400 Register map PMA_401 Register map PMA_402 Register map PMA_403 Register map PMA_404 Register map PMA_405 Register map PMA_412 Register map PMA_413 Register map PMA_480 Register map PMA_481 Register map PMA_4E0 Register map PMA_4E1 Register map PMA_4E2 Register map PMA_500 Register map PMA_507 Register map

10 Contents PMA_513 Register map PMA_540 Register map PMA_541 Register map Document Revision History

11 1 Physical View of the L-Tile Transceiver Registers Access these registers using the reconfiguration interface. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter of the Stratix 10 L-Tile Transceiver PHY User Guide for details about how to write to and read from these registers. Related Links Reconfiguration Interface and Dynamic Reconfiguration 1.1 ATX_PLL Physical Register Map ATX_PLL Physical Register Map Summary FPGA Manager Module Configuration Data Offset Affected Attributes 0 pcs_arbiter_ctrl pcs_cal_done pcs_arbiter_ctrl:avmm2 bus Arbitration control pcs_cal_done:avmm2 calibration done 103 lccmu_mode lccmu_mode:sets the LC-CMU operating mode 106 clk_divider ref_clk_div hclk_en clk_divider:select clock divide by 2 ref_clk_div:set the N input counter divide value hclk_en:enable hclk output 108 lcnt_divide lcnt_divide:l counter divide value 109 mcnt_divide mcnt_divide:m counter divide value 10C dsm_fractional_division dsm_fractional_division:fractional divide value for fractional PLL 10D dsm_fractional_division dsm_fractional_division:fractional divide value for fractional PLL 10E dsm_fractional_division dsm_fractional_division:fractional divide value for fractional PLL 10F dsm_fractional_division dsm_fractional_division:fractional divide value for fractional PLL 110 pll_fractional_value_ready pfd_delay_compensation pll_fractional_value_ready:indicates that the fractional K value is valid pfd_delay_compensation:selects different delay compensation paths in PFD 11F pfd_pulse_width pfd_pulse_width:selects different delay compensation paths in PFD 400 atx_address_id[7: atx_address_id[7::ip Identifier 401 atx_address_id[15:8] atx_address_id[15:8]:ip Identifier 402 atx_address_id[23:16] atx_address_id[23:16]:ip Identifier 403 atx_address_id[31:24] atx_address_id[31:24]:ip Identifier 404 atx_status_register_enable atx_status_register_enable:status Register Enabled Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

12 Offset Affected Attributes RESERVED 405 atx_control_register_enable RESERVED 410 atx_mcgb_enable RESERVED 480 atx_pll_locked atx_cal_busy atx_avmm_busy RESERVED RESERVED: atx_control_register_enable:control Register Enabled RESERVED: atx_mcgb_enable:master CGB Enabled RESERVED: atx_pll_locked:pll_locked atx_cal_busy:pll_cal_busy atx_avmm_busy:avmm_busy RESERVED: 4E0 atx_pll_powerdown atx_override_pll_powerdown RESERVED atx_pll_powerdown:pll_powerdown atx_override_pll_powerdown:override_pll_powerdown RESERVED: 540 atx_cfg_sel S10_XR_OFFSET_EMBED_RCFG_ BCAST_EN atx_cfg_load atx_cfg_sel:cfg_sel S10_XR_OFFSET_EMBED_RCFG_BCAST_EN:bcast_en atx_cfg_load:cfg_load 541 atx_rcfg_busy atx_rcfg_busy:rcfg_busy ATX_PLL_0 Register map Physical register with avalon address of 0 Base Address :0 Bit Name Access 0[ pcs_arbiter_ctrl[ pcs_arbiter_ctrl: AVMM2 bus Arbitration control Avalon address(es): 0.0 AVMM2_ARBITER_PLD_SEL PLD control of AVMM 2 Interface AVMM2_ARBITER_UC_SEL Microcontroller control of AVMM 2 Interface 0[1] pcs_cal_done[ pcs_cal_done: AVMM2 calibration done Avalon address(es): 0.1 AVMM2_CAL_DONE_ASSERT calibration is done AVMM2_CAL_DONE_DEASSERT calibration is not done ATX_PLL_103 Register map Physical register with avalon address of

13 Base Address :103 Bit Name Access 103[ lccmu_mode[ lccmu_mode: Sets the LC-CMU operating mode Avalon address(es): LCCMU_PD LCCMU_RESET The LCCMU is powered down The LCCMU is powered down LCCMU_NORMAL The LCCMU is operational ATX_PLL_106 Register map Physical register with avalon address of 106 Base Address :106 Bit Name Access 106[6] clk_divider[ clk_divider: Select clock divide by 2 Avalon address(es): DIV2_OFF Disable divide-by-2 mode DIV2_ON Enable Divide-by-2 mode, output clock will be divide by 2 106[3: 2] ref_clk_div[1: ref_clk_div: Set the N input counter divide value Avalon address(es): 106.3:2 Correspond to bit(s) [1: in the following configurations: 2'b00 2'b01 2'b10 2'b11 1 The N counter is bypass mode 2 The N counter is divide by 2 mode 4 The N counter is divide by 4 mode 8 The N counter is divide by 8 mode 106[5] hclk_en[ hclk_en: enable hclk output Avalon address(es): HCLK_DISABLED disable hclk and iqtxrxclk output 13

14 Bit Name Access HCLK_ENABLE enable hclk and iqtxrxclk output ATX_PLL_108 Register map Physical register with avalon address of 108 Base Address :108 Bit Name Access 108[2: lcnt_divide[2: lcnt_divide: L counter divide value Avalon address(es): 108.2:0 Correspond to bit(s) [2: in the following configurations: 3'b000 1 Set the L counter to divide by 1 3'b001 2 Set the L counter to divide by 2 3'b010 4 Set the L counter to divide by 4 3'b011 8 Set the L counter to divide by 8 3'b Set the L counter to divide by ATX_PLL_109 Register map Physical register with avalon address of 109 Base Address :109 Bit Name Access 109[7: mcnt_divide[7: mcnt_divide: M counter divide value Avalon address(es): 109.7:0 Correspond to bit(s) [7: in the following configurations: DIRECT MAPPED mcnt_divide[7: ATX_PLL_10C Register map Physical register with avalon address of 10C Base Address :10C 14

15 Bit Name Access 10C[7: dsm_fractional_di vision[7: Part of dsm_fractional_division: Fractional divide value for fractional PLL Avalon address(es): 10F.7:0 10E.7:0 10D.7:0 10C.7:0 Correspond to bit(s) [7: in the following configurations: DIRECT MAPPED pll_fractional_division[7: ATX_PLL_10D Register map Physical register with avalon address of 10D Base Address :10D Bit Name Access 10D[7: dsm_fractional_di vision[15:8] Part of dsm_fractional_division: Fractional divide value for fractional PLL Avalon address(es): 10F.7:0 10E.7:0 10D.7:0 10C.7:0 Correspond to bit(s) [15:8] in the following configurations: DIRECT MAPPED pll_fractional_division[15:8] ATX_PLL_10E Register map Physical register with avalon address of 10E Base Address :10E Bit Name Access 10E[7: dsm_fractional_di vision[23:16] Part of dsm_fractional_division: Fractional divide value for fractional PLL Avalon address(es): 10F.7:0 10E.7:0 10D.7:0 10C.7:0 Correspond to bit(s) [23:16] in the following configurations: DIRECT MAPPED pll_fractional_division[23:16] ATX_PLL_10F Register map Physical register with avalon address of 10F Base Address :10F 15

16 Bit Name Access 10F[7: dsm_fractional_di vision[31:24] Part of dsm_fractional_division: Fractional divide value for fractional PLL Avalon address(es): 10F.7:0 10E.7:0 10D.7:0 10C.7:0 Correspond to bit(s) [31:24] in the following configurations: DIRECT MAPPED pll_fractional_division[31:24] ATX_PLL_110 Register map Physical register with avalon address of 110 Base Address :110 Bit Name Access 110[ pll_fractional_val ue_ready[ pll_fractional_value_ready: Indicates that the fractional K value is valid Avalon address(es): PLL_K_NOT_READY Fractional value is not valid PLL_K_READY Fractional value is valid 110[7: 6] pfd_delay_compe nsation[1: pfd_delay_compensation: Selects different delay compensation paths in PFD Avalon address(es): 110.7:6 Correspond to bit(s) [1: in the following configurations: 2'b00 2'b01 2'b10 2'b11 NORMAL_DELAY Selects normal delay path REF_COMPENSATED_DELAY Selects additional delay to compensate reference path FB_COMPENSATED_DELAY Selects additional delay to compensate feedback path UNUSED_DELAY Usused ATX_PLL_11F Register map Physical register with avalon address of 11F Base Address :11F 16

17 Bit Name Access 11F[6: 5] pfd_pulse_width[ 1: pfd_pulse_width: Selects different delay compensation paths in PFD Avalon address(es): 11F.6:5 Correspond to bit(s) [1: in the following configurations: 2'b00 2'b01 2'b10 2'b11 PULSE_WIDTH_SETTING0 Normal PFD pulse width PULSE_WIDTH_SETTING1 Normal PFD pulse width + 200ps PULSE_WIDTH_SETTING2 Normal PFD pulse width + 250ps PULSE_WIDTH_SETTING3 Normal PFD pulse width + 300ps ATX_PLL_400 Register map Physical register with avalon address of 400 Base Address :400 Bit Name Access 400[7: atx_address_id[7 :[7: atx_address_id[7:: IP Identifier Avalon address(es): 400.7:0 read-only Correspond to bit(s) [7: in the following configurations: DIRECT MAPPED atx_address_id[7: Unique identifier for the ATX PLL instance ATX_PLL_401 Register map Physical register with avalon address of 401 Base Address :401 Bit Name Access 401[7: atx_address_id[1 5:8][7: atx_address_id[15:8]: IP Identifier Avalon address(es): 401.7:0 Correspond to bit(s) [7: in the following configurations: read-only DIRECT MAPPED atx_address_id[15:8] ATX_PLL_402 Register map Physical register with avalon address of

18 Base Address :402 Bit Name Access 402[7: atx_address_id[2 3:16][7: atx_address_id[23:16]: IP Identifier Avalon address(es): 402.7:0 Correspond to bit(s) [7: in the following configurations: read-only DIRECT MAPPED atx_address_id[23:16] ATX_PLL_403 Register map Physical register with avalon address of 403 Base Address :403 Bit Name Access 403[7: atx_address_id[3 1:24][7: atx_address_id[31:24]: IP Identifier Avalon address(es): 403.7:0 read-only Correspond to bit(s) [7: in the following configurations: DIRECT MAPPED atx_address_id[31:24] ATX_PLL_404 Register map Physical register with avalon address of 404 Base Address :404 Bit Name Access 404[ atx_status_regist er_enable[ atx_status_register_enable: Status Register Enabled Avalon address(es): read-only DIRECT MAPPED atx_status_register_enable[0: Indicates if the status registers have been enabled. indicates the feature is enabled. 404[7: 1] RESERVED[6: RESERVED: Avalon address(es): 404.7:1 Correspond to bit(s) [6: in the following configurations: 18

19 ATX_PLL_405 Register map Physical register with avalon address of 405 Base Address :405 Bit Name Access 405[ atx_control_regis ter_enable[ atx_control_register_enable: Control Register Enabled Avalon address(es): read-only DIRECT MAPPED atx_control_register_enable[0: Indicates if the control registers have been enabled. indicates the feature is enabled. 405[7: 1] RESERVED[6: RESERVED: Avalon address(es): 405.7:1 Correspond to bit(s) [6: in the following configurations: ATX_PLL_410 Register map Physical register with avalon address of 410 Base Address :410 Bit Name Access 410[ atx_mcgb_enabl e[ atx_mcgb_enable: Master CGB Enabled Avalon address(es): read-only DIRECT MAPPED atx_mcgb_enable[0: Indicates if the Master CGB is enabled. indicates the master CGB is enabled. 410[7: 1] RESERVED[6: RESERVED: Avalon address(es): 410.7:1 Correspond to bit(s) [6: in the following configurations: ATX_PLL_480 Register map Physical register with avalon address of 480 Base Address :480 Bit Name Access 480[ atx_pll_locked[ atx_pll_locked: pll_locked read-only 19

20 Bit Name Access Avalon address(es): Indicates if the ATX PLL is locked. indicates the ATX PLL is locked [1] atx_cal_busy[ atx_cal_busy: pll_cal_busy Avalon address(es): read-only 0 Indicates the ATX PLL calibration status. indicates the ATX PLL is currently being calibrated [2] atx_avmm_busy[ atx_avmm_busy: avmm_busy Avalon address(es): read-only 0 "When, PreSICE has control of the internal configuration bus. When, user has control of the internal configuraiton bus. Refer to Arbitration section for more details." 1 480[7: 3] RESERVED[4: RESERVED: Avalon address(es): 480.7:3 Correspond to bit(s) [4: in the following configurations: ATX_PLL_4E0 Register map Physical register with avalon address of 4E0 Base Address :4E0 Bit Name Access 4E0[ atx_pll_powerdo wn[ atx_pll_powerdown: pll_powerdown Avalon address(es): 4E0.0 0 Drives the PLL powerdown when the Override is set. 20

21 Bit Name Access 1 4E0[1] atx_override_pll_ powerdown[ atx_override_pll_powerdown: override_pll_powerdown Avalon address(es): 4E0.1 DIRECT MAPPED atx_override_pll_powerdown[0: Selects whether the receiver listens to the ADME pll_powerdown register or the pll_powerdown port. indicates the receiver will listen to the ADME pll_powerdown. 4E0[7: 2] RESERVED[5: RESERVED: Avalon address(es): 4E0.7:2 Correspond to bit(s) [5: in the following configurations: ATX_PLL_540 Register map Physical register with avalon address of 540 Base Address :540 Bit Name Access 540[2: atx_cfg_sel[2: atx_cfg_sel: cfg_sel Avalon address(es): 540.2:0 Correspond to bit(s) [2: in the following configurations: DIRECT MAPPED atx_cfg_sel[2: Selects the Configuration from the list of configurations specified by you in the Native PHY IP. It represents the profile number between the GUI multiprofile generation. 540[6] S10_XR_OFFSET _EMBED_RCFG_B CAST_EN[ S10_XR_OFFSET_EMBED_RCFG_BCAST_EN: bcast_en Avalon address(es): "Selection to broadcast the profile selected using register cfg_sel to the channels.- Broadcast the same profile to all the channels,- Single Channel" 1 540[7] atx_cfg_load[ atx_cfg_load: cfg_load Avalon address(es):

22 Bit Name Access 0 "Set to to initiate streaming, self-clearing bit" ATX_PLL_541 Register map Physical register with avalon address of 541 Base Address :541 Bit Name Access 541[ atx_rcfg_busy[ atx_rcfg_busy: rcfg_busy Avalon address(es): read-only 0 This bit indicates the status of the profile streaming. - Streaming is in progress. - Streaming is complete CMU_PLL Physical Register Map CMU_PLL Physical Register Map Summary FPGA Manager Module Configuration Data Offset Affected Attributes 0 pcs_arbiter_ctrl pcs_cal_done pcs_hip_cal_en pcs_cal_reserved pcs_arbiter_ctrl:avmm1 bus Arbitration control pcs_cal_done:avmm1 calibration done pcs_hip_cal_en:avmm1 HIP Enable for Calibration pcs_cal_reserved:avmm1 calibration reserve bits 100 pm_cr_tx_rx_uc_txvod_cal pm_cr_tx_rx_uc_txvod_cal: 11D loopback_mode loopback_mode:jitter generation 132 set_cdr_vco_speed_fix cdr_powerdown_mode set_cdr_vco_speed_fix chgpmp_vccreg reverse_serial_loopback set_cdr_vco_speed_pciegen3 133 chgpmp_vccreg chgpmp_current_up_pd set_cdr_vco_speed_fix:adjust cdr VCO speed. Default bits settings cdr_powerdown_mode:select powerdown state of the CDR set_cdr_vco_speed_fix:adjust cdr VCO speed. Default bits settings chgpmp_vccreg:selects different level to boost CP regulator output reverse_serial_loopback:enable the reverse serial loopback path set_cdr_vco_speed_pciegen3:adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. chgpmp_vccreg:selects different level to boost CP regulator output 22

23 Offset Affected Attributes chgpmp_current_up_pd:select the charge pump UP current in lock to data mode 134 set_cdr_vco_speed_fix set_cdr_vco_speed_fix:adjust cdr VCO speed. Default bits settings 135 lf_resistor_pfd lf_resistor_pd lf_ripple_cap chgpmp_current_up_trim set_cdr_vco_speed_fix 136 set_cdr_vco_speed_fix vco_overrange_voltage vco_underrange_voltage 137 set_cdr_vco_speed diag_loopback_enable lf_resistor_pfd:select the loop filter resistance in lock to reclk mode lf_resistor_pd:select the loop filter resistance in lock to data mode lf_ripple_cap:select the loop filter ripple cap size chgpmp_current_up_trim:select different triming current in PD mode set_cdr_vco_speed_fix:adjust cdr VCO speed. Default bits settings set_cdr_vco_speed_fix:adjust cdr VCO speed. Default bits settings vco_overrange_voltage:select the VCO overrange detector trip point vco_underrange_voltage:select the VCO underrange detector trip point set_cdr_vco_speed:adjust cdr VCO speed. Default bits settings diag_loopback_enable:enable/disable the diagnostic loopback 138 set_cdr_vco_speed_pciegen3 set_cdr_vco_speed_pciegen3:adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. 139 chgpmp_current_pfd chgpmp_current_dn_pd chgpmp_replicate pd_fastlock_mode chgpmp_current_pfd:select the charge pump current in lock to refclk mode chgpmp_current_dn_pd:select the charge pump DOWN current in lock to data mode chgpmp_replicate:enable/disable the replica bias circuit in the charge pump pd_fastlock_mode:enable/disable fast locking in PD mode 13A pfd_l_counter pd_l_counter pfd_l_counter:l counter divide value when the CDR is in lock to reference mode pd_l_counter:select the L Counter divider value when the CDR is in PD mode 13B mcnt_div mcnt_div:select the M feedback counter division value 13C ncnt_div set_cdr_vco_speed_pciegen3 reverse_serial_loopback loopback_mode ncnt_div:select the N refclk counter division value set_cdr_vco_speed_pciegen3:adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. reverse_serial_loopback:enable the reverse serial loopback path loopback_mode:jitter generation 141 xpm_iqref_mux_iqclk_sel xmux_refclk_src xpm_iqref_mux_iqclk_sel:reference clock for top FPLL from IQCLK network xmux_refclk_src:select the CDR reference clk src 142 loopback_mode loopback_mode:jitter generation 14F set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by 3 23

24 Offset Affected Attributes 155 set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by set_cdr_input_freq_range set_cdr_input_freq_range:take input frequency after N counter divide by rate_sw_flag rate_sw_flag: 16A 16B 16C 16D 16E 16F pm_cr_tx_rx_scratch0_src pm_cr_tx_rx_cdr_clkin_scratch0 _src pm_cr_tx_rx_scratch1_src pm_cr_tx_rx_cdr_clkin_scratch1 _src pm_cr_tx_rx_scratch2_src pm_cr_tx_rx_cdr_clkin_scratch2 _src pm_cr_tx_rx_scratch3_src pm_cr_tx_rx_cdr_clkin_scratch3 _src pm_cr_tx_rx_scratch4_src pm_cr_tx_rx_cdr_clkin_scratch4 _src chgpmp_dn_pd_trim_double chgpmp_up_pd_trim_double pm_cr_tx_rx_scratch0_src:reference clock for top FPLL from IQCLK network pm_cr_tx_rx_cdr_clkin_scratch0_src:clkin[ input selection pm_cr_tx_rx_scratch1_src:reference clock for top FPLL from IQCLK network pm_cr_tx_rx_cdr_clkin_scratch1_src:clkin[1] input selection pm_cr_tx_rx_scratch2_src:reference clock for top FPLL from IQCLK network pm_cr_tx_rx_cdr_clkin_scratch2_src:clkin[ input selection pm_cr_tx_rx_scratch3_src:reference clock for top FPLL from IQCLK network pm_cr_tx_rx_cdr_clkin_scratch3_src:clkin[1] input selection pm_cr_tx_rx_scratch4_src:reference clock for top FPLL from IQCLK network pm_cr_tx_rx_cdr_clkin_scratch4_src:clkin[ input selection chgpmp_dn_pd_trim_double:select option to double charge pump DN PD trim current in lock to data mode chgpmp_up_pd_trim_double:select option to double charge pump UP PD trim current in lock to data mode 170 chgpmp_current_up_trim chgpmp_current_dn_trim chgpmp_current_up_trim:select different triming current in PD mode chgpmp_current_dn_trim:select different triming current in PD mode 172 set_cdr_vco_speed_pciegen3 set_cdr_vco_speed_pciegen3:adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. 175 set_cdr_vco_speed_pciegen3 set_cdr_vco_speed_pciegen3:adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. 404 RESERVED RESERVED: 405 RESERVED RESERVED: 410 RESERVED RESERVED: 480 RESERVED RESERVED: 4E0 cmu_pll_powerdown cmu_override_pll_powerdown RESERVED cmu_pll_powerdown:pll_powerdown cmu_override_pll_powerdown:override_pll_powerdown RESERVED: 540 cmu_cfg_sel S10_XR_OFFSET_EMBED_RCFG_ BCAST_EN cmu_cfg_load cmu_cfg_sel:cfg_sel S10_XR_OFFSET_EMBED_RCFG_BCAST_EN:bcast_en cmu_cfg_load:cfg_load 541 cmu_rcfg_busy cmu_rcfg_busy:rcfg_busy CMU_PLL_0 Register map Physical register with avalon address of 0 24

25 Base Address :0 Bit Name Access 0[ pcs_arbiter_ctrl[ pcs_arbiter_ctrl: AVMM1 bus Arbitration control Avalon address(es): 0.0 AVMM1_ARBITER_PLD_SEL PLD control of AVMM 1 Interface AVMM1_ARBITER_UC_SEL Microcontroller control of AVMM 1 Interface 0[1] pcs_cal_done[ pcs_cal_done: AVMM1 calibration done Avalon address(es): 0.1 AVMM1_CAL_DONE_ASSERT calibration is done AVMM1_CAL_DONE_DEASSERT calibration is not done 0[2] pcs_hip_cal_en[0 ] pcs_hip_cal_en: AVMM1 HIP Enable for Calibration Avalon address(es): 0.2 DISABLE Hip Enable ENABLE Hip Disable 0[7:3] pcs_cal_reserve d[4: pcs_cal_reserved: AVMM1 calibration reserve bits Avalon address(es): 0.7:3 Correspond to bit(s) [4: in the following configurations: DIRECT MAPPED avmm1_cal_reserved[4: CMU_PLL_100 Register map Physical register with avalon address of 100 Base Address :100 Bit Name Access 100[1] pm_cr_tx_rx_uc_ txvod_cal[ pm_cr_tx_rx_uc_txvod_cal: Avalon address(es):

26 Bit Name Access UC_TX_VOD_CAL_OFF UC_TX_VOD_CAL_ON CMU_PLL_11D Register map Physical register with avalon address of 11D Base Address :11D Bit Name Access 11D[ loopback_mode[ Part of loopback_mode: Jitter generation Avalon address(es): C.7 11D.0 3'b000 3'b010 3'b001 3'b011 3'b100 3'b101 3'b111 LOOPBACK_DISABLED LOOPACK is disabled LOOPBACK_RECOVERED_DATA Loopback the recovered data & BTI Loopback. Additional settings required in pm_cdr. Settings also disable the outputs to save power RX_REFCLK LOOPACK is disabled, RX dynamic loopback driver is enabled to driver refclk network RX_REFCLK_CDR_LOOPBACK Enable RX as refclk & BTI loopback UNUSED2 Invalid mode LOOPBACK_RECEIVED_DATA Loopback received (metallic) data UNUSED1 Invalid mode CMU_PLL_132 Register map Physical register with avalon address of 132 Base Address :132 Bit Name Access 132[ set_cdr_vco_spe ed_fix[7] Part of set_cdr_vco_speed_fix: Adjust cdr VCO speed. Default bits settings Avalon address(es): :0 Correspond to bit(s) [7] in the following configurations: 26

27 Bit Name Access DIRECT MAPPED set_cdr_vco_speed_fix[7] 132[1] cdr_powerdown_ mode[ cdr_powerdown_mode: Select powerdown state of the CDR Avalon address(es): POWER_DOWN Power down POWER_UP Power up 132[2] set_cdr_vco_spe ed_fix[6] Part of set_cdr_vco_speed_fix: Adjust cdr VCO speed. Default bits settings Avalon address(es): :0 Correspond to bit(s) [6] in the following configurations: DIRECT MAPPED set_cdr_vco_speed_fix[6] 132[3] chgpmp_vccreg[ Part of chgpmp_vccreg: Selects different level to boost CP regulator output Avalon address(es): 133.3: 'b000 3'b010 3'b100 3'b110 3'b001 3'b011 3'b101 3'b111 VREG_FW0 vcc = vreg VREG_FW1 vcc = vreg*1.012 VREG_FW2 vcc = vreg*1.024 VREG_FW3 vcc = vreg*1.036 VREG_FW4 vcc = vreg*1.048 VREG_FW5 vcc = vreg*1.06 VREG_FW6 vcc = vreg*1.072 VREG_FW7 vcc = vreg* [5: 4] reverse_serial_lo opback[1: Part of reverse_serial_loopback: Enable the reverse serial loopback path Avalon address(es): 13C :4 Correspond to bit(s) [1: in the following configurations: 3'b000 3'b100 3'b101 NO_LOOPBACK No loop back. LOOPBACK_DATA_NO_POSTTAP Loopback the data signal without Eq LOOPBACK_DATA_WITH_POSTTAP Loopback the data signal with Eq 27

28 Bit Name Access 3'b110 LOOPBACK_DATA_0_1 Loopback 0/1 signal 132[7: 6] set_cdr_vco_spe ed_pciegen3[1:0 ] Part of set_cdr_vco_speed_pciegen3: Adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. Avalon address(es): 175.7: C.6: : :6 Correspond to bit(s) [1: in the following configurations: 13'b CDR_VCO_MIN_SPEEDBIN_PCIEGEN3 CDR_VCO_MAX_SPEEDBIN_PCIEGEN3 Set cdr vco speed: Minimum speed Set cdr vco speed: Minimum speed CMU_PLL_133 Register map Physical register with avalon address of 133 Base Address :133 Bit Name Access 133[3: 2] chgpmp_vccreg[ 2:1] Part of chgpmp_vccreg: Selects different level to boost CP regulator output Avalon address(es): 133.3: Correspond to bit(s) [2:1] in the following configurations: 3'b000 3'b010 3'b100 3'b110 3'b001 3'b011 3'b101 3'b111 VREG_FW0 vcc = vreg VREG_FW1 vcc = vreg*1.012 VREG_FW2 vcc = vreg*1.024 VREG_FW3 vcc = vreg*1.036 VREG_FW4 vcc = vreg*1.048 VREG_FW5 vcc = vreg*1.06 VREG_FW6 vcc = vreg*1.072 VREG_FW7 vcc = vreg* [7: 5] chgpmp_current_ up_pd[2: chgpmp_current_up_pd: Select the charge pump UP current in lock to data mode Avalon address(es): 133.7:5 Correspond to bit(s) [2: in the following configurations: 3'b000 CP_CURRENT_PD_UP_SETTING0 Charge pump UP current setting in PD mode (0uA) 28

29 Bit Name Access 3'b001 3'b010 3'b011 3'b100 CP_CURRENT_PD_UP_SETTING1 Charge pump UP current setting in PD mode (2.5uA) CP_CURRENT_PD_UP_SETTING2 Charge pump UP current setting in PD mode (5uA) CP_CURRENT_PD_UP_SETTING3 Charge pump UP current setting in PD mode (7.5uA) CP_CURRENT_PD_UP_SETTING4 Charge pump UP current setting in PD mode (10uA) CMU_PLL_134 Register map Physical register with avalon address of 134 Base Address :134 Bit Name Access 134[6] set_cdr_vco_spe ed_fix[4] Part of set_cdr_vco_speed_fix: Adjust cdr VCO speed. Default bits settings Avalon address(es): :0 Correspond to bit(s) [4] in the following configurations: DIRECT MAPPED set_cdr_vco_speed_fix[4] CMU_PLL_135 Register map Physical register with avalon address of 135 Base Address :135 Bit Name Access 135[1: lf_resistor_pfd[1: lf_resistor_pfd: Select the loop filter resistance in lock to reclk mode Avalon address(es): 135.1:0 Correspond to bit(s) [1: in the following configurations: 2'b00 2'b01 2'b10 LF_PFD_SETTING0 Loop Filter resistor setting in PFD mode LF_PFD_SETTING1 Loop Filter resistor setting in PFD mode LF_PFD_SETTING2 Loop Filter resistor setting in PFD mode 29

30 Bit Name Access 2'b11 LF_PFD_SETTING3 Loop Filter resistor setting in PFD mode 135[3: 2] lf_resistor_pd[1: lf_resistor_pd: Select the loop filter resistance in lock to data mode Avalon address(es): 135.3:2 Correspond to bit(s) [1: in the following configurations: 2'b00 2'b01 2'b10 2'b11 LF_PD_SETTING0 Loop Filter resistor setting in PD mode LF_PD_SETTING1 Loop Filter resistor setting in PD mode LF_PD_SETTING2 Loop Filter resistor setting in PD mode LF_PD_SETTING3 Loop Filter resistor setting in PD mode 135[4] lf_ripple_cap[ lf_ripple_cap: Select the loop filter ripple cap size Avalon address(es): LF_NO_RIPPLE Loop filter ripple cap disabled LF_RIPPLE_CAP1 Loop filter ripple cap enabled 135[5] chgpmp_current_ up_trim[ Part of chgpmp_current_up_trim: Select different triming current in PD mode Avalon address(es): 170.3: 'b0000 4'b0010 4'b0100 4'b0110 4'b1000 4'b1010 4'b1100 4'b1110 4'b0001 CP_CURRENT_TRIMMING_UP_SETTING0 Select UP trimming current (0uA) CP_CURRENT_TRIMMING_UP_SETTING1 Select UP trimming current (0.21uA) CP_CURRENT_TRIMMING_UP_SETTING2 Select UP trimming current (0.42uA) CP_CURRENT_TRIMMING_UP_SETTING3 Select UP trimming current (0.62uA) CP_CURRENT_TRIMMING_UP_SETTING4 Select UP trimming current (0.83uA) CP_CURRENT_TRIMMING_UP_SETTING5 Select UP trimming current (1.04uA) CP_CURRENT_TRIMMING_UP_SETTING6 Select UP trimming current (1.25uA) CP_CURRENT_TRIMMING_UP_SETTING7 Select UP trimming current (1.46uA) CP_CURRENT_TRIMMING_UP_SETTING8 Select UP trimming current (1.67uA) 30

31 Bit Name Access 4'b0011 4'b0101 4'b0111 4'b1001 4'b1011 4'b1101 4'b1111 CP_CURRENT_TRIMMING_UP_SETTING9 Select UP trimming current (1.87uA) CP_CURRENT_TRIMMING_UP_SETTING10 Select UP trimming current (2.08uA) CP_CURRENT_TRIMMING_UP_SETTING11 Select UP trimming current (2.29uA) CP_CURRENT_TRIMMING_UP_SETTING12 Select UP trimming current (2.50uA) CP_CURRENT_TRIMMING_UP_SETTING13 Select UP trimming current (2.71uA) CP_CURRENT_TRIMMING_UP_SETTING14 Select UP trimming current (2.92uA) CP_CURRENT_TRIMMING_UP_SETTING15 Select UP trimming current (3.12uA) 135[6] set_cdr_vco_spe ed_fix[5] Part of set_cdr_vco_speed_fix: Adjust cdr VCO speed. Default bits settings Avalon address(es): :0 Correspond to bit(s) [5] in the following configurations: DIRECT MAPPED set_cdr_vco_speed_fix[5] CMU_PLL_136 Register map Physical register with avalon address of 136 Base Address :136 Bit Name Access 136[3: set_cdr_vco_spe ed_fix[3: Part of set_cdr_vco_speed_fix: Adjust cdr VCO speed. Default bits settings Avalon address(es): :0 Correspond to bit(s) [3: in the following configurations: DIRECT MAPPED set_cdr_vco_speed_fix[3: 136[5: 4] vco_overrange_v oltage[1: vco_overrange_voltage: Select the VCO overrange detector trip point Avalon address(es): 136.5:4 Correspond to bit(s) [1: in the following configurations: 2'b00 VCO_OVERRANGE_OFF VCO overrange is off 2'b01 VCO_OVERRANGE_REF_1 VCO overrange REF voltage is 1.7V 31

32 Bit Name Access 2'b10 VCO_OVERRANGE_REF_2 VCO overrange REF voltage is 1.8V 2'b11 VCO_OVERRANGE_REF_3 VCO overrange REF voltage is 1.9V 136[7: 6] vco_underrange_ voltage[1: vco_underrange_voltage: Select the VCO underrange detector trip point Avalon address(es): 136.7:6 Correspond to bit(s) [1: in the following configurations: 2'b00 VCO_UNDERANGE_OFF VCO underrange is off 2'b01 VCO_UNDERANGE_REF_1 VCO underrange REF voltage is 1.7V 2'b10 VCO_UNDERANGE_REF_2 VCO underrange REF voltage is 1.8V 2'b11 VCO_UNDERANGE_REF_3 VCO underrange REF voltage is 1.9V CMU_PLL_137 Register map Physical register with avalon address of 137 Base Address :137 Bit Name Access 137[6: 2] set_cdr_vco_spe ed[4: set_cdr_vco_speed: Adjust cdr VCO speed. Default bits settings Avalon address(es): 137.6:2 Correspond to bit(s) [4: in the following configurations: DIRECT MAPPED set_cdr_vco_speed[4: 137[7] diag_loopback_e nable[ diag_loopback_enable: Enable/disable the diagnostic loopback Avalon address(es): NO_DIAG_REV_LOOPBACK No diagnostic reverse serial loop back. DIAG_REV_LOOPBACK Use in conjunction with cr_rlbk and rrevlb_sw loopback control signals CMU_PLL_138 Register map Physical register with avalon address of 138 Base Address :138 32

33 Bit Name Access 138[4: set_cdr_vco_spe ed_pciegen3[6:2 ] Part of set_cdr_vco_speed_pciegen3: Adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. Avalon address(es): 175.7: C.6: : :6 Correspond to bit(s) [6:2] in the following configurations: 13'b CDR_VCO_MIN_SPEEDBIN_PCIEGEN3 CDR_VCO_MAX_SPEEDBIN_PCIEGEN3 Set cdr vco speed: Minimum speed Set cdr vco speed: Minimum speed CMU_PLL_139 Register map Physical register with avalon address of 139 Base Address :139 Bit Name Access 139[2: chgpmp_current_ pfd[2: chgpmp_current_pfd: Select the charge pump current in lock to refclk mode Avalon address(es): 139.2:0 Correspond to bit(s) [2: in the following configurations: 3'b000 3'b001 3'b010 3'b011 3'b100 CP_CURRENT_PFD_SETTING0 Charge pump current setting in PFD mode CP_CURRENT_PFD_SETTING1 Charge pump current setting in PFD mode CP_CURRENT_PFD_SETTING2 Charge pump current setting in PFD mode CP_CURRENT_PFD_SETTING3 Charge pump current setting in PFD mode CP_CURRENT_PFD_SETTING4 Charge pump current setting in PFD mode 139[5: 3] chgpmp_current_ dn_pd[2: chgpmp_current_dn_pd: Select the charge pump DOWN current in lock to data mode Avalon address(es): 139.5:3 Correspond to bit(s) [2: in the following configurations: 3'b000 3'b001 CP_CURRENT_PD_DN_SETTING0 Charge pump DN current setting in PD mode (0uA) CP_CURRENT_PD_DN_SETTING1 Charge pump DN current setting in PD mode (2.5uA) 33

34 Bit Name Access 3'b010 3'b011 3'b100 CP_CURRENT_PD_DN_SETTING2 Charge pump DN current setting in PD mode (5uA) CP_CURRENT_PD_DN_SETTING3 Charge pump DN current setting in PD mode (7.5uA) CP_CURRENT_PD_DN_SETTING4 Charge pump DN current setting in PD mode (10uA) 139[6] chgpmp_replicat e[ chgpmp_replicate: Enable/disable the replica bias circuit in the charge pump Avalon address(es): DISABLE_REPLICA_BIAS_CTRL disable replica bias control ENABLE_REPLICA_BIAS_CTRL enable replica bias control 139[7] pd_fastlock_mod e[ pd_fastlock_mode: Enable/disable fast locking in PD mode Avalon address(es): FAST_LOCK_DISABLE Disable fast lock mode. FAST_LOCK_ENABLE Enable fast lock mode CMU_PLL_13A Register map Physical register with avalon address of 13A Base Address :13A Bit Name Access 13A[2: pfd_l_counter[2: pfd_l_counter: L counter divide value when the CDR is in lock to reference mode Avalon address(es): 13A.2:0 Correspond to bit(s) [2: in the following configurations: 3'b000 3'b001 3'b010 3'b011 3'b100 0 PFD L counter disabled for lock to refclk 100 PFD L counter refclk test input 1 PFD L counter in divide by 1 mode for lock to refclk 2 PFD L counter in divide by 2 mode for lock to refclk 4 PFD L counter in divide by 4 mode for lock to refclk 34

35 Bit Name Access 3'b101 3'b110 8 PFD L counter in divide by 8 mode for lock to refclk 16 PFD L counter in divide by 16 mode for lock to refclk 13A[5: 3] pd_l_counter[2:0 ] pd_l_counter: Select the L Counter divider value when the CDR is in PD mode Avalon address(es): 13A.5:3 Correspond to bit(s) [2: in the following configurations: 3'b000 3'b001 3'b011 3'b100 3'b101 3'b110 0 Disable PD L counter when in CMU mode 1 PD L counter in divide by 1 mode for lock to data 2 PD L counter in divide by 2 mode for lock to data 4 PD L counter in divide by 4 mode for lock to data 8 PD L counter in divide by 8 mode for lock to data 16 PD L counter in divide by 16 mode for lock to data CMU_PLL_13B Register map Physical register with avalon address of 13B Base Address :13B Bit Name Access 13B[7: mcnt_div[7: mcnt_div: Select the M feedback counter division value Avalon address(es): 13B.7:0 Correspond to bit(s) [7: in the following configurations: DIRECT MAPPED mcnt_div[7: CMU_PLL_13C Register map Physical register with avalon address of 13C Base Address :13C Bit Name Access 13C[3: 2] ncnt_div[1: ncnt_div: Select the N refclk counter division value Avalon address(es): 13C.3:2 Correspond to bit(s) [1: in the following configurations: 35

36 Bit Name Access 2'b00 1 bypass ncnt 2'b01 2 ncnt /2 2'b10 4 ncnt /4 2'b11 8 ncnt /8 13C[6: 4] set_cdr_vco_spe ed_pciegen3[9:7 ] Part of set_cdr_vco_speed_pciegen3: Adjust cdr VCO speed. Settings only used when PCIE_SW selects PCIE Gen3 mode. Avalon address(es): 175.7: C.6: : :6 Correspond to bit(s) [9:7] in the following configurations: 13'b CDR_VCO_MIN_SPEEDBIN_PCIEGEN3 CDR_VCO_MAX_SPEEDBIN_PCIEGEN3 Set cdr vco speed: Minimum speed Set cdr vco speed: Minimum speed 13C[7] reverse_serial_lo opback[2] Part of reverse_serial_loopback: Enable the reverse serial loopback path Avalon address(es): 13C :4 Correspond to bit(s) [2] in the following configurations: 3'b000 3'b100 3'b101 3'b110 NO_LOOPBACK No loop back. LOOPBACK_DATA_NO_POSTTAP Loopback the data signal without Eq LOOPBACK_DATA_WITH_POSTTAP Loopback the data signal with Eq LOOPBACK_DATA_0_1 Loopback 0/1 signal 13C[7] loopback_mode[ 1] Part of loopback_mode: Jitter generation Avalon address(es): C.7 11D.0 Correspond to bit(s) [1] in the following configurations: 3'b000 3'b010 3'b001 3'b011 3'b100 3'b101 3'b111 LOOPBACK_DISABLED LOOPACK is disabled LOOPBACK_RECOVERED_DATA Loopback the recovered data & BTI Loopback. Additional settings required in pm_cdr. Settings also disable the outputs to save power RX_REFCLK LOOPACK is disabled, RX dynamic loopback driver is enabled to driver refclk network RX_REFCLK_CDR_LOOPBACK Enable RX as refclk & BTI loopback UNUSED2 Invalid mode LOOPBACK_RECEIVED_DATA Loopback received (metallic) data UNUSED1 Invalid mode 36