Verilog Lecţia 1. Primitive porţi. Primitive porţi de transmisie. Sintaxa generală de instanţiere a porţilor:
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1 Verilog Lecţia 1 Primitive porţi Sintaxa generală de instanţiere a porţilor: <tip_poarta> [nume_instanta] (iesire, intrare1, intrare2,...); tip_poarta ::= and nand or nor xor xnor Poartă Descriere Sintaxă and Poartă ŞI cu N intrări and U0(out,in1,in2,in3,in4); nand Poartă ŞI-NU (ŞI negat) cu N intrări nand U1(out,in1,in2); or Poartă SAU cu N intrări or U2(out,in1,in2,in3); nor Poartă SAU-NU (SAU negat) cu N intrări nor U3(out,in1,in2,in3,in4,in5); xor Poartă SAU EXCLUSIV cu N intrări xor U4(out,in1,in2); xnor Poartă SAU-NU EXCLUSIV (SAU EXCLUSIV negat) cu N intrări xnor U5(out,in1,in2,in3); Primitive porţi de transmisie - Pagina 1 din 6 -
2 Sintaxa generală de instanţiere a porţilor de transmisie: porţi de transmisie cu ieşire multiplă (N ieşiri) not buf [nume_instanta] (iesire1, iesire2,..., intrare); porţi de transmisie cu ieşiri în trei stări (tri-state) <tip_poarta> [nume_instanta] (iesire, intrare, control); tip_poarta ::= bufif0 bufif1 notif0 notif1 Poartă Descriere Sintaxă not Inversor cu N ieşiri not U0(out,in); buf Repetor (tampon) cu N ieşiri buf U1(out,in); bufif0 Repetor cu trei stări (tri-state), activ pe Low EN bufif0 U2(out,in,EN_low); bufif1 Repetor cu trei stări (tri-state), activ pe High EN bufif1 U3(out,in,EN_high); notif0 Inversor cu trei stări (tri-state), activ pe Low EN notif0 U4(out,in,EN_low); notif1 Inversor cu trei stări (tri-state), activ pe High EN notif1 U5(out,in,EN_high); Primitive comutatoare Poartă Descriere 1. pmos Comutator PMOS uni-direcţional 1. rpmos Comutator PMOS rezistiv pmos Mp0(out_drain, in_source, EN_low_gate); rpmos Mp1(out_drain, in_source, EN_low_gate); - Pagina 2 din 6 -
3 2. nmos Comutator NMOS uni-direcţional 2. rnmos Comutator NMOS rezistiv 3. cmos Comutator CMOS uni-direcţional 3. rcmos Comutator PMOS rezistiv nmos Mn0(out_drain, in_source, EN_high_gate); rnmos Mn1(out_drain, in_source, EN_high_gate); cmos Mnp0(out_drain, in_source, EN_high_gate, EN_low_gate); rcmos Mnp1(out_drain, in_source, EN_high_gate, EN_low_gate) ; 4. tranif1 Comutator bi-direcţional (activ High) tranif1 Mn2(portA, portb, EN_high); 4. tranif0 Comutator bi-direcţional (activ Low) tranif0 Mp2(portA, portb, EN_low); 5. rtranif1 Comutator bi-direcţional rezistiv (activ High) rtranif1 Mn3(portA, portb, EN_high); 5. rtranif0 Comutator bi-direcţional rezistiv (activ Low) rtranif0 Mp3(portA, portb, EN_low); 6. tran Comutator bi-direcţional activat (folosit pentru interfaţare) tran Conn0(portA, portb); 6. rtran Comutator bi-direcţional rezistiv activat (folosit pentru interfaţare) rtran Conn1(portA, portb); 7. pullup Rezistor pull up pullup R0(toVdd); 8. pulldown Rezistor pull down pulldown R1(toGnd); Inversorul CMOS // Descrierea la nivel de comutator a unui inversor CMOS module inv_sw (out, in); output out; // ieşirea inversorului input in; // intrarea inversorului - Pagina 3 din 6 -
4 supply1 power; supply0 ground; pmos m1(out, power, in); nmos m0(out, ground, in); // "power" conectat la Vdd // "ground" conectat la Gnd // se instanţiază un comutator unidirecţional pmos // se instanţiază un comutator unidirecţional nmos endmodule Multiplexor pe 1-bit 2-1 This circuit assigns the output out to either inputs in1 or in2 depending on the low or high values of ctrl respectively. // Descrierea la nivel de comutator a unui multiplexor cu două intrări // ctrl=0, out=in1; ctrl=1, out=in2 module mux21_sw (out, ctrl, in1, in2); output out; // ieşirea mux-ului input ctrl, in1, in2; // intrările mux-ului wire w; // fir intern inv_sw I1 (w, ctrl); cmos C1 (out, in1, w, ctrl); cmos C2 (out, in2, ctrl, w); // se instanţiază blocul inversor // se instanţiază comutatoarele unidir. cmos endmodule - Pagina 4 din 6 -
5 Sumator pe un bit cu ieşire de transport //1-bit Full Adder Switch Level Model //(NOTE:inverted outputs for faster carry chain) //Nathan Kohagen //University of Washington, EE477 Spring 2004 module fa(a,b,ci,cobar,sbar); input a, b, ci; output cobar,sbar; supply1 pwr; supply0 gnd; //pmos(drain,source,gate) //nmos(drain,source,gate) pmos m0(node2,pwr,a); pmos m1(node2,pwr,b); pmos m2(cobar,node2,ci); nmos m3(cobar,node3,ci); nmos m4(node3,gnd,a); - Pagina 5 din 6 -
6 nmos m5(node3,gnd,b); pmos m6(node4,pwr,b); pmos m7(cobar,node4,a); nmos m8(cobar,node5,a); nmos m9(node5,gnd,b); pmos m10(node6,pwr,a); pmos m11(node6,pwr,b); pmos m12(node6,pwr,ci); pmos m13(sbar,node6,cobar); nmos m14(sbar,node7,cobar); nmos m15(node7,gnd,a); nmos m16(node7,gnd,b); nmos m17(node7,gnd,ci); pmos m18(node8,pwr,a); pmos m19(node9,node8,b); pmos m20(sbar,node9,ci); nmos m21(sbar,node10,ci); nmos m22(node10,node11,a); nmos m23(node11,gnd,b); endmodule - Pagina 6 din 6 -
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