Verilog Lecţia 1. Primitive porţi. Primitive porţi de transmisie. Sintaxa generală de instanţiere a porţilor:

Size: px
Start display at page:

Download "Verilog Lecţia 1. Primitive porţi. Primitive porţi de transmisie. Sintaxa generală de instanţiere a porţilor:"

Transcription

1 Verilog Lecţia 1 Primitive porţi Sintaxa generală de instanţiere a porţilor: <tip_poarta> [nume_instanta] (iesire, intrare1, intrare2,...); tip_poarta ::= and nand or nor xor xnor Poartă Descriere Sintaxă and Poartă ŞI cu N intrări and U0(out,in1,in2,in3,in4); nand Poartă ŞI-NU (ŞI negat) cu N intrări nand U1(out,in1,in2); or Poartă SAU cu N intrări or U2(out,in1,in2,in3); nor Poartă SAU-NU (SAU negat) cu N intrări nor U3(out,in1,in2,in3,in4,in5); xor Poartă SAU EXCLUSIV cu N intrări xor U4(out,in1,in2); xnor Poartă SAU-NU EXCLUSIV (SAU EXCLUSIV negat) cu N intrări xnor U5(out,in1,in2,in3); Primitive porţi de transmisie - Pagina 1 din 6 -

2 Sintaxa generală de instanţiere a porţilor de transmisie: porţi de transmisie cu ieşire multiplă (N ieşiri) not buf [nume_instanta] (iesire1, iesire2,..., intrare); porţi de transmisie cu ieşiri în trei stări (tri-state) <tip_poarta> [nume_instanta] (iesire, intrare, control); tip_poarta ::= bufif0 bufif1 notif0 notif1 Poartă Descriere Sintaxă not Inversor cu N ieşiri not U0(out,in); buf Repetor (tampon) cu N ieşiri buf U1(out,in); bufif0 Repetor cu trei stări (tri-state), activ pe Low EN bufif0 U2(out,in,EN_low); bufif1 Repetor cu trei stări (tri-state), activ pe High EN bufif1 U3(out,in,EN_high); notif0 Inversor cu trei stări (tri-state), activ pe Low EN notif0 U4(out,in,EN_low); notif1 Inversor cu trei stări (tri-state), activ pe High EN notif1 U5(out,in,EN_high); Primitive comutatoare Poartă Descriere 1. pmos Comutator PMOS uni-direcţional 1. rpmos Comutator PMOS rezistiv pmos Mp0(out_drain, in_source, EN_low_gate); rpmos Mp1(out_drain, in_source, EN_low_gate); - Pagina 2 din 6 -

3 2. nmos Comutator NMOS uni-direcţional 2. rnmos Comutator NMOS rezistiv 3. cmos Comutator CMOS uni-direcţional 3. rcmos Comutator PMOS rezistiv nmos Mn0(out_drain, in_source, EN_high_gate); rnmos Mn1(out_drain, in_source, EN_high_gate); cmos Mnp0(out_drain, in_source, EN_high_gate, EN_low_gate); rcmos Mnp1(out_drain, in_source, EN_high_gate, EN_low_gate) ; 4. tranif1 Comutator bi-direcţional (activ High) tranif1 Mn2(portA, portb, EN_high); 4. tranif0 Comutator bi-direcţional (activ Low) tranif0 Mp2(portA, portb, EN_low); 5. rtranif1 Comutator bi-direcţional rezistiv (activ High) rtranif1 Mn3(portA, portb, EN_high); 5. rtranif0 Comutator bi-direcţional rezistiv (activ Low) rtranif0 Mp3(portA, portb, EN_low); 6. tran Comutator bi-direcţional activat (folosit pentru interfaţare) tran Conn0(portA, portb); 6. rtran Comutator bi-direcţional rezistiv activat (folosit pentru interfaţare) rtran Conn1(portA, portb); 7. pullup Rezistor pull up pullup R0(toVdd); 8. pulldown Rezistor pull down pulldown R1(toGnd); Inversorul CMOS // Descrierea la nivel de comutator a unui inversor CMOS module inv_sw (out, in); output out; // ieşirea inversorului input in; // intrarea inversorului - Pagina 3 din 6 -

4 supply1 power; supply0 ground; pmos m1(out, power, in); nmos m0(out, ground, in); // "power" conectat la Vdd // "ground" conectat la Gnd // se instanţiază un comutator unidirecţional pmos // se instanţiază un comutator unidirecţional nmos endmodule Multiplexor pe 1-bit 2-1 This circuit assigns the output out to either inputs in1 or in2 depending on the low or high values of ctrl respectively. // Descrierea la nivel de comutator a unui multiplexor cu două intrări // ctrl=0, out=in1; ctrl=1, out=in2 module mux21_sw (out, ctrl, in1, in2); output out; // ieşirea mux-ului input ctrl, in1, in2; // intrările mux-ului wire w; // fir intern inv_sw I1 (w, ctrl); cmos C1 (out, in1, w, ctrl); cmos C2 (out, in2, ctrl, w); // se instanţiază blocul inversor // se instanţiază comutatoarele unidir. cmos endmodule - Pagina 4 din 6 -

5 Sumator pe un bit cu ieşire de transport //1-bit Full Adder Switch Level Model //(NOTE:inverted outputs for faster carry chain) //Nathan Kohagen //University of Washington, EE477 Spring 2004 module fa(a,b,ci,cobar,sbar); input a, b, ci; output cobar,sbar; supply1 pwr; supply0 gnd; //pmos(drain,source,gate) //nmos(drain,source,gate) pmos m0(node2,pwr,a); pmos m1(node2,pwr,b); pmos m2(cobar,node2,ci); nmos m3(cobar,node3,ci); nmos m4(node3,gnd,a); - Pagina 5 din 6 -

6 nmos m5(node3,gnd,b); pmos m6(node4,pwr,b); pmos m7(cobar,node4,a); nmos m8(cobar,node5,a); nmos m9(node5,gnd,b); pmos m10(node6,pwr,a); pmos m11(node6,pwr,b); pmos m12(node6,pwr,ci); pmos m13(sbar,node6,cobar); nmos m14(sbar,node7,cobar); nmos m15(node7,gnd,a); nmos m16(node7,gnd,b); nmos m17(node7,gnd,ci); pmos m18(node8,pwr,a); pmos m19(node9,node8,b); pmos m20(sbar,node9,ci); nmos m21(sbar,node10,ci); nmos m22(node10,node11,a); nmos m23(node11,gnd,b); endmodule - Pagina 6 din 6 -

Verilog Tutorial (Structure, Test)

Verilog Tutorial (Structure, Test) Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology Module START Example)

More information

Introduction to Verilog design. Design flow (from the book) Hierarchical Design. Lecture 2

Introduction to Verilog design. Design flow (from the book) Hierarchical Design. Lecture 2 Introduction to Verilog design Lecture 2 ECE 156A 1 Design flow (from the book) ECE 156A 2 Hierarchical Design Chip Modules Cells Primitives A chip contain many modules A module may contain other modules

More information

Verilog. Like VHDL, Verilog HDL is like a programming language but:

Verilog. Like VHDL, Verilog HDL is like a programming language but: Verilog Verilog Like VHDL, Verilog HDL is like a programming language but: Statements can execute simultaneously unlike programming e.g. nand(y1,a1,b1); nand(y2,a2,b2); or (out,y1,y2); a1 b1 all statements

More information

Introduction to Verilog design. Design flow (from the book)

Introduction to Verilog design. Design flow (from the book) Introduction to Verilog design Lecture 2 ECE 156A 1 Design flow (from the book) ECE 156A 2 1 Hierarchical Design Chip Modules Cells Primitives A chip contain many modules A module may contain other modules

More information

Introduction to Digital Design with Verilog HDL

Introduction to Digital Design with Verilog HDL Introduction to Digital Design with Verilog HDL Modeling Styles 1 Levels of Abstraction n Behavioral The highest level of abstraction provided by Verilog HDL. A module is implemented in terms of the desired

More information

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL

More information

Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi

Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1 Venue Computer Lab: Tuesdays 10 12 am (Fixed) Computer Lab: Wednesday 10-12 am (Every other odd weeks) Note: Due to some unpredicted problems with

More information

Online Verilog Resources

Online Verilog Resources EECS 427 Discussion 6: Verilog HDL Reading: Many references EECS 427 F08 Discussion 6 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf it/ pratolo/verilog/verilogtutorial

More information

VERILOG QUICKSTART. Second Edition. A Practical Guide to Simulation and Synthesis in Verilog

VERILOG QUICKSTART. Second Edition. A Practical Guide to Simulation and Synthesis in Verilog VERILOG QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Second Edition VERILOG QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Second Edition James M. Lee SEVA Technologies

More information

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1 EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references EECS 427 W07 Lecture 14 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf

More information

OVERVIEW: ============================================================ REPLACE

OVERVIEW: ============================================================ REPLACE OVERVIEW: With mantis 928, formal arguments to properties and sequences are defined to apply to a list of arguments that follow, much like tasks and function arguments. Previously, the type had to be replicated

More information

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: RTL Coding in Verilog CSE241 R1 Verilog.1 Kahng & Cichy, UCSD 2003 Topic Outline Introduction Verilog Background Connections Modules Procedures Structural

More information

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date: Synthesizable Coding of Verilog Lecturer: Date: 2009.03.18 ACCESS IC LAB Outline Basic concepts of logic synthesis Synthesizable Verilog coding subset Verilog coding practices Coding for readability Coding

More information

Brief Introduction of Cell-based Design. Ching-Da Chan CIC/DSD

Brief Introduction of Cell-based Design. Ching-Da Chan CIC/DSD Brief Introduction of Cell-based Design Ching-Da Chan CIC/DSD 1 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D 2 Full Custom V.S Cell based Design Full custom design Better patent

More information

Programmable Logic Devices Verilog VII CMPE 415

Programmable Logic Devices Verilog VII CMPE 415 Synthesis of Combinational Logic In theory, synthesis tools automatically create an optimal gate-level realization of a design from a high level HDL description. In reality, the results depend on the skill

More information

Gate level or structural modeling

Gate level or structural modeling Gate level or structural modeling Prerequisites Functioning of basic logic gates and basic understanding of Verilog coding is required. You are suggested to complete the previous unit before starting this

More information

UNIT V: SPECIFICATION USING VERILOG HDL

UNIT V: SPECIFICATION USING VERILOG HDL UNIT V: SPECIFICATION USING VERILOG HDL PART -A (2 Marks) 1. What are identifiers? Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists

More information

Appendix A GATE-LEVEL DETAILS

Appendix A GATE-LEVEL DETAILS Appendix A GATE-LEVEL DETAILS Chapters 2 and 3 1:riefly introduced the built-in primitives. This appendix will 1:riefly describe each of the built-in primitives and the options when instantiating them.

More information

VERILOG QUICKSTART. James M. Lee Cadence Design Systems, Inc. SPRINGER SCIENCE+BUSINESS MEDIA, LLC

VERILOG QUICKSTART. James M. Lee Cadence Design Systems, Inc. SPRINGER SCIENCE+BUSINESS MEDIA, LLC VERILOG QUICKSTART VERILOG QUICKSTART by James M. Lee Cadence Design Systems, Inc. ~. " SPRINGER SCIENCE+BUSINESS MEDIA, LLC ISBN 978-1-4613-7801-3 ISBN 978-1-4615-6113-2 (ebook) DOI 10.1007/978-1-4615-6113-2

More information

Graduate Institute of Electronics Engineering, NTU Basic Concept of HDL

Graduate Institute of Electronics Engineering, NTU Basic Concept of HDL Basic Concept of HDL Lecturer: ( ) Date: 2004.03.05 ACCESS IC LAB Outline Hierarchical Design Methodology Basic Concept of Verilog HDL Switch Level Modeling Gate Level Modeling Simulation & Verification

More information

Chapter 2a: Structural Modeling

Chapter 2a: Structural Modeling Chapter 2a: Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs

More information

RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM. SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8)

RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM. SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8) RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8) HDL-BASED SYNTHESIS Modern ASIC design use HDL together with synthesis tool to create

More information

Passive Device Verilog Models For Board And System-Level Digital Simulation

Passive Device Verilog Models For Board And System-Level Digital Simulation And System-Level Digital Simulation Clifford E. Cummings Sunburst Design, Inc. cliffc@sunburst-design.com Anthony M. Nady II anthony.m.nady@whiz.to ABSTRACT Board and system-level simulations require a

More information

Verilog Tutorial By. Deepak Kumar Tala. world.com

Verilog Tutorial By. Deepak Kumar Tala.   world.com Verilog Tutorial By Deepak Kumar Tala http://www.asic world.com Sep 12 2005 1 DISCLAIMER I don't makes any claims, promises or guarantees about the accuracy, completeness, or adequacy of the contents of

More information

Verilog-A/MS is a case sensitive language. Spaces, tabs, and newlines are considered white space and are ignored except when found in strings.

Verilog-A/MS is a case sensitive language. Spaces, tabs, and newlines are considered white space and are ignored except when found in strings. 5 Language Reference 1 Basics Verilog-A/MS is a case sensitive language. Spaces, tabs, and newlines are considered white space and are ignored except when found in strings. 1.1 Comments Comments are text

More information

Verilog HDL Introduction

Verilog HDL Introduction EEE3050 Theory on Computer Architectures (Spring 2017) Prof. Jinkyu Jeong Verilog HDL Introduction 2017.05.14 TA 이규선 (GYUSUN LEE) / 안민우 (MINWOO AHN) Modules The Module Concept Basic design unit Modules

More information

430 Index. D flip-flop, from nands, 189, 191, 192 D flip-flop, verilog, 37

430 Index. D flip-flop, from nands, 189, 191, 192 D flip-flop, verilog, 37 Index *, in event control, 46 -> (event trigger), 177 $display, 34, 146, 165 $display, example, 44 $finish, 11, 165, 195, 196 $fullskew timing check, 297 $hold timing check, 298 $monitor, 34, 174 $nochange

More information

Verilog / SystemVerilog

Verilog / SystemVerilog Verilog / SystemVerilog History & main concepts structure, description styles, data types Procedural & assignment; if-then, case & loop statements Functional hierarchy tasks & functions Time & events;

More information

VERILOG QUICKSTART. A Practical Guide to Simulation and Synthesis in Verilog. Third Edition

VERILOG QUICKSTART. A Practical Guide to Simulation and Synthesis in Verilog. Third Edition VERILOG QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Third Edition THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VERILOG QUICKSTART A Practical Guide to Simulation

More information

Chapter 4: Introduction to Logic Design with Verilog. Chapter 4 Copyright 2013 G. Tumbush v1.3

Chapter 4: Introduction to Logic Design with Verilog. Chapter 4 Copyright 2013 G. Tumbush v1.3 Chapter 4: Introduction to Logic Design with Verilog 1 Hardware Description Language Verilog Background Verilog created at Gateway Design Automation in 1983/1984 Cadence Design Systems purchased Gateway

More information

Modeling Concepts. Introduction

Modeling Concepts. Introduction Introduction Verilog HDL modeling language supports three kinds of modeling styles: gate-level, dataflow, and behavioral. The gate-level and datafow modeling are used to model combinatorial circuits whereas

More information

SYSTEM SPECIFICATIONS USING VERILOG HDL. Dr. Mohammed M. Farag

SYSTEM SPECIFICATIONS USING VERILOG HDL. Dr. Mohammed M. Farag SYSTEM SPECIFICATIONS USING VERILOG HDL Dr. Mohammed M. Farag Outline Introduction Basic Concepts Modules and Ports Gate-Level Modeling Dataflow Modeling Behavioral Modeling Tasks and Functions Textbook:

More information

Why Should I Learn This Language? VLSI HDL. Verilog-2

Why Should I Learn This Language? VLSI HDL. Verilog-2 Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate

More information

REF: Reuse Methodology Manual For System-ON-A-Chip Design, Third Edition 2002 CIC Training Manual Logic Synthesis with Design Compiler, July, 2007

REF: Reuse Methodology Manual For System-ON-A-Chip Design, Third Edition 2002 CIC Training Manual Logic Synthesis with Design Compiler, July, 2007 Verilog Coding Style REF: Reuse Methodology Manual For System-ON-A-Chip Design, Third Edition 2002 CIC Training Manual Logic Synthesis with Design Compiler, July, 2007 Hsing-Chen, Lu, ARES Lab 2008 Summer

More information

Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation

Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

C13. INTERFATA PARALELA PROGRAMABILA (PPI) I8255A (PIO)

C13. INTERFATA PARALELA PROGRAMABILA (PPI) I8255A (PIO) C13. INTERFATA PARALELA PROGRAMABILA (PPI) I8255A (PIO) 1.Descriere PIO 2. Arhitectura PIO 3. Programare PIO 4. PIO in PC 5. Aplicatii http://www.advancedmsinc.com/iocards/8255.htm http://www.eisti.fr/~ga/phy/iitr/ii05/tr.pdf

More information

MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY (Affliated to Osmania University) Banjara Hills, Hyderabad, Telangana

MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY (Affliated to Osmania University) Banjara Hills, Hyderabad, Telangana MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY (Affliated to Osmania University) Banjara Hills, Hyderabad, Telangana DEPARTMENT OF INFORMATION TECHNOLOGY TABLE OF CONTENTS S.No. Content Page No. 1.

More information

Lecturer: Chihhao Chao ( 趙之昊 ) Date:

Lecturer: Chihhao Chao ( 趙之昊 ) Date: Basic Concept of Hardware Description Language Lecturer: ( 趙之昊 ) Date: 2009.02.25 The lecture note is based on Ch.4 of the textbook Review: Logic Design and Ch.2~Ch.3 of the textbook ACCESS IC LAB Overview

More information

The Verilog Golden Reference Guide

The Verilog Golden Reference Guide The Verilog Golden Reference Guide DOULOS Version 1.0, August 1996 Copyright 1996, Doulos, All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted,

More information

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93 Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure

More information

SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road QUESTION BANK UNIT I

SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road QUESTION BANK UNIT I SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK Subject with Code : DICD (16EC5703) Year & Sem: I-M.Tech & I-Sem Course

More information

Actel HDL Coding. Style Guide

Actel HDL Coding. Style Guide Actel HDL Coding Style Guide Actel Corporation, Mountain View, CA 94043 2003 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029105-6/05.04 Release: May 2004

More information

Verilog Hardware Description Language (Verilog HDL)

Verilog Hardware Description Language (Verilog HDL) 1 1 Verilog Hardware Description Language () /http://ece.niu.edu.tw/~chu )2007/2/26( 2 Brief history of 1985: Verilog language and related simulator Verilog-XL were developed by Gateway Automation. 1989:

More information

Verilog HDL. In-Cheol Park Dept. of EE, KAIST

Verilog HDL. In-Cheol Park Dept. of EE, KAIST Verilog HDL In-Cheol Park Dept. of EE, KAIST Introduction to Verilog HDL Designed as a proprietary verification/simulation tool in 1983/1984 IEEE standard 1364 in 1995 Similar to C language 4 value logic

More information

Index. B Back-annotation, 507 SDF, 508

Index. B Back-annotation, 507 SDF, 508 $display, 57, 206 example, 69, 225 $fatal, SystemVerilog, 538 $finish, 206, 245 $fullskew timing check, 366 $hold timing check, 366 $info, SystemVerilog, 538 $monitor, 217 $monitor, 57 $nochange timing

More information

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 99-1 Under-Graduate Project Verilog Simulation & Debugging Tools Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 ACCESS IC LAB Outline Basic Concept of Verilog HDL Gate Level Modeling

More information

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language 1 / 15 2014/11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware

More information

ECEN 468 Advanced Logic Design

ECEN 468 Advanced Logic Design ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26 Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean

More information

Verilog HDL. In-Cheol Park Dept. of EE, KAIST

Verilog HDL. In-Cheol Park Dept. of EE, KAIST Verilog HDL In-Cheol Park Dept. of EE, KAIST Introduction to Verilog HDL Designed as a proprietary verification/simulation tool in 1983/1984 IEEE standard 1364 in 1995 Similar to C language 4 value logic

More information

Combinational Circuits

Combinational Circuits Combinational Circuits Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted

More information

Arithmetic Operators There are two types of operators: binary and unary Binary operators:

Arithmetic Operators There are two types of operators: binary and unary Binary operators: Verilog operators operate on several data types to produce an output Not all Verilog operators are synthesible (can produce gates) Some operators are similar to those in the C language Remember, you are

More information

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2 Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely

More information

3. Implementing Logic in CMOS

3. Implementing Logic in CMOS 3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 27 September, 27 ECE Department,

More information

ACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1

ACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1 ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying

More information

1. Să se determine de câte ori apare cifra c în scrierea în baza p a numărului n.

1. Să se determine de câte ori apare cifra c în scrierea în baza p a numărului n. Observatii: Codul de mai jos a fost realizat si testat pe pagina online: https://www.tutorialspoint.com/compile_pascal_online.php 1. Să se determine de câte ori apare cifra c în scrierea în baza p a numărului

More information

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E.

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E. Introduction to Verilog Garrison W. Greenwood, Ph.D, P.E. November 11, 2002 1 Digital Design Flow Specification Functional Design Register Transfer Level Design Circuit Design Physical Layout Production

More information

Lecture 15: System Modeling and Verilog

Lecture 15: System Modeling and Verilog Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading

More information

UNIT 6 CIRCUIT DESIGN

UNIT 6 CIRCUIT DESIGN UNIT 6 CIRCUIT DESIGN 1 2 HIERARCHY DESIGN CMOS LOGIC CIRCUIT DESIGN Learning outcomes FOR HIERARCHY DESIGN Student should be able to: Define hierarchy design. Explain the levels of hierarchical design.

More information

Chapter 3 Part 2 Combinational Logic Design

Chapter 3 Part 2 Combinational Logic Design University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 3 Part 2 Combinational Logic Design Originals by: Charles R. Kime and Tom

More information

VLSI Design 13. Introduction to Verilog

VLSI Design 13. Introduction to Verilog Last module: Sequential circuit design Design styles This module Synthesis Brief introduction to Verilog Synthesis in the Design Flow Designer Tasks Tools Architect Logic Designer Circuit Designer Define

More information

The Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science

The Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Synthesis of combinational logic

Synthesis of combinational logic Page 1 of 14 Synthesis of combinational logic indicates problems that have been selected for discussion in section, time permitting. Problem 1. A certain function F has the following truth table: A B C

More information

C-Based Hardware Design

C-Based Hardware Design LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples

More information

Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers. Outline. Number Systems and Digital Logic Review Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

More information

Spiral 2-8. Cell Layout

Spiral 2-8. Cell Layout 2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric

More information

A Tutorial Introduction 1

A Tutorial Introduction 1 Preface From the Old to the New Acknowledgments xv xvii xxi 1 Verilog A Tutorial Introduction 1 Getting Started A Structural Description Simulating the binarytoeseg Driver Creating Ports For the Module

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 201 Memories Lecture 14: 1 Announcements HW6 will be posted tonight Lab 4b next week: Debug your design before the in-lab exercise Lecture 14: 2 Review:

More information

1 /8_ 2 /12 3 /12 4 /25 5 /12 6 /15 7 /16

1 /8_ 2 /12 3 /12 4 /25 5 /12 6 /15 7 /16 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.S084 Computation Structures Spring 2018 Practice Quiz #1 1 /8_ 2 /12 3 /12

More information

Single-Strip Static CMOS Layout

Single-Strip Static CMOS Layout EE244: Design Technology for Integrated Circuits and Systems Outline Lecture 6.2 Regular Module Structures CMOS Synthetic Libraries Weinberger Arrays Gate Matrix Programmable Logic Array (PLA) Storage

More information

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example David Harris Harvey Mudd College Spring 2004 Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design

More information

Actel HDL Coding. Style Guide

Actel HDL Coding. Style Guide Actel HDL Coding Style Guide Actel Corporation, Mountain View, CA 94043 2006 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029105-7 Release: November 2006

More information

EECS 151/251A: SRPING 2017 MIDTERM 1

EECS 151/251A: SRPING 2017 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Thursday, Mar 2 nd, 2017 7:00-8:30pm EECS 151/251A: SRPING 2017 MIDTERM 1 NAME Last First

More information

Combinational Logic Worksheet

Combinational Logic Worksheet Combinational Logic Worksheet Concept Inventory: Truth tables sum-of-products equations implementation using NOT/AND/OR Demorgan s Law, implementation using NAND/NOR Simplification, truth tables w/ don

More information

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

Design of Digital Circuits Lecture 6: Combinational Logic, Hardware Description Lang. & Verilog. Prof. Onur Mutlu ETH Zurich Spring March 2018

Design of Digital Circuits Lecture 6: Combinational Logic, Hardware Description Lang. & Verilog. Prof. Onur Mutlu ETH Zurich Spring March 2018 Design of Digital Circuits Lecture 6: Combinational Logic, Hardware Description Lang. & Verilog Prof. Onur Mutlu ETH Zurich Spring 2018 9 March 2018 Required Lecture Video Why study computer architecture?

More information

Introduction to Verilog

Introduction to Verilog Introduction to Verilog Course Objectives Learn the basic constructs of Verilog Learn the modeling structure of Verilog Learn the concept of delays and their effects in simulation Course Outline Verilog

More information

PAGE NO: EXP NO: 1A SIMULATION OF HALF ADDER AND FULL ADDER. DATE: AIM: To design, simulate and synthesize the Half adder and Full adder. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the

More information

HDL for Combinational Circuits. ENEL211 Digital Technology

HDL for Combinational Circuits. ENEL211 Digital Technology HDL for Combinational Circuits ENEL211 Digital Technology Lecture Outline Vectors Modular design Tri-state gates Dataflow modelling Behavioural Modelling Vectors Often we want multi-bit quantities in digital

More information

Lab 4: Arithmetic Logic Unit (ALU)

Lab 4: Arithmetic Logic Unit (ALU) EE 231-1 - Fall 2016 Lab 4: Arithmetic Logic Unit (ALU) Introduction The heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of the computer which performs arithmetic operations

More information

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers Universit Electrical & Computer Engineering Fall 2013 Lecture #23: Verilog Structural and Behavial Design Hardware Description Languages [ Recall from

More information

Se cer 2 variante: una cu implementarea statica si a doua cu implementarea dinamica a structurilor de date necesare. Comentati variantele.

Se cer 2 variante: una cu implementarea statica si a doua cu implementarea dinamica a structurilor de date necesare. Comentati variantele. Lucrarea 1 SDA 03.04.2017 Sa se realizeze urmatoarele programe, in limbaj C: 1. Se primesc de la intrarea standard: un numar k si un sir infinit de numere naturale a i. Se afiseaza la iesirea standard,

More information

Overview of Verilog Part 1

Overview of Verilog Part 1 University of Wisconsin - Madison ECE/Comp ci 352 Digital ystems Fundamentals Charles R. Kime ection 2 Fall 2001 Chapters 3 and 4 Verilog Part 1 Minor Updates on 11/9/01 are shown in red. Charles Kime

More information

Lecture 4: MIPS Processor Example

Lecture 4: MIPS Processor Example Lecture 4: MIPS Processor Example Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture

More information

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs EE 352 Unit 8 HW Constructs Logic Circuits Combinational logic Perform a specific function (mapping of 2 n input combinations to desired output combinations) No internal state or feedback Given a set of

More information

The Verilog Hardware Description Language

The Verilog Hardware Description Language Donald Thomas Philip Moorby The Verilog Hardware Description Language Fifth Edition 4y Spri nnger Preface From the Old to the New Acknowledgments xv xvii xxi 1 Verilog A Tutorial Introduction Getting Started

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 8 Design Rules Adib Abrishamifar EE Department IUST Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell

More information

Introduction*To*Verilog*for* Combinational*Logic. General*Module*Structure

Introduction*To*Verilog*for* Combinational*Logic. General*Module*Structure Introduction*To*Verilog*for* Combinational*Logic Verilog*is*a*language*used*for*simulation*and* synthesis*of*digital*logic. A*New*Extension* System*Verilog *also*supports* new*features*including*verification*of*digital*systems

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 2012) The Register Transfer Level Daniel Kroening Oxford University, Computer Science Department Version 1.0, 2011 Outline Reminders Gates Implementations of Gates Latches, Flip-flops

More information

HMP7001 Manual de utilizare

HMP7001 Manual de utilizare www.philips.com/welcome HMP7001 Manual de utilizare Interface are trademarks or registered trademarks of HDMI licensing LLC in the United States and other countries. Manufactured under license from Dolby

More information

Lecture 2: MIPS Processor Example

Lecture 2: MIPS Processor Example Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example Outline Design Partitioning MIPS Processor Example Architecture t Microarchitecture Logic Design Circuit Design Physical Design Fabrication,

More information

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL?

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL? Why use an HDL? Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL Increase digital design engineer s productivity (from Dataquest) Behavioral HDL RTL HDL Gates Transistors 2K 10K gates/week

More information

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

More information

Fişiere in C++ Un fişier este o colecţie de date indicat printr-un nume şi o extensie. Numele este desparţit de extensie prin punct.

Fişiere in C++ Un fişier este o colecţie de date indicat printr-un nume şi o extensie. Numele este desparţit de extensie prin punct. Fişiere in C++ Un fişier este o colecţie de date indicat printr-un nume şi o extensie. Numele este desparţit de extensie prin punct. Avantajul lucrului cu fisiere este evident, datele rezultate în urma

More information

Synthesizable Verilog

Synthesizable Verilog Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL

More information

DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL (REGULATION-2013) LAB MANUAL DEPARTMENT OF ECE NAME: REGISTER NUMBER: YEAR/SEM.: ACADEMIC YEAR: 2015-2016 DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in

More information

Digital Integrated Circuits Lecture 2: MIPS Processor Example

Digital Integrated Circuits Lecture 2: MIPS Processor Example Digital Integrated Circuits Lecture 2: MIPS Processor Example Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec2 cwliu@twins.ee.nctu.edu.tw 1 Outline

More information