UNIT 6 CIRCUIT DESIGN

Transcription

1 UNIT 6 CIRCUIT DESIGN 1 2 HIERARCHY DESIGN CMOS LOGIC CIRCUIT DESIGN

2 Learning outcomes FOR HIERARCHY DESIGN Student should be able to: Define hierarchy design. Explain the levels of hierarchical design. Explain examples of circuit design using this approach such as 1-bit full adder design.

3 Learning outcomes FOR cmos logic circuit design Student should be able to: Explain how NMOS and PMOS transistors function as switches for logic 0 and logic 1. Explain CMOS inverter circuits. Explain CMOS transmission gate circuits. Construct CMOS multi-input NAND gate. Construct CMOS multi-input NOR gate. Construct any combinational logic gate.

4 Source : DEFINITION OF HIERARCHY DESIGN Hierarchy design is technique involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. This approach is very similar to the software case where large programs are split into smaller and smaller sections until simple subroutines, with well-defined functions and interfaces, can be written.

5 Source : DEFINITION OF HIERARCHY DESIGN Figure showing the structural decomposition of a CMOS four-bit adder into its components. The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates.

6 Source : Advantage of HIERARCHY DESIGN A clean hierarchical organization makes all phases of design easier. If each level of the hierarchy has obvious functionality and aggregates only those components that pertain (berkaitan) to that hierarchical level, then the circuit is easier to understand. With a good hierarchy, simulation can be done effectively by completely testing each level of the hierarchy starting at the bottom.

7 Source : Techniques in HIERARCHY DESIGN Two types: Top down from high-level description to layout high level functions are defined first, and the lower level implementation details are filled in later. Bottom up from cells to blocks to systems

8 The top level block represents the entire chip. The next lower level blocks also represent the entire chip but divided into the major function blocks of the chip. Intermediate level blocks divide the functionality into more manageable pieces. The bottom level contains only gates and macrofunctions.

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15 Example : 1-bit full adder

16 1-bit full adder (transistor level) How to generate transistor-level schematic?

17 1-bit full adder (gate level) How to generate gate-level schematic?

18 1-bit full adder (RTL level) How to generate RTL-level schematic? entity BIT_ADDER is port( A, B, CARRY_IN : in bit; SUM, CARRY_OUT : out bit ); end entity BIT_ADDER; architecture BHV of BIT_ADDER is begin SUM <= (A xor B xor CARRY_IN); CARRY_OUT <= (A and B) or (A and CARRY_IN); end architecture BHV;

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24 users.ece.utexas.edu/~adnan/vlsi-05-backup/lec3mos.ppt

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26 users.ece.utexas.edu/~adnan/vlsi-05-backup/lec3mos.ppt

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46 CMOS CIRCUIT FROM BOOLEAN FUNCTION

47 CMOS CIRCUIT FROM BOOLEAN FUNCTION PMOS + : parallel : series

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49 CMOS CIRCUIT FROM BOOLEAN FUNCTION NMOS

50 CMOS CIRCUIT FROM BOOLEAN FUNCTION

51 EXERCISE 1. Draw the schematic of CMOS static logic circuit for the following equation. i. ii. iii.

52 ASSIGNMENT 2 1. Draw the schematic based on the CMOS transistor which can implement the logic equation as below: 2. Determine the schematic diagram based on the CMOS transistor that can implement the logic equation as below: 3. Determine the schematic diagram based on the CMOS transistor that can implement the logic equation as below: i. ii. INDIVIDUALLY. DUE DATE : 2 WEEKS FROM NOW IN HANDWRITING