Digital Integrated CircuitDesign

Transcription

1 Digital Integrated CircuitDesign Lecture 8 Design Rules Adib Abrishamifar EE Department IUST

2 Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell Design Standard Cells Datapath Cells Sticks Diagrams Logic Graph Euler Path Area Estimation Summary 2/50

3 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) 3/50

4 Design Rules CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 4/50

5 Design Rules Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select Contact or Via Hole 2 2 Metal1 Metal /50

6 Design Rules Transistor Layout Transistor /50

7 Design Rules Via s and Contacts 1 Metal to Active Contact 1 Via 1 Metal to Poly Contact /50

8 Design Rules Select Layer Select Substrate Well 8/50

9 Design Rules CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 9/50

10 Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell Design Standard Cells Datapath Cells Sticks Diagrams Logic Graph Euler Path Area Estimation Summary 10/50

11 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width 11/50

12 Cell Design Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology Vdd and GND should abut (standard height) Adjacent gates should satisfy design rules NMOS at bottom and PMOS at top All gates include well and substrate contacts 12/50

13 Cell Design Standard Cell Layout Methodology-1980s Routing channel V DD signals GND 13/50

14 Cell Design Standard Cell Layout Methodology-1990s Mirrored Cell No Routing channels V DD V DD M1 M2 Mirrored Cell GND GND 14/50

15 Cell Design Standard Cells N Well V DD Cell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects 2λ In Out Cell height is 12 pitch Cell boundary GND Rails ~10λ 15/50

16 Cell Design Standard Cells With minimal diffusion routing V DD With silicided diffusion V DD V DD M 2 In Out In Out In Out M 1 GND GND 16/50

17 Cell Design Standard Cells V DD 2-input NAND gate V DD A B B Out A GND 17/50

18 Cell Design Standard Cells CMOS Inverter N Well V DD PMOS 2λ V DD Contacts In PMOS Out Polysilicon In Out Metal 1 NMOS NMOS GND 18/50

19 Cell Design Standard Cells Two Inverters Share power and ground V DD Connect in Metal 19/50

20 Cell Design Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance 20/50

21 Cell Design Inverter 21/50

22 Cell Design NAND3 Horizontal N-diffusion and P-diffusion strips Vertical polysilicon gates Metal1 Vdd rail at top Metal1 GND rail at bottom 22/50

23 Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell Design Standard Cells Datapath Cells Sticks Diagrams Logic Graph Euler Path Area Estimation Summary 23/50

24 Sticks Diagrams To help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers 24/50

25 Sticks Diagrams Contains No Dimensions Represents Relative Positions of Transistors V DD V DD Inverter NAND2 Out Out GND In GND A B 25/50

26 Sticks Diagrams Stick Diagram for a 4-input NOR Gate A +Vdd VDD A B C D B C Y D Y A B C D GND 26/50

27 Sticks Diagrams Logic Graph Logic Graph X Pull Up Network (PUN) C X i V DD B j GND A (PDN) Pull Down Network 27/50

28 Sticks Diagrams OAI22 Logic Graph A B C D D X C PUN X = (A+B) (C+D) X V DD C D B A A B A B C D GND PDN 28/50

29 Sticks Diagrams Logic Graph A B j C Logic Graph X C PUN X = C (A + B) X i V DD C i B j A A B A B C GND PDN 29/50

30 Sticks Diagrams Two Versions of C(A + B) A C B A B C V DD V DD X X GND GND 30/50

31 Sticks Diagrams Consistent Euler Path X C X i V DD B j A GND A B C 31/50

32 Sticks Diagrams Euler Path and Circuit As legend has it, a resident of Konigsberg wrote to Leonard Euler saying that a popular pastime for couples was to try to cross each of the seven bridges in the city exactly once, without crossing any bridge more than once It was well-known that the feat could not be accomplished, yet no one knew why. Could Euler, great mathematician as he was, answer that question 32/50

33 Sticks Diagrams Euler Path and Circuit In Konigsberg, Germany, a river ran through the city such that in its center was an island, and after passing the island, the river broke into two parts. Seven bridges were built so that the people of the city could get from one part to another as below 33/50

34 Sticks Diagrams Euler Path and Circuit Euler realized that all problems of this form could be represented by replacing areas of land by points (he called them vertices), and the bridges to and from them by arcs 34/50

35 Sticks Diagrams Euler Path and Circuit Once the problem is simplified the graph of the bridges and land look like this 35/50

36 Sticks Diagrams Euler Path and Circuit The problem now becomes one of drawing this picture without retracing any line and without picking your pencil up off the paper 36/50

37 Sticks Diagrams Euler Path and Circuit Euler looked at the vertices that had an odd number of lines connected to it He stated they would either be the beginning or end of his pencil-path 37/50

38 Sticks Diagrams Euler Path and Circuit Euler path: a continuous path that passes through every edge once and only once Euler circuit: when a Euler path begins and ends at the same vertex 38/50

39 Sticks Diagrams Euler Path and Circuit Euler s 1 st Theorem If a graph has any vertices of odd degree, then it can't have any Euler circuit If a graph is connected and every vertex has an even degree, then it has at least one Euler circuit (usually more) 39/50

40 Sticks Diagrams Euler Path and Circuit Euler s 2 nd Theorem If a graph has more than two vertices of odd degree, then it cannot have an Euler path If a graph is connected and has exactly two vertices of odd degree, then is has at least one Euler path. Any such path must start at one of the odd degree vertices and must end at the other odd degree vertex 40/50

41 Sticks Diagrams Euler Path and Circuit Path, circuit, or neither? 41/50

42 Sticks Diagrams Example: x = ab + cd x x b c b c x V DD x V DD a d a d GND GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} V DD x GND a b c d (c) stick diagram for ordering {a b c d} 42/50

43 Sticks Diagrams Area Estimation Wiring Tracks A wiring track is the space required for a wire 4 λ width, 4 λ spacing from neighbor = 8 λ pitch Transistors also consume one wiring track 43/50

44 Sticks Diagrams Area Estimation Well Spacing Wells must surround transistors by 6 λ Implies 12 λ between opposite transistor flavors Leaves room for one wire track 44/50

45 Sticks Diagrams Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in λ 45/50

46 Sticks Diagrams Area Estimation Stick diagram for O3AI and estimate area Y = ( A + B + C) D A B C D +Vdd D Y A B C 46/50

47 Sticks Diagrams Area Estimation Stick diagram for O3AI and estimate area Y = ( A + B + C) D 47/50

48 Sticks Diagrams Area Estimation Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C) D 48/50

49 Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell Design Standard Cells Datapath Cells Sticks Diagrams Logic Graph Euler Path Area Estimation Summary 49/50

50 Summary This lecture describes the basic design rules for the layout of both MOS and CMOS transistors, cells design methodologies and also sticks diagrams. Specifically described in detail are: Design Rules Cells Design Methodologies Sticks Diagrams Logic Graph Euler Path Area Estimation 50/50