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2 STK50... User Guide

3

4 Table of Contents Table of Contents Section Introduction Features...- Section Using the STK50 Top Module Connecting the STK50 to the STK500 Starter Kit Placing an ATmega03(L) or ATmega8(L) on the STK PORT Connectors PORT E/PORT F PORT G/AUX PG0 - PG A SRAMEN PEN Programming the ATmega03(L)/ 8(L) In-System Programming High-voltage Programming JTAG Connector External SRAM A SRAMEN Ram High Address Jumpers A[7:0] Connector Using the SRAM Interface with AT90S/LS855 and ATmega TOSC Switch RS-3C Port...-9 Section 3 Troubleshooting Guide Section 4 Technical Specifications Section 5 Technical Support i

5 Table of Contents Section 6 Complete Schematics ii

6 Section Introduction The STK50 board is a top module designed to add ATmega03(L) and ATmega8(L) support to the STK500 development board from Atmel Corporation. With this board the STK500 is extended to support all current AVR devices in a single development environment. The STK50 includes connectors, jumpers and hardware allowing full utilization of the new features of the ATmega8(L) while the Zero Insertion Force (ZIF) socket allows easy use of TQFP packages for prototyping. This user guide acts as a general getting started guide as well as a complete technical reference for advanced users. In addition to adding support for new devices, it also adds new support for peripherals previously not supported by the STK500. An additional RS-3 port and external SRAM interface are09/0 among the new features. Devices with dual UART or XRAM interface can all take advantage of the new resources on the STK50 board. Figure -. STK50 Top Module for STK500 AVR STK50 User Guide - Rev. 49A-09/0

7 Introduction. Features STK500 Compatible AVR Studio Compatible Supports ATmega03(L) and ATmega8(L) Zero Insertion Force Socket for TQFP Packages TQFP Footprint for Emulator Adapters Supports all Added Features in ATmega8(L) JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega8(L)) Additional RS-3C Port with Available RTS/CTS Handshake Lines Adds External SRAM Support to the STK500 Board (Usable for all Devices with XRAM Interface) On-board 3 khz Crystal for Easy RTC Implementations - AVR STK50 User Guide

8 Section Using the STK50 Top Module. Connecting the STK50 to the STK500 Starter Kit The STK50 should be connected to the STK500 expansion header 0 and. It is important that the top module is connected in the correct orientation as shown in Figure -. The EXPAND0 written on the STK50 top module should match the EXPAND0 written beside the expansion header on the STK500 board. Figure -. Connecting STK50 to the STK500 Board Note: Connecting the STK50 with wrong orientation may damage the board... Placing an ATmega03(L) or ATmega8(L) on the STK500 The STK50 contains both a ZIF socket, and the pinout for a TQFP package; which allows an easy way of soldering an emulator adapter directly into the STK50. Care should be taken so that the device (or adapter) is mounted with the correct orientation. Figure - shows the location of pin for the ZIF socket and the TQFP footprint. Caution: Do not mount an ATmega03(L) or ATmega8(L) on the STK50 at the same time as an AVR is mounted on the STK500 board. AVR STK50 User Guide - Rev. 49A-09/0

9 Using the STK50 Top Module Figure -. Pin on ZIF Socket and TQFP Footprint. PORT Connectors Since the ATmega03(L) and ATmega8(L) have additional ports not available on the STK500, these ports are located on the STK50 board. They have the same pinout and functionality as the ports on the STK500 board. Port A to Port D which are already present on the STK500 board are not duplicated on the STK50... PORT E/PORT F Figure -3 shows the pinout for the I/O port headers Port E and Port F. Figure -3. General I/O Ports PE0 PE PE4 PE6 PORT E PE PE3 PE5 PE7 PF0 PF PF4 PF6 PORT F PF PF3 PF5 PF7 Note: Port E is also present on the STK500, but only PE0 to PE (3 least significant bits) are accessible there. To access all Port E bits the connector on the STK50 must be used. - AVR STK50 User Guide

10 Using the STK50 Top Module.. PORT G/AUX In addition to the normal Port G pins, this connector has some extra signals. See Figure -4. Figure -4. PORTG/AUX PG0 PG PG4 SRAMEN... PG0 - PG4 These are general I/O ports for the ATmega8(L) and connect to the ZIF socket and the TQFP footprint. The PG3 and PG4 signals are routed through the TOSC switch since these pins also are inputs for a 3 khz oscillator. For a description on the TOSC switch see Section.9. Note: ATmega03(L) does not have Port G.... A6 This line goes to A6 (most significant address bit) on the SRAM. See Section.5 for more information about this signal. can be connected to any AVR pin....3 SRAMEN The SRAMEN signal controls if the SRAM is enabled or not. To enable the SRAM a LOW level should be applied to this pin. See External SRAM, Section.5, for more information on how to use this signal. This signal is pulled high by default....4 PEN The PEN pin is connected to the PEN pin on the ATmega03(L)/8(L). This pin is described in the programming section of the ATmega03(L) and ATmega8(L) datasheets. PG PG3 A6 PEN PORT G/AUX.3 Programming the ATmega03(L)/ 8(L).3. In-System Programming The ATmega03(L) and ATmega8(L) can be programmed using both SPI and Highvoltage Parallel Programming. This sub section will explain how to connect the programming cables to successfully use one of these two modes. The AVR Studio STK500 software is used in the same way as for other AVR parts. Note: The ATmega8(L) also supports Self Programming. See AVR09 application note for more information on this topic. To program the ATmega03(L) or ATmega8(L) using ISP programming mode, connect the 6-wire cable between the ISP6PIN connector on the STK500 board and the ISP connector on the STK50 board as shown in Figure -5. The device can be programmed using the serial programming mode in the AVR Studio STK500 software. Note: See the STK500 User Guide for information on how to use the STK500 frontend software for ISP programming. AVR STK50 User Guide -3

11 Using the STK50 Top Module Figure -5. In-System Programming.3. High-voltage Programming To program the ATmega03(L) or ATmega8(L) using High-voltage (Parallel) Programming, connect the PROGCTRL to PORTD and PROGDATA to PORTB on the STK500 as shown in Figure -6. As described in the STK500 User Guide, the BSFL jumper must be mounted when High-voltage Programming ATmega devices. This also applies to the High-voltage Programming of ATmega03(L) and ATmega8(L). The device can now be programmed using the High-voltage Programming mode in AVR Studio STK500 software. Note: See the STK500 User Guide for information on how to use the STK500 frontend software in High-voltage Programming mode. Note: For the High-voltage Programming mode to function correctly, the target voltage must be higher than 4.5V. Caution: Make sure the SRAM (if mounted) can handle this voltage. -4 AVR STK50 User Guide

12 Using the STK50 Top Module Figure -6. High-voltage (Parallel) Programming.4 JTAG Connector The JTAG connector is intended for the ATmega8(L) that has a built-in JTAG interface. The pinout of the JTAG connector is shown in Figure -7 and is compliant with the pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector allows On-chip Debugging of the ATmega8(L). More information about the JTAG ICE and On-chip Debugging can be found in the AVR JTAG ICE User Guide, which is available at the Atmel web site, Figure -7. JTAG Connector TCK TDO TMS TDI JTAG RST NC Figure -8 shows how to connect the JTAG ICE probe on the STK50 board. AVR STK50 User Guide -5

13 Using the STK50 Top Module Figure -8. Connecting JTAG ICE to the STK50.5 External SRAM The STK50 contains a footprint where an external SRAM device can be mounted. Make sure the SRAM device has the same voltage range as the rest of the design. Caution: Special care should be taken if a low voltage SRAM is used, since High-voltage Programming requires a programming voltage higher than 4.5V. Low-voltage SRAM may be damaged if High-voltage Programming of the target AVR is done. Table - shows a list of recommended SRAM devices, and typical range of operation. It is important that the SRAM device is soldered with the correct orientation as shown in Figure -9. Note: The SRAM is disabled by default. To enable SRAM support, put a jumper between the SRAMEN and pin on the PORTG/AUX connector. Figure -9. Pin on SRAM Footprint and Pinout A0 A A A3 CS D0 D VCC D D3 WE A4 A5 A6 A Kx A6 A5 A4 A3 OE D7 D6 VCC D5 D4 A A A0 A9 A8-6 AVR STK50 User Guide

14 Using the STK50 Top Module Table -. Recommended SRAM Devices Manufacturer Part Number Supply Voltage (V) Package ISSI IS63LV04-T 3.3 TSOP-II ISSI IS63LV04-J 3.3 SOJ 300-mil ISSI IS63LV04-K 3.3 SOJ 400-mil IDT IDT74-Y 5.0 SOJ 400-mil IDT IDT7V4SA-TY 3.3 SOJ 300-mil IDT IDT7V4SA-Y 3.3 SOJ 400-mil IDT IDT7V4SA-PH 3.3 TSOP-II.5. A6 The A6 pin on the PORTG/AUX connector is connected to A6 (address pin 6) on the SRAM. ATmega03(L) and ATmega8(L) support up to 60 KB of external SRAM. The STK50 SRAM footprint is for a 8 KB SRAM. Implementing software control of the A6 line will increase the memory range from 64 KB to 8 KB. This line is pulled low by default, addressing the lower 64 KB of the SRAM. Figure -0. SRAM Block Schematic AVR SRAM PORTC From PORTG/AUX connector A6 SRAMEN PC7 PC6 PC5 PC4 PC3 PC PC PC0 RAM HIGH ADDRESS A6 A5 A4 A3 A A A0 A9 A8 0K x RD (PG) WR (PG0) CE OE WE ALE (PG) LE OE PA7 PA6 PA5 PA4 PA3 PA PA PA0 D7 D6 D5 D4 D3 D D D0 LATCH Q7 Q6 Q5 Q4 Q3 Q Q Q0 A7 A6 A5 A4 A3 A A A0 A0 A A4 A6 A[7:0] A A3 A5 A7 A7 A6 A5 A4 A3 A A A0 A7 A6 A5 A4 A3 A A A0 D7 D6 D5 D4 D3 D D D0 PA7 PA6 PA5 PA4 PA3 PA PA PA0 PORTA.5. SRAMEN The SRAMEN pin on the PORTG/AUX connector is connected to the Chip-enable (CE) pin of the SRAM. This signal controls if the SRAM should be enabled or not. To enable the SRAM, a low level should be applied to this pin. This pin is pulled high by default, through a 0 kω resistor. Figure -0 shows a simplified block schematic on how the SRAM interface is implemented. Figure - shows how to enable the SRAM by shorting SRAMEN and on the PORTG/AUX connector using one of the supplied jumpers. This signal can also be controlled by software or by some external control logic. AVR STK50 User Guide -7

15 Using the STK50 Top Module Figure -. SRAMEN Connected to.6 Ram High Address Jumpers When External Memory is enabled in an AVR, all Port C pins are by default used for the high address byte. If the full 60 KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal port pin function as described in the ATmega8(L) datasheet. AT90S/LS855, ATmega03(L) and ATmega6 do not have this feature, and all jumpers should be connected if using the XRAM interface with these devices. If some or all of the Port C pins are released for normal port pin functions, the corresponding RAM High Address jumper should be removed to avoid any Port C activity to reach the SRAM address pins thus corrupting the address. If a jumper is removed, the corresponding address line will be pulled low giving a logic zero on that address bit on the SRAM. See the block schematic on Figure A[7:0] Connector The connector marked A[7:0] contains the 8 least-significant bits of the external SRAM address bus. The purpose of the connector is to provide easy access to the address bus. The 8 most significant bits can be found on the Ram High Addresses jumpers or the Port C connector. The connector is placed after the latch as shown in Figure -0. This connector is handy when using the SRAM interface to interface external devices..8 Using the SRAM Interface with AT90S/LS855 and ATmega6 When using the SRAM interface with devices placed in the STK500 board, some additional straps are required. The reason is that the RD, WR, and ALE signals are not on the same port pins for the AT90S855/ATmega6(L) and ATmega03(L)/ ATmega8(L), so these signals must be routed manually using two of the -wire cables. Table -. Signal Routing Required for AT90S855A and ATmega6(L) Connections STK500 STK50 Description Write Signal WR PD6 PG0 Connect PD6:STK500 to PG0:STK50 Read Signal RD PD7 PG Connect PD7:STK500 to PG:STK50 Address Latch Enable ALE PE PG Connect PE:STK500 to PG:STK50-8 AVR STK50 User Guide

16 Using the STK50 Top Module Figure -. Enabling SRAM Interface for Devices in STK500.9 TOSC Switch On the ATmega8(L) the TOSC and TOSC lines are shared with Port G (PG4 and PG3). The TOSC switch select if the 3 khz crystal, or the Port G connector pins should be connected to the pins on the device. Figure -3 shows a simplified block schematic on how this is implemented. Note: Port G is not available on the ATmega03(L), the switch will thus only select if the 3 khz crystal should be connected or not. Figure -3. TOSC Block Schematic AVR 3 khz PG3/TOSC PG4/TOSC TOSC Switch PG3 PG4 To PORT G/AUX Connector.0 RS-3C Port The ATmega8(L) has an additional UART compared to the ATmega03(L). The RS- 3 port on the STK50 board has in addition to the RXD and TXD lines support for RTS and CTS flow control. Figure -4 shows a simplified block schematic on how this is implemented. Note: The UART in ATmega8(L) does not support hardware RTS or CTS control. If such functionality is needed, it must be implemented in software. AVR STK50 User Guide -9

17 Using the STK50 Top Module Figure -4. UART Block Schematic RS3 SPARE RS-3/Logic Level Converter RxD CTS TxD RTS This UART can also be used from devices placed in the STK500 board. Simply connect the appropriate port pins to RXD and TXD on the STK50 board. Note: If no software RTS/CTS flow control is implemented, a jumper shorting RTS and CTS will ensure correct communication with an external application that uses such flow control. -0 AVR STK50 User Guide

18 Section 3 Troubleshooting Guide Table 3-. Troubleshooting Guide Problem Reason Solution SRAM does not work properly. SRAM does not work when used by devices on the STK500 board. After doing a High-voltage Programming of the AVR, the SRAM does not work properly. The SRAM is not connected. SRAMEN is not mounted. XRAM interface is not enabled in the AVR device. Some of the ADDRESS HIGH BYTE jumpers may be set incorrectly. WR, RD and ALE signals must be strapped using two -wire cables. The SRAM might be damaged due to the Highvoltage needed to program the AVR. Verify all solderings, and make sure the Pin on the SRAM matches the one on the footprint. Make sure the SRAM pinout is correct. Make sure that the SRAMEN is connected to on the AUX connector. Verify that the code actually enables the XRAM interface. Connect some or all of ADDRESS HIGH BYTE jumpers. Use two -wire cables, and connect these signals to the appropriate pins. Make sure the SRAM handles 5V, if High-voltage Programming mode should be used. AVR STK50 User Guide 3-

19 Troubleshooting Guide 3- AVR STK50 User Guide

20 Section 4 Technical Specifications System Unit Physical Dimensions x 9 x 7 mm Weight g Operating Conditions Voltage Supply V - 5.5V Connections Serial Connector pin D-SUB female Serial Communications Speed kbps AVR STK50 User Guide 4-

21 Technical Specifications 4- AVR STK50 User Guide

22 Section 5 Technical Support For Technical support, please contact avr@atmel.com. When requesting technical support, please include the following information: Which target AVR device is used (complete part number) Target voltage and speed Clock source and fuse setting of the AVR Programming method (ISP or High-voltage) Hardware revisions of the AVR tools, found on the PCB Version number of AVR Studio. This can be found in the AVR Studio help menu. PC operating system and version/build PC processor type and speed A detailed description of the problem AVR STK50 User Guide 5-

23 Technical Support 5- AVR STK50 User Guide

24 Section 6 Complete Schematics On the following pages the complete schematics and assembly drawing of the STK50 revision B are shown. AVR STK50 User Guide 6-

25 Complete Schematics Figure 6-. Schematics, of 3 D C B A TQFP Footprint ZIF Socket PAT[7..0] PAT[7..0] PFT[7..0] PFT[7..0] PAT[7..0] PFT[7..0] PFT[7..0] PAT[7..0] PET[7..0] PET[7..0] PET0 PET PET PET3 PET4 PET5 PET6 PET7 PBT0 PBT PBT PBT3 PBT4 PBT5 PBT6 PCT[7..0] PCT[7..0] PBT7 PBT[7..0] PBT[7..0] PDT[7..0] PDT[7..0] TOSC TOSC TOSC XT TOSC XT RESET RESET XT RESET RESET XT PGT[4..0] PGT[4..0] STK50 Page of 3 A B Rev. B 9-Jun-00 Copyright Atmel Corporation D C B A PAT0 PAT PAT PAT3 PAT4 PAT5 PAT6 PAT7 PCT7 PCT6 PCT5 PCT4 PCT3 PCT PCT PCT0 PGT PDT0 PDT PDT PDT3 PDT4 PDT5 PDT6 PDT7 PFT0 PFT PFT PFT3 PFT4 PFT5 PFT6 PFT7 AREFT AREFT AREFT AREFT PEN PEN PEN PEN PAT0 PAT PAT PET[7..0] PET[7..0] A C08 00N_6V_X7R PET0 PET PET PET3 PET4 PET5 PET6 PET7 PBT0 PBT PBT PBT3 PBT4 PBT5 PBT6 PAT3 PAT4 PAT5 PAT6 PAT7 PCT7 PCT6 PCT5 PCT4 PCT3 PCT PCT PCT0 PCT[7..0] PCT[7..0] PGT PGT TQFP64 ZIF SOCKET PGT PGT0 PGT0 PBT7 PDT0 PDT PDT PDT3 PDT4 PDT5 PDT6 PDT7 PFT0 PFT PFT PFT3 PFT4 PFT5 PFT6 PFT7 A PEN 3 PE0/PDI/RXD PE/PDO/TXD 4 PE/AC+ 5 6 PE3/AC- PE4/INT4 7 PE5/INT5 8 9 PE6/INT6 0 PE7/INT7 PB0/SS PB/SCK 3 PB/MOSI 4 PB3/MISO 5 PB4/OC0 6 PB5/OCA PB6/OCB AD3/PA3 48 AD4/PA4 47 AD5/PA5 46 AD6/PA6 45 AD7/PA7 44 ALE/PG 43 A5/PC7 4 A4/PC6 4 A3/PC5 40 A/PC4 39 A/PC3 38 A0/PC A9/PC 35 A8/PC0 RD/PG WR/PG0 PBT[7..0] PBT[7..0] TOSC TOSC PDT[7..0] PDT[7..0] TOSC TOSC PGT[4..0] PGT[4..0] A L0 BLM-A0S C0 00N_6V_X7R C0 00N_6V_X7R C05 00N_6V_X7R C06 00N_6V_X7R PB7/OC PG3/TOSC PG4/TOSC RESET VCC XTAL XTAL PD0/INT0 PD/INT PD/INT PD3/INT3 PD4/IC PD5 PD6/T PD7/T ADC0/PF0 ADC/PF ADC/PF ADC3/PF3 ADC4/PF4 ADC6/PF6 ADC6/PF6 ADC7/PF7 AD0/PA0 AD/PA AD/PA AVCC A AREF VCC U0 ATMEGA ST C03 00N_6V_X7R C04 00N_6V_X7R C07 00N_6V_X7R 6- AVR STK50 User Guide

26 Complete Schematics Figure 6-. Schematics, of 3 D C B A PET[7..0] PET[7..0] XT XT RESET RESET PET PCT7 PCT5 PCT3 PCT PAT7 PAT5 PAT3 PAT AREFT PET PET0 PCT6 PCT4 PCT PCT0 PAT6 PAT4 PAT PAT0 AREFT 5 6 XT 7 8 XT 9 0 PBT7 3 4 PBT6 PBT5 5 6 PBT4 C0 PBT3 7 8 PBT 00N_6V_X7R PBT 9 30 PBT0 PDT7 3 3 PDT6 PDT PDT4 PDT PDT PDT PDT EXPAND0 EXPAND PAT[7..0] PDT[7..0] PAT[7..0] PDT[7..0] PCT[7..0] PCT[7..0] PBT[7..0] PBT[7..0] PET PET0 4 6 J06 VCC MOSI MISO SCK 3 5 RESET ISP_CONNECTOR STK50 Page of 3 A B Rev. B 9-Jun-00 Copyright Atmel Corporation D C B A PBT C0 00N_6V_X7R R0 0R R03 0R PFT4 PFT6 PFT5 PFT7 J JTAG RESET C03 00N_6V_X7R RESET C04 00N_6V_X7R PFT[7..0] PGT[4..0] A[7..0] PFT[7..0] PGT[4..0] A[7..0] J03 J05 J08 J07 PFT0 PFT PET0 PET PGT0 PGT A0 A PFT 3 4 PFT3 PET 3 4 PET3 PGT 3 4 PGT3 A 3 4 A3 PFT4 5 6 PFT5 PET4 5 6 PET5 PGT4 5 6 A6 A4 5 6 A5 A6 PFT6 7 8 PFT7 PET6 7 8 PET7 SRAMEN 7 8 A6 7 8 A7 SRAMEN PORTF PORTE JS0 JS0 PORTG/AUX LATCHED ADDRESS R0 0K Port G special features PG0: nwr PEN PG: nrd PEN PG: ALE J J NOT MOUNTED PG3: TOSC PG4: TOSC AVR STK50 User Guide 6-3

27 Complete Schematics Figure 6-3. Schematics, 3 of 3 D C B A A[7..0] A[7..0] U30 74AHC573PW OE LE Q0 9 Q 8 D0 Q 7 3 D Q3 6 4 D Q D3 Q5 4 D4 Q6 3 7 D5 Q7 8 9 D6 D7 STK50 Page of 3 3 A B Rev. B 9-Jun-00 Copyright Atmel Corporation D C B A 0 VCC 0 C30 00N_6V_X7R PAT0 PAT PAT PAT3 PAT4 PAT5 PAT6 PAT7 A0 A A A3 A4 A5 A6 A7 JS30 JS30 JS303 JS304 JS305 JS306 JS307 JS308 PCT0 PCT PCT PCT3 PCT4 PCT5 PCT6 PCT7 A0 A A A3 A4 A5 A6 A7 A8 A9 A0 A A A3 A4 A5 A6 PAT0 PAT PAT PAT3 PAT4 PAT5 PAT6 PAT7 PCT[7..0] PGT[4..0] PCT[7..0] PGT0 PGT PGT A6 A6 PGT[4..0] PAT[7..0] PAT[7..0] 6 VCC J30 0 C303 00N_6V_X7R KF-E-9-S-N C304 00N_6V_X7R RS3 SPARE C306 00N_6V_X7R JS309 R3 33R JP U30 A0 3 A 4 A 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 A9 0 A0 A 9 A 30 A3 3 A4 3 A5 A6 5 8 CE OE WE I/O0 I/O I/O I/O3 I/O4 I/O5 I/O6 I/O VCC 8 VCC C30 00N_6V_X7R R30 0K R30 0K R303 0K R304 0K R305 0K R306 0K R307 0K R308 0K R309 R30 8Kx8 SRAM 0K 0K R3 SRAMEN SRAMEN U303 C+ V+ C- 3 T R 0 T 9 R V- C+ 4 XC30 C N_6V_X7R 4 SW30 TOSC 3kHz TOSC TOSC 3 PGT3 6 J30 TOSC 5 TOSC RXD TXD 4 PGT4 CTS 3 4 RTS 7 C308 0P_50V_NP0 RAM HIGH ADDRESS 0K R33 0K C- 5 MAX33ECAE PGT[4..0] PGT[4..0] C307 00N_6V_X7R 6-4 AVR STK50 User Guide

28 Complete Schematics Figure 6-4. Assembly Drawing, of AVR STK50 User Guide 6-5

29 Complete Schematics 6-6 AVR STK50 User Guide

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