A Framework to Model Self-Adaptive Computing Systems

Size: px
Start display at page:

Download "A Framework to Model Self-Adaptive Computing Systems"

Transcription

1 A Framework to Model Self-Adaptive Computing Systems AHS di Torino - Italy June 25, 2013 Cristiana BOLCHINI Matteo CARMINATI Antonio MIELE Elisa QUINTARELLI mcarminati@elet.polimi.it

2 Motivations Context-awareness and self-adaptiveness are growing trends in designing new computing systems But rigorous definitions and formal models are usually neglected or overlooked This becomes a limitation when the number of elements determining the context grows: the quest for a flexible and powerful support arises 2

3 Context Lot of attention from SE and DB research areas context: information that can be used to characterize situation of an entity [1] context-aware system: uses context to provide relevant information and/or services to the user, where relevancy depends on the user s task [1] [1] A.K. Dey and G.D. Abowd - Towards a better understanding of context and context-awareness - Workshop on the What, Who, Where, When, and How of Context-Awareness,

4 Context acquisition context [2] representation usage interpretation reasoning [2] M. Baldauf, S. Dustdar, and F. Rosenberg - A survey on context-aware systems - International Journal Ad Hoc and Ubiquitous Computing (IJAHUC),

5 Context acquisition modeling context [2] representation usage interpretation reasoning [2] M. Baldauf, S. Dustdar, and F. Rosenberg - A survey on context-aware systems - International Journal Ad Hoc and Ubiquitous Computing (IJAHUC),

6 Context user physical [3] context [2] acquisition representation modeling computing usage interpretation reasoning [2] M. Baldauf, S. Dustdar, and F. Rosenberg - A survey on context-aware systems - International Journal Ad Hoc and Ubiquitous Computing (IJAHUC), [3] B. Schilit, N. Adams, and R. Want - Context-aware computing applications - Workshop on Mobile Computing Systems and Applications (HotMobile),

7 Context user physical [3] context [2] acquisition representation modeling computing usage interpretation reasoning [2] M. Baldauf, S. Dustdar, and F. Rosenberg - A survey on context-aware systems - International Journal Ad Hoc and Ubiquitous Computing (IJAHUC), [3] B. Schilit, N. Adams, and R. Want - Context-aware computing applications - Workshop on Mobile Computing Systems and Applications (HotMobile),

8 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

9 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

10 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

11 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

12 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

13 Self-Adaptiveness [4] Sensor Sensor Sensor Private Self-Awareness Engine State & Context Learnt Model(s) Public Self-Awareness Engine Environment Monitor/ Controller Actuator Goals Values Objectives Constraints Self-Expression Engine Actuator External Actions [4] T. Becker, A. Agne, P. R. Lewis, R. Bahsoon, F. Faniyi, L. Esterle, A. Keller, A. Chandra, A. R. Jensenius, and S. C. Stilkerich - EPiCS: Engineering Proprioception in Computing Systems - International Conference on Computational Science and Engineering (CSE),

14 Work Goals The definition of a model for self-adaptive Computing Systems to express: the elements affecting their behavior, including existing relations and constraints the conditions that trigger adaptation The validation of the completeness and flexibility of the model, by applying it to self-adaptive systems from literature 14

15 What is relevant? Self-Adaptive Computing Systems (SACS) 15

16 What is relevant? Self-Adaptive Computing Systems (SACS) elements ODA control loop O: high-level quantities D: aspects to reason on A: knobs and strategies 16

17 What is relevant? Self-Adaptive Computing Systems (SACS) elements ODA control loop O: high-level quantities D: aspects to reason on relations Both direct and indirect effects of planned actions A: knobs and strategies 17

18 Context Dimensions Main Dimensions goals requirements observations 18

19 Context Dimensions Main Dimensions goals requirements observations Collected Data Dimensions raw data measures metrics 19

20 Context Dimensions Main Dimensions goals requirements observations Collected Data Dimensions raw data measures metrics Self- Expression Dimensions control actions methods 20

21 Context Meta-Model goals control actions methods requirements metrics measures raw data observations driving dimensions 21

22 Context Meta-Model goals control actions methods requirements metrics measures raw data observations driving dimensions may not exist in some contexts 22

23 Context Meta-Model segments represent relations between dimensions goals control actions methods requirements metrics measures raw data observations driving dimensions may not exist in some contexts 23

24 Context Meta-Model OR relation segments represent relations between dimensions AND relation goals control actions methods requirements metrics measures raw data observations driving dimensions may not exist in some contexts 24

25 Context Meta-Model OR relation segments represent relations between dimensions AND relation goals control actions methods requirements metrics measures raw data observations driving dimensions may not exist in some contexts New dimensions can be added by simply connecting them to the existing ones through (possibly new) relations 25

26 Context Model driving dim. secondary dim. Each dimension has a domain of values whose selection will define the specific context model control actions methods goals/requirements/observations metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache Idle Cycle Injection Core Frequency... SIMO controller & ARMA model Controlled Task Scheduling Round Robin FIFO Constant Value... Performance Resource Exploitation Power Temperature Reliability Area Manufacturability... Weighted IPC Harmonic Speed-Up Utilization Mean Time To Failure... Instructions per Cycle (IPC) Average Resource Usage Execution Time Transactions per Second... Cores Temperature Screen Brightness Acceleration Execution Time Memory Usage CPU Utilization Cache Hits... 26

27 Context Model For a given SACS, the context model is defined as a set of <dimension, value> pairs where each is a dimension and is its value 27

28 Context Model For a given SACS, the context model is defined as a set of <dimension, value> pairs where each is a dimension and is its value satisfying the following constraints 28

29 METE [4] control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App [4] A. Sharifi, S. Srikantaiah, A. K. Mishra, M. Kandemir, and C. R. Chita - METE: meeting end-to-end QoS in multicores through system-wide resource management - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),

30 METE [4] control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App goals Exploitation requirements Performance [4] A. Sharifi, S. Srikantaiah, A. K. Mishra, M. Kandemir, and C. R. Chita - METE: meeting end-to-end QoS in multicores through system-wide resource management - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),

31 METE [4] control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache metrics measures raw data #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App [4] A. Sharifi, S. Srikantaiah, A. K. Mishra, M. Kandemir, and C. R. Chita - METE: meeting end-to-end QoS in multicores through system-wide resource management - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),

32 METE [4] control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App control actions #Allocated Cores Off-Chip Memory Bandwidth Shared Cache methods SIMO controller & ARMA model [4] A. Sharifi, S. Srikantaiah, A. K. Mishra, M. Kandemir, and C. R. Chita - METE: meeting end-to-end QoS in multicores through system-wide resource management - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),

33 METE [4] control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App [4] A. Sharifi, S. Srikantaiah, A. K. Mishra, M. Kandemir, and C. R. Chita - METE: meeting end-to-end QoS in multicores through system-wide resource management - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),

34 Re-cap Context Meta-Model control actions methods goals requirements observations metrics measures raw data Context Model control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App Context Instance control actions methods goals requirements metrics measures raw data #Allocated 25 Cores Off-Chip 325Memory Bandwidth Shared 0.8 Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic 1.4 Speed-Up 15 Utilization Instructions 58.1 per Cycle (IPC) Allocated 6 Cores Off-Chip 15 Memory Bandwidth Shared 4 Cache #Executed Instructions Execution 300 Time #Allocated 2 Cores/App Off-Chip 680.2Memory Bandwidth/App Shared 0.8Cache /App 34

35 Why do we need it? Context representation: Help the computing system designer in understanding which resources are needed to be able to pursue its goal control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App 35

36 Why do we need it? Context representation: Help the computing system designer in understanding which resources are needed to be able to pursue its goal control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache sensors #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App 36

37 Why do we need it? Context representation: Help the computing system designer in understanding which resources are needed to be able to pursue its goal control actions methods goals requirements metrics measures raw data #Allocated Cores Off-Chip Memory Bandwidth Shared Cache SIMO controller & ARMA model actuators Exploitation Performance Weighted IPC Harmonic Speed-Up Utilization Instructions per Cycle (IPC) Allocated Cores Off-Chip Memory Bandwidth Shared Cache #Executed Instructions Execution Time #Allocated Cores/App Off-Chip Memory Bandwidth/App Shared Cache /App 37

38 Why do we need it? Context representation: Help the computing system designer in understanding which resources are needed to be able to pursue its goal Document the system to provide a common and systematic classification of self-adaptive computing systems Describe, at run-time, the current context of the considered system 38

39 What can be done? Context usage: Development of a framework able to generate, in a template fashion, the main control loop of the selfadaptive engine, according to the driving dimensions value Automate the testing phase, by creating optimal test sets to stimulate all possible system configurations Exploit the knowledge contained in our formalization to keep track of the context evolution, to deal with unforeseen contexts 39

40 Questions? Cristiana BOLCHINI Matteo CARMINATI Antonio MIELE Elisa QUINTARELLI 40

41 Questions? Cristiana BOLCHINI Matteo CARMINATI Antonio MIELE Elisa QUINTARELLI 41

42 Into The Wild [5] control actions methods goals metrics measures raw data Cores Frequency Display Brightness On Demand DFS Gradual Reduction Exploitation Power Utilization Power Model Average Resource Usage #Used Resources CPU Utilization System Up-Time Screen Brightness Connections Utilization SD Card Accesses [5] A. Shye, B. Scholbrock, and G. G. Memik - Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures - International Symposium on Microarchitecture (MICRO),

43 Into The Wild [5] control actions methods goals metrics measures raw data Cores Frequency Display Brightness On Demand DFS Gradual Reduction Exploitation Power Utilization Power Model Average Resource Usage #Used Resources CPU Utilization System Up-Time Screen Brightness Connections Utilization SD Card Accesses [5] A. Shye, B. Scholbrock, and G. G. Memik - Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures - International Symposium on Microarchitecture (MICRO), Metronome [6] control actions methods goals requirement metrics measures raw data Virtual Run-Time Scheduling Policy Exploitation Performance Application Progress Heartrate Heartbeat Execution Time [6] F. Sironi, D. B. Bartolini, S. Campanoni, F. Cancare, H. Hoffmann, D. Sciuto, and M. D. Santambrogio - Metronome: operating system level performance management via self-adaptive computing - Design Automation Conference (DAC),

A Framework to Model Self-Adaptive Computing Systems

A Framework to Model Self-Adaptive Computing Systems A Framework to Model Self-Adaptive Computing Systems Cristiana Bolchini, Matteo Carminati, Antonio Miele, Elisa Quintarelli Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano P.zza

More information

METE: Meeting End-to-End QoS in Multicores through System-Wide Resource Management

METE: Meeting End-to-End QoS in Multicores through System-Wide Resource Management METE: Meeting End-to-End QoS in Multicores through System-Wide Resource Management Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut Kandemir and Chita R. Das Department of CSE The Pennsylvania

More information

Context-Aware Systems. Michael Maynord Feb. 24, 2014

Context-Aware Systems. Michael Maynord Feb. 24, 2014 Context-Aware Systems Michael Maynord Feb. 24, 2014 The precise definition of 'context' is contentious. Here we will be using 'context' as any information that can be used to characterize the situation

More information

The Pennsylvania State University The Graduate School ADDRESSING POWER, PERFORMANCE AND END-TO-END QOS IN EMERGING MULTICORES THROUGH SYSTEM-WIDE

The Pennsylvania State University The Graduate School ADDRESSING POWER, PERFORMANCE AND END-TO-END QOS IN EMERGING MULTICORES THROUGH SYSTEM-WIDE The Pennsylvania State University The Graduate School ADDRESSING POWER, PERFORMANCE AND END-TO-END QOS IN EMERGING MULTICORES THROUGH SYSTEM-WIDE RESOURCE MANAGEMENT A Dissertation in Computer Science

More information

Self-Aware Adaptation in FPGA-based Systems

Self-Aware Adaptation in FPGA-based Systems DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE Self-Aware Adaptation in FPGA-based Systems IEEE FPL 2010 Filippo Siorni: filippo.sironi@dresd.org Marco Triverio: marco.triverio@dresd.org Martina Maggio: mmaggio@mit.edu

More information

Autonomic Thread Scaling Library for QoS Management

Autonomic Thread Scaling Library for QoS Management Autonomic Thread Scaling Library for QoS Management Gianluca C. Durelli Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria gianlucacarlo.durelli@polimi.it Marco D. Santambrogio

More information

Feature Extraction in Wireless Personal and Local Area Networks

Feature Extraction in Wireless Personal and Local Area Networks Feature Extraction in Wireless Personal and Local Area Networks 29. October 2003, Singapore Institut für Praktische Informatik Johannes Kepler Universität Linz, Austria rene@soft.uni-linz.ac.at < 1 > Content

More information

Involving tourism domain experts in the development of context-aware mobile services

Involving tourism domain experts in the development of context-aware mobile services Involving tourism domain experts in the development of context-aware mobile services David Martín a, Diego López de Ipiña b, Carlos Lamsfus a and Aurkene Alzua a a Human Mobility and Technology CICtourGUNE

More information

A Comparison of Capacity Management Schemes for Shared CMP Caches

A Comparison of Capacity Management Schemes for Shared CMP Caches A Comparison of Capacity Management Schemes for Shared CMP Caches Carole-Jean Wu and Margaret Martonosi Princeton University 7 th Annual WDDD 6/22/28 Motivation P P1 P1 Pn L1 L1 L1 L1 Last Level On-Chip

More information

Contextion: A Framework for Developing Context-Aware Mobile Applications

Contextion: A Framework for Developing Context-Aware Mobile Applications Contextion: A Framework for Developing Context-Aware Mobile Applications Elizabeth Williams, Jeff Gray Department of Computer Science, University of Alabama eawilliams2@crimson.ua.edu, gray@cs.ua.edu Abstract

More information

Recognizing and Predicting Context by Learning from User Behavior

Recognizing and Predicting Context by Learning from User Behavior Recognizing and Predicting Context by Learning from User Behavior 15. September 2003, Jakarta Institut für Praktische Informatik Johannes Kepler Universität Linz, Austria rene@soft.uni-linz.ac.at < 1 >

More information

Efficient Evaluation and Management of Temperature and Reliability for Multiprocessor Systems

Efficient Evaluation and Management of Temperature and Reliability for Multiprocessor Systems Efficient Evaluation and Management of Temperature and Reliability for Multiprocessor Systems Ayse K. Coskun Electrical and Computer Engineering Department Boston University http://people.bu.edu/acoskun

More information

Multithreading: Exploiting Thread-Level Parallelism within a Processor

Multithreading: Exploiting Thread-Level Parallelism within a Processor Multithreading: Exploiting Thread-Level Parallelism within a Processor Instruction-Level Parallelism (ILP): What we ve seen so far Wrap-up on multiple issue machines Beyond ILP Multithreading Advanced

More information

Orchestrated Scheduling and Prefetching for GPGPUs. Adwait Jog, Onur Kayiran, Asit Mishra, Mahmut Kandemir, Onur Mutlu, Ravi Iyer, Chita Das

Orchestrated Scheduling and Prefetching for GPGPUs. Adwait Jog, Onur Kayiran, Asit Mishra, Mahmut Kandemir, Onur Mutlu, Ravi Iyer, Chita Das Orchestrated Scheduling and Prefetching for GPGPUs Adwait Jog, Onur Kayiran, Asit Mishra, Mahmut Kandemir, Onur Mutlu, Ravi Iyer, Chita Das Parallelize your code! Launch more threads! Multi- threading

More information

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip ASP-DAC 2010 20 Jan 2010 Session 6C Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip Jonas Diemer, Rolf Ernst TU Braunschweig, Germany diemer@ida.ing.tu-bs.de Michael Kauschke Intel,

More information

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. Yoongu Kim Michael Papamichael Onur Mutlu Mor Harchol-Balter

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. Yoongu Kim Michael Papamichael Onur Mutlu Mor Harchol-Balter Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior Yoongu Kim Michael Papamichael Onur Mutlu Mor Harchol-Balter Motivation Memory is a shared resource Core Core Core Core

More information

A Case for Core-Assisted Bottleneck Acceleration in GPUs Enabling Flexible Data Compression with Assist Warps

A Case for Core-Assisted Bottleneck Acceleration in GPUs Enabling Flexible Data Compression with Assist Warps A Case for Core-Assisted Bottleneck Acceleration in GPUs Enabling Flexible Data Compression with Assist Warps Nandita Vijaykumar Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarangnirun,

More information

Computer Hardware Requirements for Real-Time Applications

Computer Hardware Requirements for Real-Time Applications Lecture (4) Computer Hardware Requirements for Real-Time Applications Prof. Kasim M. Al-Aubidy Computer Engineering Department Philadelphia University Real-Time Systems, Prof. Kasim Al-Aubidy 1 Lecture

More information

Managing and mining (streaming) sensor data

Managing and mining (streaming) sensor data Petr Čížek Artificial Intelligence Center Czech Technical University in Prague November 3, 2016 Petr Čížek VPD 1 / 1 Stream data mining / stream data querying Problem definition Data can not be stored

More information

HSA foundation! Advanced Topics on Heterogeneous System Architectures. Politecnico di Milano! Seminar Room A. Alario! 23 November, 2015!

HSA foundation! Advanced Topics on Heterogeneous System Architectures. Politecnico di Milano! Seminar Room A. Alario! 23 November, 2015! Advanced Topics on Heterogeneous System Architectures HSA foundation! Politecnico di Milano! Seminar Room A. Alario! 23 November, 2015! Antonio R. Miele! Marco D. Santambrogio! Politecnico di Milano! 2

More information

Caching video contents in IPTV systems with hierarchical architecture

Caching video contents in IPTV systems with hierarchical architecture Caching video contents in IPTV systems with hierarchical architecture Lydia Chen 1, Michela Meo 2 and Alessandra Scicchitano 1 1. IBM Zurich Research Lab email: {yic,als}@zurich.ibm.com 2. Politecnico

More information

Evaluating Orthogonality between Application Auto tuning and Run Time Resource Management for Adaptive OpenCL Applications

Evaluating Orthogonality between Application Auto tuning and Run Time Resource Management for Adaptive OpenCL Applications Evaluating Orthogonality between Application Auto tuning and Run Time Resource Management for Adaptive OpenCL Applications Edoardo Paone, Davide Gadioli, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano

More information

GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs

GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs Authors: Jos e L. Abell an, Juan Fern andez and Manuel E. Acacio Presenter: Guoliang Liu Outline Introduction Motivation Background

More information

GENERATING HIGH LEVEL CONTEXT FROM SENSOR DATA FOR MOBILE APPLICATIONS

GENERATING HIGH LEVEL CONTEXT FROM SENSOR DATA FOR MOBILE APPLICATIONS GENERATING HIGH LEVEL CONTEXT FROM SENSOR DATA FOR MOBILE APPLICATIONS Wolfgang Woerndl 1, Christian Schueller 2, Thomas Rottach 1,2 1 Technische Universitaet Muenchen, Institut fuer Informatik Boltzmannstr.

More information

Context Aware Computing

Context Aware Computing CPET 565/CPET 499 Mobile Computing Systems Context Aware Computing Lecture 7 Paul I-Hai Lin, Professor Electrical and Computer Engineering Technology Purdue University Fort Wayne Campus 1 Context-Aware

More information

Building the Web of Things: frameworks and tools for fast prototyping Web-based physical mashups

Building the Web of Things: frameworks and tools for fast prototyping Web-based physical mashups Building the Web of Things: frameworks and tools for fast prototyping Web-based physical mashups Vlad Trifa & Dominique Guinard - ETH Zurich Context Embedded computers, sensors, actuators are omnipresent

More information

ADAPTIVE HANDLING OF 3V S OF BIG DATA TO IMPROVE EFFICIENCY USING HETEROGENEOUS CLUSTERS

ADAPTIVE HANDLING OF 3V S OF BIG DATA TO IMPROVE EFFICIENCY USING HETEROGENEOUS CLUSTERS INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 ADAPTIVE HANDLING OF 3V S OF BIG DATA TO IMPROVE EFFICIENCY USING HETEROGENEOUS CLUSTERS Radhakrishnan R 1, Karthik

More information

Web Application Testing in Fifteen Years of WSE

Web Application Testing in Fifteen Years of WSE Web Application Testing in Fifteen Years of WSE Anna Rita Fasolino Domenico Amalfitano Porfirio Tramontana Dipartimento di Ingegneria Elettrica e Tecnologie dell Informazione University of Naples Federico

More information

Exploiting Core Criticality for Enhanced GPU Performance

Exploiting Core Criticality for Enhanced GPU Performance Exploiting Core Criticality for Enhanced GPU Performance Adwait Jog, Onur Kayıran, Ashutosh Pattnaik, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, Chita R. Das. SIGMETRICS 16 Era of Throughput Architectures

More information

COMPARISON OF ENERGY EFFICIENT DATA TRANSMISSION APPROACHES FOR FLAT WIRELESS SENSOR NETWORKS

COMPARISON OF ENERGY EFFICIENT DATA TRANSMISSION APPROACHES FOR FLAT WIRELESS SENSOR NETWORKS COMPARISON OF ENERGY EFFICIENT DATA TRANSMISSION APPROACHES FOR FLAT WIRELESS SENSOR NETWORKS Saraswati Mishra 1 and Prabhjot Kaur 2 Department of Electrical, Electronics and Communication Engineering,

More information

low Energy COnsumption NETworks

low Energy COnsumption NETworks low Energy COnsumption NETworks (ECONET) Smart power management for fixed network devices ETSI Workshop on Energy Efficiency Genova 21st June 2012 The Project Motivations and Focus x 10 Static energy efficiency

More information

Vertical Profiling: Understanding the Behavior of Object-Oriented Applications

Vertical Profiling: Understanding the Behavior of Object-Oriented Applications Vertical Profiling: Understanding the Behavior of Object-Oriented Applications Matthias Hauswirth, Amer Diwan University of Colorado at Boulder Peter F. Sweeney, Michael Hind IBM Thomas J. Watson Research

More information

NESL. CAreDroid: Adaptation Framework for Android Context-Aware Applications. Salma Elmalaki Lucas Wanner Mani Srivastava

NESL. CAreDroid: Adaptation Framework for Android Context-Aware Applications. Salma Elmalaki Lucas Wanner Mani Srivastava CAreDroid: Adaptation Framework for Android Context-Aware Applications Salma Elmalaki Lucas Wanner Mani Srivastava 1 Isolated Disconnected Unaware Photo Courtesy: Student Portal 2 Computing From Isolation

More information

A GROUP-BASED METHOD FOR CONTEXT-AWARE SERVICE DISCOVERY IN PERVASIVE COMPUTING ENVIRONMENT

A GROUP-BASED METHOD FOR CONTEXT-AWARE SERVICE DISCOVERY IN PERVASIVE COMPUTING ENVIRONMENT A GROUP-BASED METHOD FOR CONTEXT-AWARE SERVICE DISCOVERY IN PERVASIVE COMPUTING ENVIRONMENT ABSTRACT Marzieh Ilka 1, Mahdi Niamanesh 2, and Ahmad Faraahi 3 1 Payam Noor University, Tehran, Iran marzieh.ilka@gmail.com

More information

No Tradeoff Low Latency + High Efficiency

No Tradeoff Low Latency + High Efficiency No Tradeoff Low Latency + High Efficiency Christos Kozyrakis http://mast.stanford.edu Latency-critical Applications A growing class of online workloads Search, social networking, software-as-service (SaaS),

More information

Applying March Tests to K-Way Set-Associative Cache Memories

Applying March Tests to K-Way Set-Associative Cache Memories 13th European Test Symposium Applying March Tests to K-Way Set-Associative Cache Memories Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino Politecnico di Torino, Dep. of Control and Computer

More information

MOBILE COMPUTING 2/11/18. System Structure. Context as Implicit Input. explicit input. explicit output. explicit input.

MOBILE COMPUTING 2/11/18. System Structure. Context as Implicit Input. explicit input. explicit output. explicit input. MOBILE COMPUTING CSE 40814/60814 Spring 2018 System Structure explicit input explicit output Context as Implicit Input explicit input explicit output Context: state of the user state of the physical environment

More information

HSA Foundation! Advanced Topics on Heterogeneous System Architectures. Politecnico di Milano! Seminar Room (Bld 20)! 15 December, 2017!

HSA Foundation! Advanced Topics on Heterogeneous System Architectures. Politecnico di Milano! Seminar Room (Bld 20)! 15 December, 2017! Advanced Topics on Heterogeneous System Architectures HSA Foundation! Politecnico di Milano! Seminar Room (Bld 20)! 15 December, 2017! Antonio R. Miele! Marco D. Santambrogio! Politecnico di Milano! 2

More information

Einführung in die Erweiterte Realität

Einführung in die Erweiterte Realität Einführung in die Erweiterte Realität - 7. Context Toolkit - Gudrun Klinker Dec. 2, 2003 Literature Anind K. Dey, Gregory D. Abowd, and Danieal Salber, A Conceptual Framework and a Toolkit for Supporting

More information

Memory Hierarchy. Slides contents from:

Memory Hierarchy. Slides contents from: Memory Hierarchy Slides contents from: Hennessy & Patterson, 5ed Appendix B and Chapter 2 David Wentzlaff, ELE 475 Computer Architecture MJT, High Performance Computing, NPTEL Memory Performance Gap Memory

More information

The Effect of Temperature on Amdahl Law in 3D Multicore Era

The Effect of Temperature on Amdahl Law in 3D Multicore Era The Effect of Temperature on Amdahl Law in 3D Multicore Era L Yavits, A Morad, R Ginosar Abstract This work studies the influence of temperature on performance and scalability of 3D Chip Multiprocessors

More information

MOBILE COMPUTING 2/14/17. System Structure. Context as Implicit Input. explicit input. explicit output. explicit input.

MOBILE COMPUTING 2/14/17. System Structure. Context as Implicit Input. explicit input. explicit output. explicit input. MOBILE COMPUTING CSE 40814/60814 Spring 2017 System Structure explicit input explicit output Context as Implicit Input explicit input explicit output Context: state of the user state of the physical environment

More information

A Survey of Context-Aware Mobile Computing Research

A Survey of Context-Aware Mobile Computing Research A Survey of Context-Aware Mobile Computing Research Guanling Chen and David Kotz 2005.11. 14 Cho Jaekyu jkcho@mmlab.snu.ac.kr Contents 1 2 3 4 5 6 7 8 Introduction Definition of Context Context-Aware Computing

More information

Understanding GPGPU Vector Register File Usage

Understanding GPGPU Vector Register File Usage Understanding GPGPU Vector Register File Usage Mark Wyse AMD Research, Advanced Micro Devices, Inc. Paul G. Allen School of Computer Science & Engineering, University of Washington AGENDA GPU Architecture

More information

Analyzing Memory Access Patterns and Optimizing Through Spatial Memory Streaming. Ogün HEPER CmpE 511 Computer Architecture December 24th, 2009

Analyzing Memory Access Patterns and Optimizing Through Spatial Memory Streaming. Ogün HEPER CmpE 511 Computer Architecture December 24th, 2009 Analyzing Memory Access Patterns and Optimizing Through Spatial Memory Streaming Ogün HEPER CmpE 511 Computer Architecture December 24th, 2009 Agenda Introduction Memory Hierarchy Design CPU Speed vs.

More information

The Green Switch: Designing for Sustainability in Mobile Computing. Riikka Puustinen & Galit Zadok SustainIT February 2010

The Green Switch: Designing for Sustainability in Mobile Computing. Riikka Puustinen & Galit Zadok SustainIT February 2010 The Green Switch: Designing for Sustainability in Mobile Computing Riikka Puustinen & Galit Zadok SustainIT 10 22 February 2010 Mobile & Sustainability Mobile & Sustainability 3 trends converging User

More information

Measuring the Capability of Smartphones for Executing Context Algorithms

Measuring the Capability of Smartphones for Executing Context Algorithms Maximilian Eibl, Martin Gaedke. (Hrsg.): INFORMATIK 2017, Lecture Lecture Notes in Notes Informatics in Informatics (LNI), Gesellschaft (LNI), Gesellschaft für Informatik, für Informatik, Bonn 2017 Bonn

More information

Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service

Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service * Kshitij Sudan* Sadagopan Srinivasan Rajeev Balasubramonian* Ravi Iyer Executive Summary Goal: Co-schedule N applications

More information

Mobile Sensing Towards Context Awareness

Mobile Sensing Towards Context Awareness Mobile Sensing Towards Context Awareness Susana Bulas Cruz Instituto de Telecomunicações Faculdade de Engenharia da Universidade do Porto Rua Dr. Roberto Frias, s/n 4200-465 Porto, Portugal susana.bulas.cruz@fe.up.pt

More information

Efficient Hardware Acceleration on SoC- FPGA using OpenCL

Efficient Hardware Acceleration on SoC- FPGA using OpenCL Efficient Hardware Acceleration on SoC- FPGA using OpenCL Advisor : Dr. Benjamin Carrion Schafer Susmitha Gogineni 30 th August 17 Presentation Overview 1.Objective & Motivation 2.Configurable SoC -FPGA

More information

SAVE: Towards efficient resource management in heterogeneous system architectures

SAVE: Towards efficient resource management in heterogeneous system architectures SAVE: Towards efficient resource management in heterogeneous system architectures G. Durelli 1, M. Coppola 2, K. Djafarian 3, G. Kornaros 4, A. Miele 1, M. Paolino 5, O. Pell 6, C. Plessl 7, M.D. Santambrogio

More information

Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems

Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems Roland Dobai Faculty of Information Technology Brno University of Technology Brno, Czech

More information

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design Zhi-Liang Qian and Chi-Ying Tsui VLSI Research Laboratory Department of Electronic and Computer Engineering The Hong Kong

More information

Network-Aware Resource Allocation in Distributed Clouds

Network-Aware Resource Allocation in Distributed Clouds Dissertation Research Summary Thesis Advisor: Asst. Prof. Dr. Tolga Ovatman Istanbul Technical University Department of Computer Engineering E-mail: aralat@itu.edu.tr April 4, 2016 Short Bio Research and

More information

BREAKING THE MEMORY WALL

BREAKING THE MEMORY WALL BREAKING THE MEMORY WALL CS433 Fall 2015 Dimitrios Skarlatos OUTLINE Introduction Current Trends in Computer Architecture 3D Die Stacking The memory Wall Conclusion INTRODUCTION Ideal Scaling of power

More information

REAL TIME OPERATING SYSTEMS. Lesson-15:

REAL TIME OPERATING SYSTEMS. Lesson-15: REAL TIME OPERATING SYSTEMS Lesson-15: Power Optimization 1 1. Memory Optimization 2 Power Optimization Saving power and energy requirement for a given set of codes, while finishing instructions in the

More information

Basics of Performance Engineering

Basics of Performance Engineering ERLANGEN REGIONAL COMPUTING CENTER Basics of Performance Engineering J. Treibig HiPerCH 3, 23./24.03.2015 Why hardware should not be exposed Such an approach is not portable Hardware issues frequently

More information

Deterministic Memory Abstraction and Supporting Multicore System Architecture

Deterministic Memory Abstraction and Supporting Multicore System Architecture Deterministic Memory Abstraction and Supporting Multicore System Architecture Farzad Farshchi $, Prathap Kumar Valsan^, Renato Mancuso *, Heechul Yun $ $ University of Kansas, ^ Intel, * Boston University

More information

A Transformation-Based Model of Evolutionary Architecting for Embedded System Product Lines

A Transformation-Based Model of Evolutionary Architecting for Embedded System Product Lines A Transformation-Based Model of Evolutionary Architecting for Embedded System Product Lines Jakob Axelsson School of Innovation, Design and Engineering, Mälardalen University, SE-721 23 Västerås, Sweden

More information

A Heterogeneous Multiple Network-On-Chip Design: An Application-Aware Approach

A Heterogeneous Multiple Network-On-Chip Design: An Application-Aware Approach A Heterogeneous Multiple Network-On-Chip Design: An Application-Aware Approach Asit K. Mishra Onur Mutlu Chita R. Das Executive summary Problem: Current day NoC designs are agnostic to application requirements

More information

A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks

A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks Sarani Bhattacharya, Chester Rebeiro, Debdeep Mukhopadhyay Indian Institute of Technology Kharagpur HASP 2016

More information

Wireless Sensor Networks

Wireless Sensor Networks Wireless Sensor Networks c.buratti@unibo.it +39 051 20 93147 Office Hours: Tuesday 3 5 pm @ Main Building, second floor Credits: 6 Ouline 1. WS(A)Ns Introduction 2. Applications 3. Energy Efficiency Section

More information

Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review

Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review Bijay K.Paikaray Debabala Swain Dept. of CSE, CUTM Dept. of CSE, CUTM Bhubaneswer, India Bhubaneswer, India

More information

A Two Layered approach to perform Effective Page Replacement

A Two Layered approach to perform Effective Page Replacement IOSR Journal of Engineering (IOSRJEN) e-issn: 2250-3021, p-issn: 2278-8719 Vol. 3, Issue 10 (October. 2013), V5 PP 21-25 A Two Layered approach to perform Effective Page Replacement Khusbu Rohilla 1 (Student

More information

1 Microprocessors 2 Microcontrollers 3 Actuation sensing, process control

1 Microprocessors 2 Microcontrollers 3 Actuation sensing, process control 1 Microprocessors 2 Microcontrollers 3 Actuation sensing, process control 1 Microcontrollers, microprocessors -what are microprocessors, microcontrollers? -what is the difference between them? -what are

More information

Extending the Growing Neural Gas Classifier for Context Recognition

Extending the Growing Neural Gas Classifier for Context Recognition Extending the Classifier for Context Recognition Eurocast 2007, Workshop on Heuristic Problem Solving, Paper #9.24 14. February 2007, 10:30 Rene Mayrhofer Lancaster University, UK Johannes Kepler University

More information

A Proposed Framework for Testing Mobile Cloud Based Applications Using Mobile Testing as a Service (MTaaS)

A Proposed Framework for Testing Mobile Cloud Based Applications Using Mobile Testing as a Service (MTaaS) A Proposed Framework for Mobile Cloud Based Applications Using Mobile as a Service (MTaaS) Engr. Ali Ahmed Computer & Software Engineering Department Bahria University, Karachi Campus Karachi, Pakistan

More information

Generic Profiles V 1.0

Generic Profiles V 1.0 Generic Profiles V 1.0 EnOcean Alliance Inc. San Ramon, CA, USA, June 20, 2013 Executive Summary This is an extract from the document that provides the specification of Generic Profiles. The full specification

More information

Data Sources for Cyber Security Research

Data Sources for Cyber Security Research Data Sources for Cyber Security Research Melissa Turcotte mturcotte@lanl.gov Advanced Research in Cyber Systems, Los Alamos National Laboratory 14 June 2018 Background Advanced Research in Cyber Systems,

More information

CPU Scheduling. Operating Systems (Fall/Winter 2018) Yajin Zhou ( Zhejiang University

CPU Scheduling. Operating Systems (Fall/Winter 2018) Yajin Zhou (  Zhejiang University Operating Systems (Fall/Winter 2018) CPU Scheduling Yajin Zhou (http://yajin.org) Zhejiang University Acknowledgement: some pages are based on the slides from Zhi Wang(fsu). Review Motivation to use threads

More information

Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms

Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms IEEE High Performance Extreme Computing Conference (HPEC), 2017 Broadening the Exploration of the Design Space in Embedded Scalable Platforms Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca

More information

Staged Memory Scheduling

Staged Memory Scheduling Staged Memory Scheduling Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel H. Loh*, Onur Mutlu Carnegie Mellon University, *AMD Research June 12 th 2012 Executive Summary Observation:

More information

Improving multicore memory systems

Improving multicore memory systems 1 Improving multicore memory systems and some thoughts on chip multiprocessor programming NIK MULTICORE TECHNOLOGY WORKSHOP 19. Nov. 2007 Lasse.Natvig@idi.ntnu.no NTNU Computer Architecture Research group

More information

A task migration algorithm for power management on heterogeneous multicore Manman Peng1, a, Wen Luo1, b

A task migration algorithm for power management on heterogeneous multicore Manman Peng1, a, Wen Luo1, b 5th International Conference on Advanced Materials and Computer Science (ICAMCS 2016) A task migration algorithm for power management on heterogeneous multicore Manman Peng1, a, Wen Luo1, b 1 School of

More information

Low Rate DOS Attack Prevention

Low Rate DOS Attack Prevention ISSN No: 2454-9614 Low Rate DOS Attack Prevention S. Kandasamy, N.P. Kaushik *, A. Karthikeyan, S. Aravindh Srira *Corresponding Author: S.Kandasamy E-mail: skandu23@gmail.com Department of Computer Science

More information

Managing GPU Concurrency in Heterogeneous Architectures

Managing GPU Concurrency in Heterogeneous Architectures Managing Concurrency in Heterogeneous Architectures Onur Kayıran, Nachiappan CN, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das Era of Heterogeneous Architectures

More information

Harnessing the Potential of SAP HANA with IBM Power Systems

Harnessing the Potential of SAP HANA with IBM Power Systems Harnessing the Potential of SAP HANA with IBM Power Systems Contents Introduction.... 3 CHAPTER 1: Transition to the Future: SAP HANA and IBM Power Systems... 4 CHAPTER 2: SAP HANA on IBM Power Systems:

More information

A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System

A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System HU WEI, CHEN TIANZHOU, SHI QINGSONG, JIANG NING College of Computer Science Zhejiang University College of Computer

More information

Massimo Poncino Dipartimento di Automatica e Informatica

Massimo Poncino Dipartimento di Automatica e Informatica EDA Group Massimo Poncino Dipartimento di Automatica e Informatica the EDA group Electronic Design Automation 6 Faculty members Enrico Macii Massimo Poncino Alberto Macii Andrea Acquaviva Elisa Ficarra

More information

A METHOD FOR DETECTING FALSE POSITIVE AND FALSE NEGATIVE ATTACKS USING SIMULATION MODELS IN STATISTICAL EN- ROUTE FILTERING BASED WSNS

A METHOD FOR DETECTING FALSE POSITIVE AND FALSE NEGATIVE ATTACKS USING SIMULATION MODELS IN STATISTICAL EN- ROUTE FILTERING BASED WSNS A METHOD FOR DETECTING FALSE POSITIVE AND FALSE NEGATIVE ATTACKS USING SIMULATION MODELS IN STATISTICAL EN- ROUTE FILTERING BASED WSNS Su Man Nam 1 and Tae Ho Cho 2 1 College of Information and Communication

More information

High Performance Computing on MapReduce Programming Framework

High Performance Computing on MapReduce Programming Framework International Journal of Private Cloud Computing Environment and Management Vol. 2, No. 1, (2015), pp. 27-32 http://dx.doi.org/10.21742/ijpccem.2015.2.1.04 High Performance Computing on MapReduce Programming

More information

Basic Low Level Concepts

Basic Low Level Concepts Course Outline Basic Low Level Concepts Case Studies Operation through multiple switches: Topologies & Routing v Direct, indirect, regular, irregular Formal models and analysis for deadlock and livelock

More information

for Exascale Architectures

for Exascale Architectures Toward a Selfaware System for Exascale Architectures Aaron Landwehr, Stéphane Zuckerman, Guang R. Gao University of Delaware 1 Organization Introduction Position, Motivation, Problem Statement Background

More information

CPI IPC. 1 - One At Best 1 - One At best. Multiple issue processors: VLIW (Very Long Instruction Word) Speculative Tomasulo Processor

CPI IPC. 1 - One At Best 1 - One At best. Multiple issue processors: VLIW (Very Long Instruction Word) Speculative Tomasulo Processor Single-Issue Processor (AKA Scalar Processor) CPI IPC 1 - One At Best 1 - One At best 1 From Single-Issue to: AKS Scalar Processors CPI < 1? How? Multiple issue processors: VLIW (Very Long Instruction

More information

Statement of Research for Taliver Heath

Statement of Research for Taliver Heath Statement of Research for Taliver Heath Research on the systems side of Computer Science straddles the line between science and engineering. Both aspects are important, so neither side should be ignored

More information

DNN ENGINE: A 16nm Sub-uJ DNN Inference Accelerator for the Embedded Masses

DNN ENGINE: A 16nm Sub-uJ DNN Inference Accelerator for the Embedded Masses DNN ENGINE: A 16nm Sub-uJ DNN Inference Accelerator for the Embedded Masses Paul N. Whatmough 1,2 S. K. Lee 2, N. Mulholland 2, P. Hansen 2, S. Kodali 3, D. Brooks 2, G.-Y. Wei 2 1 ARM Research, Boston,

More information

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6.

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Cache Memories From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging

More information

Model Driven Development of Context Aware Software Systems

Model Driven Development of Context Aware Software Systems Model Driven Development of Context Aware Software Systems Andrea Sindico University of Rome Tor Vergata Elettronica S.p.A. andrea.sindico@gmail.com Vincenzo Grassi University of Rome Tor Vergata vgrassi@info.uniroma2.it

More information

MEMORY/RESOURCE MANAGEMENT IN MULTICORE SYSTEMS

MEMORY/RESOURCE MANAGEMENT IN MULTICORE SYSTEMS MEMORY/RESOURCE MANAGEMENT IN MULTICORE SYSTEMS INSTRUCTOR: Dr. MUHAMMAD SHAABAN PRESENTED BY: MOHIT SATHAWANE AKSHAY YEMBARWAR WHAT IS MULTICORE SYSTEMS? Multi-core processor architecture means placing

More information

A Simulation-Based Analysis of Scheduling Policies for Multimedia Servers

A Simulation-Based Analysis of Scheduling Policies for Multimedia Servers A Simulation-Based Analysis of Scheduling Policies for Multimedia Servers Nabil J. Sarhan Chita R. Das Department of Computer Science and Engineering The Pennsylvania State University University Park,

More information

Policy-Based Context-Management for Mobile Solutions

Policy-Based Context-Management for Mobile Solutions Policy-Based Context-Management for Mobile Solutions Caroline Funk 1,Björn Schiemann 2 1 Ludwig-Maximilians-Universität München Oettingenstraße 67, 80538 München caroline.funk@nm.ifi.lmu.de 2 Siemens AG,

More information

Do we need a crystal ball for task migration?

Do we need a crystal ball for task migration? Do we need a crystal ball for task migration? Brandon {Myers,Holt} University of Washington bdmyers@cs.washington.edu 1 Large data sets Data 2 Spread data Data.1 Data.2 Data.3 Data.4 Data.0 Data.1 Data.2

More information

ECE 486/586. Computer Architecture. Lecture # 2

ECE 486/586. Computer Architecture. Lecture # 2 ECE 486/586 Computer Architecture Lecture # 2 Spring 2015 Portland State University Recap of Last Lecture Old view of computer architecture: Instruction Set Architecture (ISA) design Real computer architecture:

More information

Partitioning Deep Cache Hierarchies in Software for Predictable Performance

Partitioning Deep Cache Hierarchies in Software for Predictable Performance Partitioning Deep Cache Hierarchies in Software for Predictable Performance BY ALBERTO SCOLARI B.S., Politecnico di Milano, Milan, Italy, September 2011 THESIS Submitted as partial fulfillment of the requirements

More information

Afterwards, you will connect the scene function to the group addresses from the existing project.

Afterwards, you will connect the scene function to the group addresses from the existing project. Introduction Introduction: The scene function is supported in the ETS with the parameters of the push button sensors and actuators. In doing so, the device functions act together with the abilities of

More information

Shared Cache Aware Task Mapping for WCRT Minimization

Shared Cache Aware Task Mapping for WCRT Minimization Shared Cache Aware Task Mapping for WCRT Minimization Huping Ding & Tulika Mitra School of Computing, National University of Singapore Yun Liang Center for Energy-efficient Computing and Applications,

More information

Support for Moving Users through Thin Clients: Hype or Future?

Support for Moving Users through Thin Clients: Hype or Future? Support for Moving Users through Thin Clients: Hype or Future? Speaker: P. Simoens IBCN INTEC, Ghent University Joint work of M. Strobbe, P. Simoens, L. Deboosere, D. De Winter, F. Van Quickenborne, F.

More information

Computer Systems Architecture

Computer Systems Architecture Computer Systems Architecture Lecture 12 Mahadevan Gomathisankaran March 4, 2010 03/04/2010 Lecture 12 CSCE 4610/5610 1 Discussion: Assignment 2 03/04/2010 Lecture 12 CSCE 4610/5610 2 Increasing Fetch

More information

Hardware-Software Codesign. 1. Introduction

Hardware-Software Codesign. 1. Introduction Hardware-Software Codesign 1. Introduction Lothar Thiele 1-1 Contents What is an Embedded System? Levels of Abstraction in Electronic System Design Typical Design Flow of Hardware-Software Systems 1-2

More information

Multi-batch Function (/BT)

Multi-batch Function (/BT) User s Manual Model GX10/GX20/GP10/GP20/10 Multi-batch Function (/BT) User s Manual IM 04L51B01-03EN 3rd Edition Introduction Thank you for purchasing the SMARTDAC+ GX10/GX20/GP10/GP20 (hereafter referred

More information