32-bit Embedded Core Peripheral. Advanced Interrupt Controller (AIC)

Transcription

1 Features Compatible with an Embedded ARM7TDMI Processor 8-level Priority From 2 to 32 Interrupt Sources Individually Maskable and Vectored Substantially Reduces the Software and Real-time Overhead in Handling Internal and External Interrupts Full Scan Testable (up to 99%) Can be Directly Connected to the Atmel Implementation of the AMBA Peripheral Bus (APB) Description The advanced interrupt controller () is an 8-level priority, individually maskable, vectored interrupt controller. It can substantially reduce the software and real-time overhead in handling internal and external interrupts. This peripheral can be used with any 32-bit microcontroller core if the timing diagram shown on page 8 is respected. The interrupt handling must be performed as described on page 6, using the corresponding assembler instructions for the 32-bit core used. When using an ARM7TDMI as the core, the Atmel bridge must be used to provide the correct bus interface to the. The interrupt controller can be directly connected to the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an ARM7TDMI processor, or the equivalent inputs of another 32-bit microcontroller core. The processor s nfiq line can only be asserted by the external fast interrupt request input: FIQ. The nirq line can be asserted by all the other interrupt sources. An 8-level priority encoder allows the customer to define the priority between the different nirq interrupt sources. Internal interrupt sources are programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive or negative edge triggered or high or low level sensitive. This document describes the in a specific configuration that is identical to the implemented in the AT91M40400 as specified below: One FIQ is connected on the interrupt line[0]. Eight internal interrupt sources are connected on interrupt lines[8:1]. Three external interrupt sources are connected on interrupt lines[11:9] but are mapped on interrupts[18:16]. The interrupt sources are listed in Table 2 and the programmable registers in Table 3. The register interaction is shown in Figure bit Embedded Core Peripheral Advanced Interrupt Controller () Rev. 1246D 12/00 1

2 Figure 1. Pin Configuration nreset_r Functional nreset_f clock periph_address[13:0] periph_data_in[31:0] periph_write nfiq nirq nint periph_data_out[31:0] Functional pstb_rising periph_strobe periph_select interrupt_lines[(n-1):0] (1) Debug debug_int_mask debug_mode Test Scan scan_test_mode test_se test_so[n chain :1] (2) Test Scan test_si[n chain :1] (2) Notes: 1. N = Number of interrupt sources 2. N chain = Number of scan chains Table 1. Pin Description List Name Definition Type Active Level Functional Comments nreset_r System Reset Input Low Resets all counters and signals clocked on rising edge of clock nreset_f System Reset Input Low Resets all counters and signals clocked on falling edge of clock clock System Clock Input periph_address[13:0] periph_data_in[31:0] periph_data_out[31:0] periph_write Peripheral Address Bus Peripheral Data Bus Input Peripheral Data Bus Input Peripheral Write Enable Input From host (bridge). Software user interface address bus Input From host (bridge). Software user interface data bus Output To host (bridge). Software user interface data bus Input From host (bridge). Transfer enable. When high, indicates that the host processor is writing to a register or executing a command. pstb_rising Input From host (bridge). Clock for all DFFs controlling configuration registers periph_strobe Peripheral Strobe Input High When high indicates that data and address buses are stable periph_select Peripheral Selection Input High When high nfiq and nirq outputs are disabled (set to high). nint is not affected 2

3 Table 1. Pin Description List (Continued) Name Definition Type Active Level Comments interrupt_lines[(n-1):0] (1) Interrupt Input Lines (Sources) Input Polarities can be defined in the configuration registers for inputs corresponding to external interrupt sources. Generally, they are connected as follows: - FIQ source on interrupt_lines[0] - N int internal sources on interrupt_lines[n int :1] (2) (1, 3) - N ext external sources on interrupt_lines[(n-1):(n-n ext )] Note: N = N ext + N int + 1(FIQ) nfiq Fast Interrupt Request Output Low Destination: Input nfiq of ARM core Source: Fast Interrupt Request; usually connected to interrupt_iines[0] nirq Interrupt Request Output Low Destination: Input nirq of ARM core Source: All interrupt requests (except Fast Interrupt Request) usually connected to interrupt_lines[(n-1):1] (1) nint Output Low Low if either nfiq or nirq is active. If nfiq and nirq are disabled by debug_int_mask, nint generates an interrupt depending on the interrupt sources Debug (for use with AT91 Development Tools) debug_mode Input Reserved. Must be set to 0 debug_int_mask Input Reserved. Must be set to 0 Test Scan scan_test_mode Scan Test Mode Input Must be tied to 1 during scan test. Must be tied to 0 in functional mode. test_se Test Scan Shift Enable Input Scan shift enabled when tied to 1 test_si[n chain :1] (4) Test Scan Input Input Input to scan chains test_so[n chain :1] (4) Test Scan Output Output Output from scan chains Notes: 1. N = Number of interrupt sources 2. N int = Number of internal interrupt sources 3. N ext = Number of external interrupt sources 4. N chain = Number of scan chains Scan Test Configuration The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to achieve this, the ATPG vectors must be generated on the entire circuit (top-level) which includes the or all I/Os must have a top level access and ATPG vectors must be applied to these pins. 3

4 Functional Description Figure 2. Interrupt Controller Block Diagram FIQ(IRQ0) Source Memorization nfiq Manager nfiq Bus Interface Control Logic 32-bit Core Internal Interrupt Sources (IRQ1 - IRQ8) External Interrupt Sources (IRQ9 - IRQ11) Memorization Prioritization Controller nirq Manager nirq Figure 3. Connecting the to an ARM -based Microcontroller CLOCK NRESET FIQ Source interrupt_lines[0] nfiq Internal Interrupt Sources (from peripheral interrupt outputs) External Interrupt Sources IRQ0 to IRQ2 (from ASIC pads, PIO peripherals,...) 3 Atmel Bus Interface interrupt_lines[8:1] interrupt_lines[11:9] PWRITE PWDATA[31:0 ](1) PA[13:0] PSTB_RISING PSTB PSEL PRDATA[31:0] (2) debug_int_mask debug_mode nint nirq 32-bit Core (ARM) Atmel Bridge ASB Notes: 1. data_to_periph = signal name from Atmel Bridge, periph_data_in[31:0] = signal name from peripheral, PWDATA[31:0] = signal name from Atmel AMBA System Architecture specification. 2. data_from_periph = signal name from Atmel Bridge, periph_data_out[31:0] = signal name from peripheral, PRDATA[31:0] = signal name from Atmel AMBA System Architecture specification. 4

5 Table 2. Interrupt Sources Interrupt Source Interrupt Name 0 FIQ Fast Interrupt 1 IRQ1 Interrupt 1 Interrupt Description (1) Comment AT91M40400 Interrupt Assignment (1) Edge/Level Negative/Positive Fast Interurpt Software Interrupt 2 IRQ2 Interrupt 2 USART Channel 0 Interrupt 3 IRQ3 Interrupt 3 USART Channel 1 Interrupt 4 IRQ4 Interrupt 4 Edge/Level Timer Channel 0 Interrupt 5 IRQ5 Interrupt 5 Positive only Timer Channel 1 Interrupt 6 IRQ6 Interrupt 6 Timer Channel 2 Interrupt 7 IRQ7 Interrupt 7 Watchdog Interrupt 8 IRQ8 Interrupt 8 Parallel I/O interrupt 9 Reserved Reserved 10 Reserved Reserved 11 Reserved Reserved 12 Reserved Reserved 13 Reserved Reserved 14 Reserved Reserved 15 Reserved Reserved 16 IRQ9 Interrupt 9 External Interrupt 0 17 IRQ10 Interrupt 10 Edge/Level Negative/Positive External Interrupt 1 18 IRQ11 Interrupt 11 External Interrupt 2 19 Reserved Reserved 20 Reserved Reserved 21 Reserved Reserved 22 Reserved Reserved 23 Reserved Reserved 24 Reserved Reserved 25 Reserved Reserved 26 Reserved Reserved 27 Reserved Reserved 28 Reserved Reserved 29 Reserved Reserved 30 Reserved Reserved 31 Reserved Reserved Note: 1. Reserved interrupt sources are not available. Corresponding registers must not be used and read 0. 5

6 Interrupt Handling Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one. By storing the following instruction at address 0x (if an ARM7TDMI is used as the host processor), the processor loads the program counter with the interrupt handler address stored in the _IVR register. Execution is then vectored to the interrupt handler corresponding to the current interrupt. LDR PC,[PC,# -&F20] The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register (_IVR) is read. The value read in the _IVR corresponds to the address stored in the Source Vector Register (_SVR) of the current interrupt. Each interrupt source has its corresponding _SVR. In order to take advantage of the hardware interrupt vectoring, it is necessary to store the address of each interrupt handler in the corresponding _SVR, at system initialization. Priority Controller The nirq line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. When the receives more than one unmasked interrupt at a time, the interrupt with the highest priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest interrupt source number (see Table 2) is serviced first. The current priority level is defined as the priority level of the current interrupt at the time the register _IVR is read (the interrupt which will be serviced). In the case when a higher priority unmasked interrupt occurs while an interrupt already exists, there are two possible outcomes depending on whether the _IVR has been read. 1. If the nirq line has been asserted but the _IVR has not been read, then the processor will read the new higher priority interrupt handler address in the _IVR register and the current interrupt level is updated. 2. If the processor has already read the _IVR then the nirq line is reasserted. When the processor has authorized nested interrupts to occur and reads the _IVR again, it reads the new, higher priority interrupt handler address. At the same time the current priority value is pushed onto a first-in last-out stack and the current priority is updated to the higher priority. 6 When the end of interrupt command register (_EOICR) is written the current interrupt level is updated with the last stored interrupt level from the stack (if any). Hence at the end of a higher priority interrupt, the returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. Software Interrupt Handling The interrupt handler must read the _IVR as soon as possible. This de-asserts the nirq request to the processor and clears the interrupt in case it is programmed to be edge triggered. This permits the to assert the nirq line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of interrupt command register (_EOICR) must be written. This allows pending interrupts to be serviced. Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled using the command registers _IECR and _IDCR. The interrupt mask can be read in the read only register _IMR. A disabled interrupt does not affect the servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources which are programmed to be edge triggered (including FIQ) can be individually set or cleared by respectively writing to the registers _ISCR and _ICCR. This function of the interrupt controller is available for auto-test or software debug purposes. Fast Interrupt Request The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore, it has no priority controller. It can be programmed to be positive or negative edge triggered or high- or low-level sensitive in the related _SMR register (SMR[0]). The fast interrupt handler address can be stored in the related _SVR register (SVR[0]). The value written into this register is available by reading the _FVR register when an FIQ interrupt is raised. By storing the following instruction at address 0x C (if an ARM7TDMI is used as the host processor), the processor will load the program counter with the interrupt handler address stored in the _FVR register. LDR PC,[PC,# -&F20] Alternatively, the interrupt handler can be stored starting from address 0x C as described in the ARM7TDMI datasheet.

7 Software Interrupt Any interrupt source of the can be a software interrupt. It must be programmed to be edge triggered in order to set or clear it by writing to the _ISCR and _ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor. Spurious Interrupt A spurious interrupt is a signal of very short duration on one of the interrupt input lines. See Spurious Interrupt Sequence on page 21 for the sequence of actions necessary to handle this situation. Figure 4. Register Interaction _ICCR _IPR _IVR Interrupt Sources N clear Edge/Polarity Detector set Level/Polarity Detector _ISCR Memorization Priority Encoder _SMRXX _ISR _CISR _SVR _SVR31 _IDCR clear Mask _IMR _IECR set 7

8 Timing Diagram Figure 5. Timing Diagram clock t PD_IRQ, t PD_FIQ, t PD_INT nfiq, nirq, nint periph_strobe pstb_rising t SU_A t HOLD_A periph_address[13:0] t SU_DIN t HOLD_DIN periph_data_in[31:0] t SU_WRITE t HOLD_WRITE periph_write t PD1 t PD2 periph_data_out[31:0] Valid 8

9 User Interface Table 3. Memory Map Address (2,3) Register Name Access Reset State 0x3000 Source Mode Register 0 _SMR0 Read/write 0 0x3004 Source Mode Register 1 _SMR1 Read/write 0 Read/write 0 0x307C Source Mode Register 31 _SMR31 Read/write 0 0x3080 Source Vector Register 0 _SVR0 Read/write 0 0x3084 Source Vector Register 1 _SVR1 Read/write 0 Read/write 0 0x30FC Source Vector Register 31 _SVR31 Read/write 0 0x3100 IRQ Vector Register _IVR Read-only 0 0x3104 FIQ Vector Register _FVR Read-only 0 0x3108 Interrupt Status Register _ISR Read-only 0 0x310C Interrupt Pending Register _IPR Read-only (see Note 1) 0x3110 Interrupt Mask Register _IMR Read-only 0 0x3114 Core Interrupt Status Register _CISR Read-only 0 0x3118 Reserved 0x311C Reserved 0x3120 Interrupt Enable Command Register _IECR Write-only 0x3124 Interrupt Disable Command Register _IDCR Write-only 0x3128 Interrupt Clear Command Register _ICCR Write-only 0x312C Interrupt Set Command Register _ISCR Write-only 0x3130 End of Interrupt Command Register _EOICR Write-only 0x3134 Spurious Interrupt Vector Register _SPU Read/write 0 Notes: 1. The reset value of this register depends on the level of the external interrupt sources (IRQ9 - IRQ11). All other sources are cleared at reset. 2. The address takes into account the 2 LSBs [1:0], but the macrocell does not implement these bits. 3. To use relative offset from interrupt exception vector addresses (see Standard Interrupt Sequence on page 19), the base address for the into an ARM7TDMI-based system must be 0xFFFFF000. As the 14 LSBs of the address system bus are used to address the registers, the minimum offset is 0x3000. In the following register descriptions, all undefined bits ( ) read 0. If the user selects an address which is not defined in Table 3, the value of periph_data_out[31:0] is 0x

10 Source Mode Register Register Name: _SMR0.._SMR31 Access Type: Read/write Reset Value: 0 SRCTYPE PRIOR PRIOR: Priority Level Program the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ, in the related SMR register (SMR[0]). SRCTYPE: Interrupt Source Type Program the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal interrupt sources (IRQ1 - IRQ8). SRCTYPE Internal Interrupt Sources (IRQ1 - IRQ8) External Interrupt Sources (IRQ9 - IRQ11) 0 0 Level-sensitive Low-level Sensitive 0 1 Edge-triggered Negative-edge Triggered 1 0 Level-sensitive High-level Sensitive 1 1 Edge-triggered Positive-edge Triggered 10

11 Source Vector Register Register Name: _SVR0.._SVR31 Access Type: Read/write Reset Value: 0 VECTOR VECTOR VECTOR VECTOR VECTOR: Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler for each interrupt source. 11

12 Interrupt Vector Register Register Name: _IVR Access Type: Read-only Reset Value: 0 IRQV IRQV IRQV IRQV IRQV: Interrupt Vector Register The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31 in the case of FIQ mapped on interrupt[0]) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. FIQ Vector Register Register Name: _FVR Access Type: Read-only Reset Value: 0 FIQV FIQV FIQV FIQV FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register (0 in case of FIQ mapped on interrupt[0]) that corresponds to FIQ. 12

13 Interrupt Status Register Register Name: _ISR Access Type: Read-only Reset Value: IRQID IRQID: Current IRQ Identifier The Interrupt Status Register returns the current interrupt source number. 13

14 Interrupt Pending Register Register Name: _IPR Access Type: Read-only Reset Value: 0 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Pending 0 = Corresponding interrupt is inactive. 1 = Corresponding interrupt is pending. Interrupt Mask Register Register Name: _IMR Access Type: Read-only Reset Value: 0 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 14

15 Core Interrupt Status Register Register Name: _CISR Access Type: Read-only Reset Value: NIRQ NFIQ NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active. NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. 15

16 Interrupt Enable Command Register Register Name: _IECR Access Type: Write-only IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. Interrupt Disable Command Register Register Name: _IDCR Access Type: Write-only IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 16

17 Interrupt Clear Command Register Register Name: _ICCR Access Type: Write-only IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. Interrupt Set Command Register Register Name: _ISCR Access Type: Write-only IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 FIQ Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 17

18 End of Interrupt Command Register Register Name: Access Type: _EOICR Write-only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. Spurious Interrupt Vector Register Register Name: _SPU Access Type: Read/write Reset Value: 0 SIQV SIQV SIQV SIQV SIQV: Spurious Interrupt Vector Register (see Spurious Interrupt Sequence on page 21 for more details) This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. The programmed address is read in the _IVR if it is read when the nirq line is not asserted. The programmed address is read in the _FVR if it is read when the nfiq line is not asserted. 18

19 Standard Interrupt Sequence For details on the registers mentioned in the steps below, refer to the ARM7TDMI Embedded Core datasheet. It is assumed that: 1. The advanced interrupt controller has been programmed, _SVR is loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at address 0x18 (IRQ exception vector address) is LDR PC, [PC, #-&F20] When nirq is asserted, if the bit I of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the IRQ link register (R14_IRQ) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_IRQ, decrementing it by four. 2. The ARM core enters IRQ mode, if it is not already. 3. When the instruction loaded at address 0x18 is executed, the Program Counter is loaded with the value read in _IVR. Reading the _IVR has the following effects: Sets the current interrupt to be the pending one with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nirq line on the processor. (Even if vectoring is not used, _IVR must be read in order to de-assert nirq.) Automatically clears the interrupt, if it has been programmed to be edge-triggered Pushes the current level on to the stack Returns the value written in the _SVR corresponding to the current interrupt 4. The previous step has effect to branch to the corresponding interrupt service routine. This should start by saving the Link Register(R14_IRQ) and the SPSR(SPSR_IRQ). Note that the Link Register must be decremented by four when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used,. 5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-assertion of the nirq to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The Interrupt Handler can then proceed as required, saving the registers which will be used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting, to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (_EOICR) must be written in order to indicate to the that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than old current level but with higher priority than the new current level, the nirq line is re-asserted, but the interrupt sequence does not immediately start because the I bit is set in the core. 9. The SPSR (SPSR_IRQ) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked). 19

20 Fast Interrupt Sequence For details on the registers mentioned in the steps below, refer to the ARM7TDMI Embedded Core datasheet. It is assumed that: 1. The Advanced Interrupt Controller has been programmed, the _SVR register corresponding to FIQ interrupt (_SVR[0] in this example) is loaded with fast interrupt service routine address, and the fast interrupt is enabled. 2. The Instruction at address 0x1C(FIQ exception vector address) is: LDR PC, [PC, #-&F20]. 3. Nested Fast Interrupts are not needed by the user. When nfiq is asserted, if the bit F of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (R14_FIQ) and the Program Counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_FIQ, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in _FVR. Reading the _FVR has effect of automatically clearing the fast interrupt (source 0 connected to the FIQ line), if it has been programmed to be edge triggered. In this case only, it de-asserts the nfiq line on the processor. 4. The previous step has effect to branch to the corresponding interrupt service routine. It is not necessary to save the Link Register(R14_FIQ) and the SPSR(SPSR_FIQ) if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the nfiq line. 6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the SPSR, masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). 20

21 Spurious Interrupt Sequence A spurious interrupt is a signal of very short duration on one of the interrupt input lines. It is handled by the following sequence of actions. 1. When an interrupt is active, the asserts the nirq (or nfiq) line and the ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source disappears, the nirq (or nfiq) line is de-asserted but the ARM7TDMI continues with the interrupt handler. 2. If the IRQ Vector Register (_IVR) is read when the nirq is not asserted, the _IVR is read with the contents of the Spurious Interrupt Vector Register. 3. If the register FIQ Vector Register (_FVR) is read when the nfiq is not asserted, the _FVR is read with the contents of the Spurious Interrupt Vector Register. 4. The Spurious Interrupt Routine must as a minimum write an end of interrupt command. It is sufficient to write to the end of interrupt command register _EOICR. Until the _EOICR write is received by the interrupt controller, the nirq (or nfiq) line is not reasserted. 5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine. 6. During a Spurious Interrupt Routine, the Interrupt Status Register _ISR reads 0. 21

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