Microkernel Construction

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1 Microkernel Construction Kernel Entry / Exit Nils Asmussen 05/04/ / 45

2 Outline x86 Details Protection Facilities Interrupts and Exceptions Instructions for Entry/Exit Entering NOVA Leaving NOVA 2 / 45

3 Privilege Levels Ring 3 Ring 2 Ring 1 Ring 0 Ring 0 Operating System Kernel Privileged Ring 1 & 2 Operating System Services Unprivileged Ring 3 User-level Applications Unprivileged 3 / 45

4 Protection Facilities Segmentation Mechanism for dividing linear address space into segments Different segment types: code, data, stack,... Segment has base address and limit Mandatory mechanism; cannot be disabled Paging Mechanism for translating linear to physical addresses Splits virt. & phys. address space into same-size pages Per-page access rights (present, writable, user/kernel) Optional; can be turned off (not on x86 64) 4 / 45

5 Logical Address Translation Logical address consists of Segment selector Segment offset CPU uses table indicator in segment selector to access descriptor in GDT/LDT Segment descriptor provides segment base address, segment limit and access rights (checked by CPU) CPU adds segment offset to segment base address to form linear address 5 / 45

6 Logical Address Translation Logical Address: Seg. Selector Seg. Offset Limit Seg. Desc + Segment Linear Address GDT Base Address Linear Address Space 6 / 45

7 Segment Registers CPU provides 6 segment registers for holding selectors CS (code segment) DS (data segment) SS (stack segment) ES, FS, GS (extra data segments) Selector forms visible part Base address, limit and access rights form shadow part 7 / 45

8 Segment Descriptor Base Address (31..24) G D 0 A V L Limit (19..16) Type P DPL 1 1 C R A Base Address (23..16) Base Address (15..0) Segment Limit (15..0) Figure: Code Segment Descriptor 0 G Granularity DPL Descriptor Privilege Level D Default Size (16/32 Bit) C Conforming AVL Available to Programmer R Readable P Present A Accessed 8 / 45

9 Flat Memory Model Hide segmentation mechanism by Setting segment base address to 0 Setting segment limit to 4 GiB Mandatory for x86 64 We need at least 2 segments Code segment Data/Stack segment If kernel/user use different segment base addresses or segment limits, we need 2 additional segments for each 9 / 45

10 Protection Checks CPU checks on instructions and memory references that certain protection conditions hold: Segment limit check Segment type check Privilege level check Restricted procedure entry points Restricted instruction set... CPU raises exception if protection check fails Protection checks in parallel with address translation No big performance penalty 10 / 45

11 Privileged Instructions LGDT LLDT LTR LIDT MOV to CR LMSW CLTS MOV to DR INVD WBINVD INVLPG HLT RDMSR / WRMSR RDPMC / RDTSC CLI / STI 11 / 45

12 Interrupts & Exceptions Forced transfer of execution from currently executing code to interrupt- or exception handler Hardware interrupts occur asynchronously in response to hardware events Exceptions (including software interrupts) occur synchronously to the instruction stream 12 / 45

13 Interrupt & Exception Vectors Vector uniquely identifies source of the interrupt or exception Vectors are used for exceptions Vectors are designated user vectors (e.g., interrupts) Interrupt Descriptor Table (IDT) is table of handler functions for all interrupts and exceptions Setup by OS Hardware is informed about it via LIDT instruction Vector = offset into IDT 13 / 45

14 Interrupt Descriptor Table (IDT) IDTR register: IDT base address IDT limit Gate for Vector n +... Gate for Vector 2 Gate for Vector 1 Gate for Vector 0 14 / 45

15 Restricted Procedure Entry Points: Gates Descriptors to call procedures at different privilege levels Subject to CPL/RPL vs. DPL checking CS and EIP loaded from descriptor Interrupt Gate disables interrupts, Trap Gate doesn t When switching privilege levels, new ESP loaded from TSS TSS contains stack pointers for privilege levels 0, 1 and 2 Kernel updates SP 0 in TSS on every thread switch Interrupt and exception handlers runs current thread s context 15 / 45

16 Interrupt Gate Offset (31..16) P DPL Reserv. Segment Selector Offset (0..15) Selector Offset DPL P Segment Selector for destination code segment Offset to procedure entry point in segment Descriptor privilege level (ignored for HW ints) Segment present flag 16 / 45

17 Exception Types Faults Can be corrected and allow the program to be resumed Processor restores machine state prior to the execution of faulting instruction (CS and EIP point to faulting instruction) Traps Reported immediately after execution of trapping instruction Allow the program to be resumed (CS and EIP point to following instruction) Aborts Are not always reported at the precise location of the exception Do not allow to resume the program Usually report severe hardware errors or inconsistent state 17 / 45

18 Exceptions 0: Divide Error (F) 1: Debug Exception (F/T) 2: Non-maskable Interrupt 3: Breakpoint (T) 4: Overflow (T) 5: Bound Range Exc. (F) 6: Invalid Opcode (F) 7: Device Not Available (F) 8: Double Fault (A) 9: Coproc. Seg. Overr. (F) 10: Invalid TSS (F) 11: Segm. Not Present (F) 12: Stack Segment Fault (F) 13: General Prot. Fault (F) 14: Pagefault (F) 15: reserved 16: FPU Math Fault (F) 17: Alignment Check (F) 18: Machine Check (A) 19: SIMD FP Exception (F) 18 / 45

19 Kernel Stack after Kernel Entry EFLAGS CS EIP SS ESP EFLAGS (Error Code) No Priv. Level Change ESP CS EIP (Error Code) Priv. Level Change 19 / 45

20 Kernel Entry SS ESP EFLAGS CS EIP entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 20 / 45

21 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 21 / 45

22 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 Error=0 entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 22 / 45

23 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 23 / 45

24 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 24 / 45

25 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt 25 / 45

26 Kernel Entry SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) entry_6: push $6 jmp entry_exc entry_exc: push $0 entry_exc_err: push %ds push %es push %fs push %gs pusha mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc handler jmp ret_from_interrupt 26 / 45

27 Exception Handler REGPARM(1) void exc_handler (Exc_regs *r) { switch (r->vec) { case Cpu::EXC_TS: handle_exc_ts (r); break; case Cpu::EXC_PF: handle_exc_pf (r); break;... } } void handle_exc_pf (Exc_regs *r) { mword addr = r->cr2; if(pd::current->space_mem::loc[cpu::id].sync_from ( Pd::current->Space_mem::hpt, addr)) return;... } 27 / 45

28 Kernel Exit to Kernel Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... )... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret from interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret_user_iret popa add $24, %esp iret 28 / 45

29 Kernel Exit to Kernel Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... )... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret user iret popa add $24, %esp iret 29 / 45

30 Kernel Exit to Kernel Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... )... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret_user_iret popa add $24, %esp iret 30 / 45

31 Kernel Exit to Kernel Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret_user_iret popa add $24, %esp iret 31 / 45

32 Kernel Exit to Kernel Mode SS ESP EFLAGS CS EIP... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret_user_iret popa add $24, %esp iret 32 / 45

33 Kernel Exit to Kernel Mode... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret_user_iret popa add $24, %esp iret 33 / 45

34 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... )... mov %esp, %ebx mov $KSTCK_BEGIN, %esp mov %cr2, %eax mov %eax, 0xc(%ebx) mov %ebx, %eax call exc_handler jmp ret_from_interrupt ret_from_interrupt: testb $3, 0x3c(%ebx) jnz ret user iret popa add $24, %esp iret 34 / 45

35 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) void ret_user_iret() { handle hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 35 / 45

36 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 36 / 45

37 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS GPR (eax, ecx, edx, ebx, cr2,... ) void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 37 / 45

38 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 DS ES FS GS void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 38 / 45

39 Kernel Exit to User Mode SS ESP EFLAGS CS EIP Vector=6 Error=0 void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 39 / 45

40 Kernel Exit to User Mode SS ESP EFLAGS CS EIP void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 40 / 45

41 Kernel Exit to User Mode void ret_user_iret() { handle_hazards(); } asm volatile ( "lea %0, %%esp;" "popa;" "pop %%gs;" "pop %%fs;" "pop %%es;" "pop %%ds;" "add $8, %%esp;" "iret;" : : "m" (current->regs) : "memory" ); UNREACHED; 41 / 45

42 Kernel Exit: IRET Load code segment selector, EIP and flags from stack Evaluate RPL of CS from stack RPL > CPL: return to other privilege level otherwise: return to same privilege level If privilege level changes Load stack segment selector and ESP from stack Adjust CPL 42 / 45

43 Fast Kernel Entry: SYSENTER Fast ring transition from any ring to ring 0 Kernel code entry point specified via SYSENTER CS MSR (code segment) SYSENTER EIP MSR (entry function) SYSENTER ESP MSR (kernel stack pointer) CPU... Disables interrupts Loads kernel CS (from SYSENTER CS MSR) Loads kernel SS (from SYSENTER CS MSR + 8) Loads kernel ESP (from SYSENTER ESP MSR) Loads kernel EIP (from SYSENTER EIP MSR) Does NOT save user return EIP or other user state 43 / 45

44 Fast Kernel Exit: SYSEXIT Fast ring transition from any ring to ring 3 CPU... Loads user CS (from SYSENTER CS MSR + 16) Loads user SS (from SYSENTER CS MSR + 24) Loads user ESP (from ECX) Loads user EIP (from EDX) Enables interrupts 44 / 45

45 Next Weeks May, 11th: Exercise 1 (Kernel entry/exit) in room E067 May, 18th: Exercise 2 (Multiboot, ELF) in room E067 May, 25th: Interprocess communication June, 1st: Exercise 3 (Thread switching) in room E067 June, 8th: Capabilities / 45

Microkernel Construction

Microkernel Construction Kernel Entry / Exit SS2013 Control Transfer Microkernel User Stack A Address Space Kernel Stack A User Stack User Stack B Address Space Kernel Stack B User Stack 1. Kernel Entry (A) 2. Thread Switch (A