µ-kernel Construction (12)
|
|
- Adela French
- 5 years ago
- Views:
Transcription
1 µ-kernel Construction (12) Review 1
2 Threading Thread state must be saved/restored on thread switch We need a Thread Control Block (TCB) per thread TCBs must be kernel objects TCBs implement threads We need to find Any thread s TCB using its global ID The currently executing thread s TCB (per processor) At least partially. We have found some good reasons to implement parts of the TCB in user memory. 2
3 Thread Switch A B Thread A is running in user mode Thread A experiences an end-of-time-slice or is preempted by a (device) interrupt We enter kernel mode The microkernel saves the status of thread A on A s TCB The microkernel loads the status of thread B from B s TCB We leave kernel mode Thread B is running in user mode 3
4 Thread Switch A kernel B Processor IP SP FLAGS IP SP FLAGS tcb A user mode A 4
5 Thread Switch A kernel B? Processor IP SP FLAGS IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 5
6 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 6
7 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 7
8 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A user mode A kernel 8
9 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel 9
10 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel IP SP FLAGS tcb B Kernel stack 10
11 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel IP SP FLAGS tcb B Kernel stack 11
12 Thread ID TCB Direct Address movl thread_id, %eax movl %eax, %ebx andl mask_version, %eax shrl threadno_shift, %eax addl offset, %eax Kernel TCB area User %eax Thread TCB NopointerVersion Mask out lower bits Bitshift Add offset offset 12
13 0-Mapping Trick Direct Addressing Allocate physical memory for TCBs on demand Dependent on the max number of allocated TCBs Map all remaining TCBs to a 0-filled read-only page Any access to unused threads will result in invalid thread ID (0) Avoids additional check TCB Array (virtual memory) n m p q r Virtual TCB array requires 256 MB virtual memory for 256k potential TCBs 0 Physical Memory Frames containing TCBs. s 13
14 Basic Address-Space Layout 14
15 Address-Space Layout 32bits, Virtual TCBs User regions Shared system regions Per-space system regions Other kernel tables Physical memory Kernel code TCBs phys mem 15
16 Shared Region Synchronization We have Region shared among all address spaces Separate page table per address space Updates occur in dynamic region May lead to inconsistencies We need Some form of synchronization within dynamic region Make sure valid virtual memory mappings are synchronized phys mem Dynamic region Static region 16
17 TCB Area Synchronization Basic Algorithm Dedicate one table as master Synchronize with master table on page faults Page fault algorithm: if (master entry valid) { copy entry from master } else { create new entry in master copy entry from master } Master Table Dynamic region Static region 17
18 TCB Area Synchronization Modifying Mappings Page tables have multiple levels IA-32: page directories and page tables We only synchronize top level (page directory) Modifications in lower levels visible in all spaces Works even if entries are invalidated ptab ptab ptab 0 pdir pdir 18
19 IPC 19
20 IPC API Operations Message Types Send to Registers Receive from Strings Receive Map pages Call Send to & Receive any Send to & Receive from 20
21 Timeouts snd timeout, rcv timeout, xfer timeout snd, xfer timeout rcv time wait for send send message (xfer) wait for reply receive message (xfer) snd to min (xfer to snd, xfer to rcv) rcv to min (xfer to rcv, xfer to snd) (specified by the partner thread) 21
22 Timeouts relative timeout values 0 infinite 0 (16) 0(10) 0 1 (5) m(10) 0 e (5) 1 µs 610 h (log) 2 e m µs absolute timeout values 1 e (4) c m (10) 10 e clock = m (10) 0 clock + 2 (e+10) m (10) 22
23 Message Construction Messages are stored in registers (MR 0 MR 63 ) First register (MR 0 ) acts as message tag Subsequent registers contain Untyped words (u), and Typed words (t) (e.g., map item, string item) Number of untyped words Number of typed words Various IPC flags MR 0 label flags t uu Message Tag Freely available (e.g., request type) 23
24 Message Construction Typed items occupy one or more words Three currently defined items Map item (2 words) Grant item (2 words) String item (2+ words) Typed items can have arbitrary order MR 8 MR 7 MR 6 MR 5 MR 4 MR 3 MR 2 MR 1 3 MR 0 label String Item Map Item Message flags 5t uu 24
25 Map and Grant Items Two words Send base Fpage send base send fpage Map Item C MR i+1 MR i Lower bits of send base indicates map or grant item send base send fpage Grant Item C MR i+1 MR i location Fpage size 0wrx 25
26 String Items Up to 4 MB (per string) Compound strings supported Allows scatter-gather Incorporates cacheability hints Reduce cache pollution for long copy operations string pointer string length String Item MR i hhC MR i hh indicates cacheability hints for the string E.g., only use L2 cache, or do not use cache at all 26
27 Receiving Messages Receiver buffers are specified in registers (BR 0 BR 33 ) First BR (BR 0 ) contains Acceptor May specify receive window (if not nil-fpage) May indicate presence of receive strings/buffers (if s-bit set) receive window Acceptor 000s BR 0 27
28 What are Virtual Registers? Virtual registers are backed by either Physical registers, or Non-pageable memory UTCBs hold the memory backed registers UTCBs are thread local UTCB can not be paged No page faults Registers always accessible Preserved by switching UTCB on context switch Virtual Registers MR MR MR MR 4 MR 3 MR 2 MR 1 MR 0 Preserved by kernel during context switch UTCB MR 63 MR 62 MR 61 MR 4 MR 3 ESI EBX EBP Physical Registers 28
29 Implementation Goal Most frequent kernel op: short IPC Thousands of invocations per second Performance is critical Structure IPC for speed Structure entire kernel to support fast IPC What affects performance? Cache line misses TLB misses Memory references Pipe stalls and flushes Instruction scheduling 29
30 Requirements for Fast Path IPC Untyped message Single runnable thread after IPC Must be valid call-like IPC Send phase Target is already waiting Receive phase Sender is not ready to couple, causing up to block Switch threads, originator blocks No receive timeout Send timeout can be ignored: receiver is waiting Xfer timeouts do not apply for untyped messages 30
31 Memory is Forbidden Memory references are slow Avoid in IPC E.g., use lazy scheduling Avoid in common case E.g., (xfer) timeouts Microkernel should minimize artifacts Cache pollution TLB pollution Memory bus 31
32 TCB + kernel stack IPC EAX ECX EDX TSS.esp0 EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 32
33 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 33
34 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 34
35 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 35
36 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 36
37 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 37
38 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 38
39 String IPC / memcpy Why? Trust Granularity Synchronous ( atomic ) transfer 39
40 Temporary Mapping 40
41 Temporary Mapping Select dest area (2x4 MB) 41
42 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) 42
43 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) Copy data 43
44 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) Copy data Switch to dest space 44
45 Temporary Mapping Copy page directory entry (PDE) from dest Addresses in temporary mapping area are resolved using dest s page table 45
46 Mapping 46
47 Mechanisms We need tools to build address spaces Map Unmap We need security Access permissions [rwx] We need resource control Use bits [accessed or dirty] Page fault messages [detect page use] 47
48 Map Map Map A B Agreed to receive mapping (BR 0 ). C Map D E 48
49 Unmap Unmap Unmap A B Implicit consent to unmap. C D E 49
50 Unmap Unmap Unmap A B Implicit consent to unmap. C D E 50
51 Grant Grant A B Grant C D E 51
52 Grant Grant A B Grant C D E 52
53 Access Rights Map r = Read w = Write x = execute A rwx rx B Mapper may restrict access rights Cannot extend its own access rights C rx rwx D rx 53
54 Access Rights Unmap r = Read w = Write x = execute A rwx B unmap(x) Mapper may revoke partial access rights Cannot extend other s access rights Unmap transitively affects mappings D C Preserves idea of synchronous mapping 54 rx rx
55 Mapping Regions A B C D 55
56 Mapping Regions: Flex Pages Abstraction: flex page Contiguous region of virtual address space Sparse physical mappings possible Called fpage Abstracts from architecture s page sizes Fpage semantics Inseparable object Aligned to its size Size is power of 2, min. 1024=2 10 byte 56
57 Fpage Encoding fpage( base, size=2 s ) s 10 base mod 2 s = 0 Special cases Complete address space (base=0, s=1) Nothing: nilpage (0) base / 2 10 s 0 r w x 22/54 bits 6 bits 4 bits 57
58 Status Bits Referenced, Written, executed Reset not visible here A B Query & reset Bitwise OR C D Reset not visible E here 58
59 Status Bits Referenced, Written, executed Query & reset Bitwise OR A B Reset not visible here C D E 59
60 Mapping Regions Implementation Based on page tables Physical page (frame) Basic mapping unit Determines minimum alignment Minimum fpage size Physical page size 60
61 Mapping Pages AS(A) map AS(B) Map pages by copying page table entries No support (yet) for Recursive unmap Combined status bits 61
62 Mapping Database physical frames physical frames AA A[1] BB B[7] DD CC D[0] C[2] E[0] XX EE 62
63 Page Fault IPC IP fault addr rwx Application PF IPC res IPC "PF" msg map msg Pager PF-IPC synthesized by the kernel, pager s reply caught by the kernel (application is not informed/involved) 63
64 IPC Map Configured by receiver receive window What about page faults? A Map item offset B 64
65 New Exception Handling Model IP SP EAX Application exception msg continue msg Exception Handler Except.-IPC synthesized by the kernel, handler s reply caught by the kernel (application is not informed/involved). IP SP EAX Kernel modifies register contents according to reply message 65
66 Other Key Ideas Avoid memory No indirection (TCB area) Lazy scheduling Make clever use of HW features Sysenter/sysexit Segmentation ( small spaces) Serialize recursive algorithms Recursive unmap 66
IPC Functionality & Interface Universität Karlsruhe, System Architecture Group
µ-kernel Construction (4) IPC Functionality & Interface 1 IPC Primitives Send to (a specified thread) Receive from (a specified thread) Two threads communicate No interference from other threads Other
More informationµ-kernel Construction
µ-kernel Construction Fundamental Abstractions Thread Address Space What is a thread? How to implement? What conclusions can we draw from our analysis with respect to µk construction? A thread of control
More information8/09/2006. µ-kernel Construction. Fundamental Abstractions. Thread Switch A B. Thread Switch A B. user mode A kernel. user mode A
Fundamental Abstractions µ- Construction Thread Address Space What is a thread? How to implement? What conclusions can we draw from our analysis with rect to µk construction? A thread of control has internal
More informationTCBs and Address-Space Layouts Universität Karlsruhe, System Architecture Group
µ-kernel Construction (3) TCBs and Address-Space Layouts 1 Thread Control Blocks (TCBs) 2 Fundamental Abstractions Thread Address space What is a thread? How to implement it? 3 Construction Conclusion
More informationµ-kernel Construction
µ-kernel Construction Fundamental Abstractions Thread Address Space What is a thread? How to implement? What conclusions can we draw from our analysis with respect to µk construction? Processor? IP SP
More information19/09/2008. Microkernel Construction. IPC - Implementation. IPC Importance. General IPC Algorithm. IPC Implementation. Short IPC
IPC Importance Microkernel Construction IPC Implementation General IPC Algorithm Validate parameters Locate target thread if unavailable, deal with it Transfer message untyped - short IPC typed message
More information19/09/2008. µ-kernel Construction. Fundamental Abstractions. user mode A kernel. user mode A kernel. user mode A kernel. user mode A kernel
Fundamental Abstractions µ- Construction Thread Address Space What is a thread? How to implement? What conclusions can we draw from our analysis with rect to µk construction? Processor? A Processor code
More informationµ-kernel Construction
µ-kernel Construction Fundamental Abstractions Thread Address Space What is a thread? How to implement? What conclusions can we draw from our analysis with respect to µk construction? Fundamental Abstractions
More informationMultiprocessor Solution
Mutual Exclusion Multiprocessor Solution P(sema S) begin while (TAS(S.flag)==1){}; { busy waiting } S.Count= S.Count-1 if (S.Count < 0){ insert_t(s.qwt) BLOCK(S) {inkl.s.flag=0)!!!} } else S.flag =0 end
More informationThreads, System Calls, and Thread Switching
µ-kernel Construction (2) Threads, System Calls, and Thread Switching (updated on 2009-05-08) Review from Last Lecture The 100-µs Disaster 25 MHz 386 50 MHz 486 90 MHz Pentium 133 MHz Alpha 3 C Costs (486,
More informationLow Level Programming Lecture 2. International Faculty of Engineerig, Technical University of Łódź
Low Level Programming Lecture 2 Intel processors' architecture reminder Fig. 1. IA32 Registers IA general purpose registers EAX- accumulator, usually used to store results of integer arithmetical or binary
More informationAssembly Language. Lecture 2 - x86 Processor Architecture. Ahmed Sallam
Assembly Language Lecture 2 - x86 Processor Architecture Ahmed Sallam Introduction to the course Outcomes of Lecture 1 Always check the course website Don t forget the deadline rule!! Motivations for studying
More informationICS143A: Principles of Operating Systems. Midterm recap, sample questions. Anton Burtsev February, 2017
ICS143A: Principles of Operating Systems Midterm recap, sample questions Anton Burtsev February, 2017 Describe the x86 address translation pipeline (draw figure), explain stages. Address translation What
More informationFaculty of Computer Science Institute for System Architecture, Operating Systems Group. Memory. Björn Döbel. Dresden,
Faculty of Computer Science Institute for System Architecture, Operating Systems Group Memory Björn Döbel Dresden, 2013-11-05 So far... Introduction Monolithic vs. microkernels L4 concepts: Threads and
More informationFundamental Concepts. L4 Programming Introduction. Root Task. KernelInterface. Kernel Information Page. Drivers at User Level
Fundamental Concepts L4 Programming Introduction Address Spaces Unit of protection, resource management Threads Execution abstraction and provide unique identifiers Communication: IPC Synchronous Identification:
More informationProcesses and Tasks What comprises the state of a running program (a process or task)?
Processes and Tasks What comprises the state of a running program (a process or task)? Microprocessor Address bus Control DRAM OS code and data special caches code/data cache EAXEBP EIP DS EBXESP EFlags
More informationAssembly Language. Lecture 2 x86 Processor Architecture
Assembly Language Lecture 2 x86 Processor Architecture Ahmed Sallam Slides based on original lecture slides by Dr. Mahmoud Elgayyar Introduction to the course Outcomes of Lecture 1 Always check the course
More informationIA32 Intel 32-bit Architecture
1 2 IA32 Intel 32-bit Architecture Intel 32-bit Architecture (IA32) 32-bit machine CISC: 32-bit internal and external data bus 32-bit external address bus 8086 general registers extended to 32 bit width
More informationMicrokernel Design A walk through selected aspects of
Microkernel Design A walk through selected aspects of kernel design and sel4 These slides are made distributed under the Creative Commons Attribution 3.0 License, unless otherwise noted on individual slides.
More informationThe Instruction Set. Chapter 5
The Instruction Set Architecture Level(ISA) Chapter 5 1 ISA Level The ISA level l is the interface between the compilers and the hardware. (ISA level code is what a compiler outputs) 2 Memory Models An
More informationComplex Instruction Set Computer (CISC)
Introduction ti to IA-32 IA-32 Processors Evolutionary design Starting in 1978 with 886 Added more features as time goes on Still support old features, although obsolete Totally dominate computer market
More informationFunction Calls COS 217. Reading: Chapter 4 of Programming From the Ground Up (available online from the course Web site)
Function Calls COS 217 Reading: Chapter 4 of Programming From the Ground Up (available online from the course Web site) 1 Goals of Today s Lecture Finishing introduction to assembly language o EFLAGS register
More informationAddressing Modes on the x86
Addressing Modes on the x86 register addressing mode mov ax, ax, mov ax, bx mov ax, cx mov ax, dx constant addressing mode mov ax, 25 mov bx, 195 mov cx, 2056 mov dx, 1000 accessing data in memory There
More informationCS533 Concepts of Operating Systems. Jonathan Walpole
CS533 Concepts of Operating Systems Jonathan Walpole Improving IPC by Kernel Design & The Performance of Micro- Kernel Based Systems The IPC Dilemma IPC is very import in µ-kernel design - Increases modularity,
More informationChapter 11. Addressing Modes
Chapter 11 Addressing Modes 1 2 Chapter 11 11 1 Register addressing mode is the most efficient addressing mode because the operands are in the processor itself (there is no need to access memory). Chapter
More informationHardware and Software Architecture. Chapter 2
Hardware and Software Architecture Chapter 2 1 Basic Components The x86 processor communicates with main memory and I/O devices via buses Data bus for transferring data Address bus for the address of a
More informationEXPERIMENT WRITE UP. LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM
EXPERIMENT WRITE UP AIM: Assembly language program for 16 bit BCD addition LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM TOOLS/SOFTWARE
More informationIA32/Linux Virtual Memory Architecture
IA32/Linux Virtual Memory Architecture Basic Execution Environment Application Programming Registers General-purpose registers 31 0 EAX AH AL EBX BH BL ECX CH CL EDX DH DL EBP ESI EDI BP SI DI Segment
More informationIntroduction to IA-32. Jo, Heeseung
Introduction to IA-32 Jo, Heeseung IA-32 Processors Evolutionary design Starting in 1978 with 8086 Added more features as time goes on Still support old features, although obsolete Totally dominate computer
More informationMicrokernel Construction
Kernel Entry / Exit SS2013 Control Transfer Microkernel User Stack A Address Space Kernel Stack A User Stack User Stack B Address Space Kernel Stack B User Stack 1. Kernel Entry (A) 2. Thread Switch (A
More informationWhat You Need to Know for Project Three. Dave Eckhardt Steve Muckle
What You Need to Know for Project Three Dave Eckhardt Steve Muckle Overview Introduction to the Kernel Project Mundane Details in x86 registers, paging, the life of a memory access, context switching,
More informationLecture 15 Intel Manual, Vol. 1, Chapter 3. Fri, Mar 6, Hampden-Sydney College. The x86 Architecture. Robb T. Koether. Overview of the x86
Lecture 15 Intel Manual, Vol. 1, Chapter 3 Hampden-Sydney College Fri, Mar 6, 2009 Outline 1 2 Overview See the reference IA-32 Intel Software Developer s Manual Volume 1: Basic, Chapter 3. Instructions
More informationINTRODUCTION TO IA-32. Jo, Heeseung
INTRODUCTION TO IA-32 Jo, Heeseung IA-32 PROCESSORS Evolutionary design Starting in 1978 with 8086 Added more features as time goes on Still support old features, although obsolete Totally dominate computer
More informationMicrokernel Construction
Microkernel Construction Kernel Entry / Exit Nils Asmussen 05/04/2017 1 / 45 Outline x86 Details Protection Facilities Interrupts and Exceptions Instructions for Entry/Exit Entering NOVA Leaving NOVA 2
More informationMICROPROCESSOR TECHNOLOGY
MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 5 Ch.2 A Top-Level View of Computer Function (Cont.) 24-Feb-15 1 CPU (CISC & RISC) Intel CISC, Motorola RISC CISC (Complex Instruction
More information238P: Operating Systems. Lecture 5: Address translation. Anton Burtsev January, 2018
238P: Operating Systems Lecture 5: Address translation Anton Burtsev January, 2018 Two programs one memory Very much like car sharing What are we aiming for? Illusion of a private address space Identical
More informationUMBC. contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. contain displacement added to IP.
Procedures: CALL: Pushes the address of the instruction following the CALL instruction onto the stack. RET: Pops the address. SUM PROC NEAR USES BX CX DX ADD AX, BX ADD AX, CX MOV AX, DX RET SUM ENDP NEAR
More information143A: Principles of Operating Systems. Lecture 6: Address translation. Anton Burtsev January, 2017
143A: Principles of Operating Systems Lecture 6: Address translation Anton Burtsev January, 2017 Address translation Segmentation Descriptor table Descriptor table Base address 0 4 GB Limit
More informationAssembler Programming. Lecture 2
Assembler Programming Lecture 2 Lecture 2 8086 family architecture. From 8086 to Pentium4. Registers, flags, memory organization. Logical, physical, effective address. Addressing modes. Processor Processor
More information6/17/2011. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to:
Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Introduction This chapter presents the microprocessor
More information6.828: Using Virtual Memory. Adam Belay
6.828: Using Virtual Memory Adam Belay abelay@mit.edu 1 Outline Cool things you can do with virtual memory: Lazy page allocation (homework) Better performance/efficiency E.g. One zero-filled page E.g.
More informationMachine-level Representation of Programs. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Machine-level Representation of Programs Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Program? 짬뽕라면 준비시간 :10 분, 조리시간 :10 분 재료라면 1개, 스프 1봉지, 오징어
More informationThe x86 Architecture
The x86 Architecture Lecture 24 Intel Manual, Vol. 1, Chapter 3 Robb T. Koether Hampden-Sydney College Fri, Mar 20, 2015 Robb T. Koether (Hampden-Sydney College) The x86 Architecture Fri, Mar 20, 2015
More informationx86 Assembly Tutorial COS 318: Fall 2017
x86 Assembly Tutorial COS 318: Fall 2017 Project 1 Schedule Design Review: Monday 9/25 Sign up for 10-min slot from 3:00pm to 7:00pm Complete set up and answer posted questions (Official) Precept: Monday
More informationChapter 2: The Microprocessor and its Architecture
Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Introduction This chapter presents the microprocessor
More informationHistory of the Intel 80x86
Intel s IA-32 Architecture Cptr280 Dr Curtis Nelson History of the Intel 80x86 1971 - Intel invents the microprocessor, the 4004 1975-8080 introduced 8-bit microprocessor 1978-8086 introduced 16 bit microprocessor
More informationThe Microprocessor and its Architecture
The Microprocessor and its Architecture Contents Internal architecture of the Microprocessor: The programmer s model, i.e. The registers model The processor model (organization) Real mode memory addressing
More information143A: Principles of Operating Systems. Lecture 5: Address translation. Anton Burtsev October, 2018
143A: Principles of Operating Systems Lecture 5: Address translation Anton Burtsev October, 2018 Two programs one memory Or more like renting a set of rooms in an office building Or more like renting a
More informationMICROKERNEL CONSTRUCTION 2014
MICROKERNEL CONSTRUCTION 2014 THE FIASCO.OC MICROKERNEL Alexander Warg MICROKERNEL CONSTRUCTION 1 FIASCO.OC IN ONE SLIDE CAPABILITY-BASED MICROKERNEL API single system call invoke capability MULTI-PROCESSOR
More informationDr. Ramesh K. Karne Department of Computer and Information Sciences, Towson University, Towson, MD /12/2014 Slide 1
Dr. Ramesh K. Karne Department of Computer and Information Sciences, Towson University, Towson, MD 21252 rkarne@towson.edu 11/12/2014 Slide 1 Intel x86 Aseembly Language Assembly Language Assembly Language
More informationMechanisms for entering the system
Mechanisms for entering the system Yolanda Becerra Fontal Juan José Costa Prats Facultat d'informàtica de Barcelona (FIB) Universitat Politècnica de Catalunya (UPC) BarcelonaTech 2017-2018 QP Content Introduction
More informationAssembly Language: Function Calls
Assembly Language: Function Calls 1 Goals of this Lecture Help you learn: Function call problems: Calling and returning Passing parameters Storing local variables Handling registers without interference
More informationCOS 318: Operating Systems. Overview. Prof. Margaret Martonosi Computer Science Department Princeton University
COS 318: Operating Systems Overview Prof. Margaret Martonosi Computer Science Department Princeton University http://www.cs.princeton.edu/courses/archive/fall11/cos318/ Announcements Precepts: Tue (Tonight)!
More informationTutorial 10 Protection Cont.
Tutorial 0 Protection Cont. 2 Privilege Levels Lower number => higher privilege Code can access data of equal/lower privilege levels only Code can call more privileged data via call gates Each level has
More informationProcesses (Intro) Yannis Smaragdakis, U. Athens
Processes (Intro) Yannis Smaragdakis, U. Athens Process: CPU Virtualization Process = Program, instantiated has memory, code, current state What kind of memory do we have? registers + address space Let's
More informationFor your convenience Apress has placed some of the front matter material after the index. Please use the Bookmarks and Contents at a Glance links to
For your convenience Apress has placed some of the front matter material after the index. Please use the Bookmarks and Contents at a Glance links to access them. Contents at a Glance About the Author...xi
More informationProtection and System Calls. Otto J. Anshus
Protection and System Calls Otto J. Anshus Protection Issues CPU protection Prevent a user from using the CPU for too long Throughput of jobs, and response time to events (incl. user interactive response
More informationAssembly Language: Function Calls" Goals of this Lecture"
Assembly Language: Function Calls" 1 Goals of this Lecture" Help you learn:" Function call problems:" Calling and returning" Passing parameters" Storing local variables" Handling registers without interference"
More informationAusgewählte Betriebssysteme. Anatomy of a system call
Ausgewählte Betriebssysteme Anatomy of a system call 1 User view #include int main(void) { printf( Hello World!\n ); return 0; } 2 3 Syscall (1) User: write(fd, buffer, sizeof(buffer)); size
More informationAssembly Language for Intel-Based Computers, 4 th Edition. Kip R. Irvine. Chapter 2: IA-32 Processor Architecture
Assembly Language for Intel-Based Computers, 4 th Edition Kip R. Irvine Chapter 2: IA-32 Processor Architecture Chapter Overview General Concepts IA-32 Processor Architecture IA-32 Memory Management Components
More informationFast access ===> use map to find object. HW == SW ===> map is in HW or SW or combo. Extend range ===> longer, hierarchical names
Fast access ===> use map to find object HW == SW ===> map is in HW or SW or combo Extend range ===> longer, hierarchical names How is map embodied: --- L1? --- Memory? The Environment ---- Long Latency
More informationAssembly Language: Function Calls" Goals of this Lecture"
Assembly Language: Function Calls" 1 Goals of this Lecture" Help you learn:" Function call problems:" Calling and urning" Passing parameters" Storing local variables" Handling registers without interference"
More informationLecture Dependable Systems Practical Report Software Implemented Fault Injection. July 31, 2010
Lecture Dependable Systems Practical Report Software Implemented Fault Injection Paul Römer Frank Zschockelt July 31, 2010 1 Contents 1 Introduction 3 2 Software Stack 3 2.1 The Host and the Virtual Machine.....................
More informationSystems Design and Implementation II.1 L4 API Crash Course Part I
Systems Design and Implementation II.1 L4 API Crash Course Part I System, SS 2007 University of Karlsruhe 22 April 2009 Jan Stoess University of Karlsruhe Tuesdays 17:30-19:00 Thursdays 15:45-17:15 SR-134,
More informationAssembly Language: Function Calls. Goals of this Lecture. Function Call Problems
Assembly Language: Function Calls 1 Goals of this Lecture Help you learn: Function call problems: Calling and urning Passing parameters Storing local variables Handling registers without interference Returning
More informationMICROPROCESSOR ALL IN ONE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)
MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 ALL IN ONE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Architecture of 80386 2 ARCHITECTURE
More informationSYSTEM CALL IMPLEMENTATION. CS124 Operating Systems Fall , Lecture 14
SYSTEM CALL IMPLEMENTATION CS124 Operating Systems Fall 2017-2018, Lecture 14 2 User Processes and System Calls Previously stated that user applications interact with the kernel via system calls Typically
More informationFalling in Love with EROS (Or Not) Robert Grimm New York University
Falling in Love with EROS (Or Not) Robert Grimm New York University The Three Questions What is the problem? What is new or different? What are the contributions and limitations? Basic Access Control Access
More informationAssembly Language for Intel-Based Computers, 4 th Edition. Chapter 2: IA-32 Processor Architecture Included elements of the IA-64 bit
Assembly Language for Intel-Based Computers, 4 th Edition Kip R. Irvine Chapter 2: IA-32 Processor Architecture Included elements of the IA-64 bit Slides prepared by Kip R. Irvine Revision date: 09/25/2002
More informationAssembly Language for Intel-Based Computers, 4 th Edition. Chapter 2: IA-32 Processor Architecture. Chapter Overview.
Assembly Language for Intel-Based Computers, 4 th Edition Kip R. Irvine Chapter 2: IA-32 Processor Architecture Slides prepared by Kip R. Irvine Revision date: 09/25/2002 Chapter corrections (Web) Printing
More informationRegister Allocation, iii. Bringing in functions & using spilling & coalescing
Register Allocation, iii Bringing in functions & using spilling & coalescing 1 Function Calls ;; f(x) = let y = g(x) ;; in h(y+x) + y*5 (:f (x
More informationProcedure Calls. Young W. Lim Sat. Young W. Lim Procedure Calls Sat 1 / 27
Procedure Calls Young W. Lim 2016-11-05 Sat Young W. Lim Procedure Calls 2016-11-05 Sat 1 / 27 Outline 1 Introduction References Stack Background Transferring Control Register Usage Conventions Procedure
More informationL4 Nucleus Version X Reference Manual. x86
L4 Nucleus Version X Reference Manual x86 Version X.0 Jochen Liedtke Universität Karlsruhe liedtke@ira.uka.de September 3, 1999 Under Construction How To Read This Manual This reference manual consists
More informationFast access ===> use map to find object. HW == SW ===> map is in HW or SW or combo. Extend range ===> longer, hierarchical names
Fast access ===> use map to find object HW == SW ===> map is in HW or SW or combo Extend range ===> longer, hierarchical names How is map embodied: --- L1? --- Memory? The Environment ---- Long Latency
More information3. Process Management in xv6
Lecture Notes for CS347: Operating Systems Mythili Vutukuru, Department of Computer Science and Engineering, IIT Bombay 3. Process Management in xv6 We begin understanding xv6 process management by looking
More informationSystems Architecture I
Systems Architecture I Topics Assemblers, Linkers, and Loaders * Alternative Instruction Sets ** *This lecture was derived from material in the text (sec. 3.8-3.9). **This lecture was derived from material
More informationBuffer Overflow Attack
Buffer Overflow Attack What every applicant for the hacker should know about the foundation of buffer overflow attacks By (Dalgona@wowhacker.org) Email: zinwon@gmail.com 2005 9 5 Abstract Buffer overflow.
More informationx86 segmentation, page tables, and interrupts 3/17/08 Frans Kaashoek MIT
x86 segmentation, page tables, and interrupts 3/17/08 Frans Kaashoek MIT kaashoek@mit.edu Outline Enforcing modularity with virtualization Virtualize processor and memory x86 mechanism for virtualization
More informationMICROPROCESSOR MICROPROCESSOR ARCHITECTURE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)
MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 MICROPROCESSOR ARCHITECTURE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Introduction
More informationIA-32 Architecture COE 205. Computer Organization and Assembly Language. Computer Engineering Department
IA-32 Architecture COE 205 Computer Organization and Assembly Language Computer Engineering Department King Fahd University of Petroleum and Minerals Presentation Outline Basic Computer Organization Intel
More informationMemory Models. Registers
Memory Models Most machines have a single linear address space at the ISA level, extending from address 0 up to some maximum, often 2 32 1 bytes or 2 64 1 bytes. Some machines have separate address spaces
More informationAssembly Language for x86 Processors 7 th Edition. Chapter 2: x86 Processor Architecture
Assembly Language for x86 Processors 7 th Edition Kip Irvine Chapter 2: x86 Processor Architecture Slides prepared by the author Revision date: 1/15/2014 (c) Pearson Education, 2015. All rights reserved.
More informationOperating Systems and Protection CS 217
Operating Systems and Protection CS 7 Goals of Today s Lecture How multiple programs can run at once o es o Context switching o control block o Virtual Boundary between parts of the system o User programs
More informationAssembly I: Basic Operations. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Assembly I: Basic Operations Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Basic Execution Environment RAX RBX RCX RDX RSI RDI RBP RSP R8 R9 R10
More informationBasic Execution Environment
Basic Execution Environment 3 CHAPTER 3 BASIC EXECUTION ENVIRONMENT This chapter describes the basic execution environment of an Intel Architecture processor as seen by assembly-language programmers.
More informationCS 16: Assembly Language Programming for the IBM PC and Compatibles
CS 16: Assembly Language Programming for the IBM PC and Compatibles Discuss the general concepts Look at IA-32 processor architecture and memory management Dive into 64-bit processors Explore the components
More informationAccess. Young W. Lim Fri. Young W. Lim Access Fri 1 / 18
Access Young W. Lim 2017-01-27 Fri Young W. Lim Access 2017-01-27 Fri 1 / 18 Outline 1 Introduction References IA32 Operand Forms Data Movement Instructions Young W. Lim Access 2017-01-27 Fri 2 / 18 Based
More informationiapx Systems Electronic Computers M
iapx Systems Electronic Computers M 1 iapx History We analyze 32 bit systems: generalization to 64 bits is straigtforward Segment Registers (16 bits) Code Segment Stack Segment Data Segment Extra Ssegment
More informationWhat is a Compiler? Compiler Construction SMD163. Why Translation is Needed: Know your Target: Lecture 8: Introduction to code generation
Compiler Construction SMD163 Lecture 8: Introduction to code generation Viktor Leijon & Peter Jonsson with slides by Johan Nordlander Contains material generously provided by Mark P. Jones What is a Compiler?
More informationBoot Procedure. BP (boot processor) Start BIOS Firmware Load A2 Bootfile Initialize modules Module Machine Module Heaps
Boot rocedure Start BIOS Firmware Load A2 Bootfile Initialize modules Module Machine Module Heaps Module Objects Setup scheduler and self process Module Kernel Start all processors Module Bootconsole read
More informationW4118: PC Hardware and x86. Junfeng Yang
W4118: PC Hardware and x86 Junfeng Yang A PC How to make it do something useful? 2 Outline PC organization x86 instruction set gcc calling conventions PC emulation 3 PC board 4 PC organization One or more
More informationChapter 2. lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1
Chapter 2 1 MIPS Instructions Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 $s3 addi $s1,$s2,4 $s1 = $s2 + 4 ori $s1,$s2,4 $s2 = $s2 4 lw $s1,100($s2) $s1 = Memory[$s2+100]
More informationMachine and Assembly Language Principles
Machine and Assembly Language Principles Assembly language instruction is synonymous with a machine instruction. Therefore, need to understand machine instructions and on what they operate - the architecture.
More informationAccess. Young W. Lim Sat. Young W. Lim Access Sat 1 / 19
Access Young W. Lim 2017-06-10 Sat Young W. Lim Access 2017-06-10 Sat 1 / 19 Outline 1 Introduction References IA32 Operand Forms Data Movement Instructions Data Movement Examples Young W. Lim Access 2017-06-10
More informationAssembly Language Lab # 9
Faculty of Engineering Computer Engineering Department Islamic University of Gaza 2011 Assembly Language Lab # 9 Stacks and Subroutines Eng. Doaa Abu Jabal Assembly Language Lab # 9 Stacks and Subroutines
More informationMICROPROCESSOR ARCHITECTURE
MICROPROCESSOR ARCHITECTURE UOP S.E.COMP (SEM-I) OPERATING IN REAL MODE Prof.P.C.Patil Department of Computer Engg Matoshri College of Engg.Nasik pcpatil18@gmail.com. Introduction 2 Introduction The 80386
More informationProcedure Calls. Young W. Lim Mon. Young W. Lim Procedure Calls Mon 1 / 29
Procedure Calls Young W. Lim 2017-08-21 Mon Young W. Lim Procedure Calls 2017-08-21 Mon 1 / 29 Outline 1 Introduction Based on Stack Background Transferring Control Register Usage Conventions Procedure
More informationx86 architecture et similia
x86 architecture et similia 1 FREELY INSPIRED FROM CLASS 6.828, MIT A full PC has: PC architecture 2 an x86 CPU with registers, execution unit, and memory management CPU chip pins include address and data
More informationAn Introduction to x86 ASM
An Introduction to x86 ASM Malware Analysis Seminar Meeting 1 Cody Cutler, Anton Burtsev Registers General purpose EAX, EBX, ECX, EDX ESI, EDI (index registers, but used as general in 32-bit protected
More informationWe can study computer architectures by starting with the basic building blocks. Adders, decoders, multiplexors, flip-flops, registers,...
COMPUTER ARCHITECTURE II: MICROPROCESSOR PROGRAMMING We can study computer architectures by starting with the basic building blocks Transistors and logic gates To build more complex circuits Adders, decoders,
More information