User Guide. FA5 ICE RDI Driver. User Guide. Preliminary. Jan Version 0.1

Transcription

1 User Guide FA5 ICE RDI Driver User Guide Preliminary Jan Version 0.1

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3 Revision History Date Rev. Author Reason for rewrite Original conditions New conditions Sections effected Jan Jerry Huang Original Copyright Faraday Technology, All Rights Reserved. Printed in Taiwan 2003 Faraday and the Faraday Logo are trademarks of Faraday Technology Corporation in Taiwan and/or other countries. Other company, product and service names may be trademarks or service ma rks of othe rs. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support application where malfunction may result in injury or death to persons. The information contained in this document does not affect or change Faraday's product specification or warranties. Nothing in this document shall operate as an express or implie d lice ns e or inde m nity unde r the inte lle ctua l prope rty rights of Fa ra da y or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other ope rating e nvironme nts may va ry. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS. In no event will Faraday be liable for damages arising directly or indirectly from any use of the information contained in this document. Faraday Technology Corporation 10-2, Li-Hsin First Road S cie nce Ba s e d Indus tria l P a rk Hsinchu, Taiwan Faraday's home page can be found at: raday.com.tw

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5 Table of Contents 1. Introduction FA5 RDI Driver Components Connecting RDI Driver to Debugger Connect to AXD Debugger Connect to ARMSD Debugger Configuring FA5 RDI Dirver Processor Target Endian Cold Boot Reset System Stack & Heap Parameters Configuration File Format FA5 Coprocessor Register AXD Self Describe Coprocessor Register FA510 coprocessor FA526 Coprocessor ARMSD Debug Internal Variable fa5_cp15_instruction_extension fa5_cp15_tlb_operation fa5_cp15_tlb_lockdown fa5_cp15_tlb_test_operation...12 User Guide Version 0.1 / Jan i

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7 1. Introduction FA5 ICE provides debug facility to support users develop software program using Faraday FA510, FA526 CPU. The ICE contains one RDI driver to connect between debugger and ICE parser hardware. FA5 RDI driver follows ARM RDI (Remote Debug Interface) specification, so user can use ARM AXD (GUI interface) or ARMSD (command line interface) to connect to FA5 ICE parser through this RDI driver. RDI driver will detect CPU type automatically, so debugger uses the same RDI driver to connect to FA510 or FA526. FA5 ICE RDI driver supports Microsoft Windows 2000 and Windows XP operating system and is easy to install. This document contains information about configuration of FA5 ICE RDI driver. It also describes FA5-specific part of AXD and ARMSD. For the detail usage of AXD or ARMSD, please refer ARM Developer Suite User Guide. 1.1 FA5 RDI Driver Components FA5 RDI driver contains three files: fa5usb_rdi.dll - The RDI interface DLL driver. This is used to connect the FA5 ICE parser to ARM debuggers. fa5usb_rdi.cnf - The configuration file for RDI interface DLL driver. WinIO.sys - The parallel port driver for Windows 2000/XP. User can copy these three files to any directory user wants. Once configure debugger, just remember finding RDI driver in this directory. User Guide 1 Version 0.1 / Jan. 2004

8 2. Connecting RDI Driver to Debugger Before connecting FA5 RDI driver, user must ensure that FA5 ICE parser hardware already connects to PC running debugger. FA5 ICE parser hardware is parallel port interface. PC running debugger must configure its parallel port to ECP/EPP mode or EPP mode. 2.1 Connect to AXD Debugger If user has already activated FA5 RDI driver in AXD before, user needn t configure it again. AXD will connect to FA5 RDI driver automatically when it start up. If user hasn t use FA5 RDI driver before, user can add it by : 1. Select Options\Configure Target 2. Press Add to add the FA5 RDI driver fa5_rdi.dll. 2 User Guide Version 0.1 / Jan

9 3. Press OK, then AXD will try to connect to CPU through FA5 RDI driver. Once AXD connect to CPU successfully, user can read/write CPU register, coprocessor, memory etc. 2.2 Connect to ARMSD Debugger ARMSD is a command line debugger. If user wants to ativate FA5 RDI drvier with ARMSD, you can just write the command below : armsd target \user s directory\fa5_rdi.dll targetconfig \user s directory\fa5_rdi.cnf For the detail command, please refer ARM Debugger Guide. User Guide 3 Version 0.1 / Jan. 2004

10 3. Configuring FA5 RDI Dirver All the RDI driver configuration will been saved in the file fa5_rdi.cnf which located at the same directory of fa5_rdi.dll. AXD user can use configuration dialog to set the configuration. ARMSD user can set the configuration by directly modifying fa5_rdi.cnf file. When debugger tries to connect to CPU through FA5 ICE parser, RDI driver will get configuration and do the corresponding operation. The following figure shows the configuration window of AXD. 3.1 Processor Processor type this RDI driver support. Now only supports FA5 processor. 3.2 Target Endian User can specify whether the target is Little endian or Big endian using Target Endian radio buttons in the configuration dialog. 3.3 Cold Boot Reset Cold boot reset type of debugger. When debugger starts, it will call Cold Boot Reset to reset target CPU or let target CPU enter ICE mode only. User can select the cold boot reset method using Cold Boot Reset radio buttons in the configuration dialog. 4 User Guide Version 0.1 / Jan

11 External Reset System (CPU & Device) Enable the ICE parser to issue the CPU reset and Go ICE signal. Thus CPU and all system will be reset and enter ICE mode immediately. This is useful for debug Boot ROM code. Internal Reset System (CPU Only) Reset CPU only. CPU program counter and coprocessor register will be set to default value and enter ICE mode. The other system remains the same. Enter ICE Mode Only Enter ICE mode only. Do not issue any reset signal. 3.4 System Stack & Heap Parameters Continas four items : heap base, heap limit, stack base, stack limit. These four items are set to make semihosting work correctly. 3.5 Configuration File Format Tag Type Value Description CONTROLLER_RDIVERSION Value 151 RDI version TARGET_DIR String FA5 DLL directory string fa5_rdi.dll, fa5_rdi.cnf, WinIO.sys directory TARGET_DLL String FA5 DLL file name string RDI driver file name. PROCESSOR String Processor string Processor name ENDIANNESS Character B or L Processor is big or little endian RESET_MODE String ENTER_ICE or INTERNAL_RESET_CPU or EXTERNAL_RESET_SYSTEM Cold boot reset type STACKBASE Value Stack base value Target platform stack base value STACKLIMIT Value Stack limit value Target platform stack limit value HEAPBASE Value Heap base value Target platform heap base value HEAPLIMIT Value Heap limit value Target platform heap limit value User Guide 5 Version 0.1 / Jan. 2004

12 4. FA5 Coprocessor Register In AXD debugger, FA5 ICE RDI driver provides user to access coprocessor by its meaning. Thus user can easily modify register without checking processor datasheet. It also provides facility to make user to do cache and TLB operations. In ARMSD debugger, user can t see coprocessor meaning and can only see raw value of coprocessor register. But it can still use debug internal variables to do cache and TLB operations. 4.1 AXD Self Describe Coprocessor Register FA5 ICE RDI driver provides self describe coprocessor register. RDI driver will group FA5 coprocessor 8, 14 and 15 by function and show them in more detail fashion. User can change coprocessor reigster value by the clue provided by RDI driver. Section explains FA510 coprocessor register menaing, section explains FA526 coprocessor register meaning. The following figure shows one example of self describe register FA510 coprocessor FA510 RDI driver arranges coprocessor into 6 groups, the CP8,ICE, CP15, DRegions, IRegions and cache operation group. They are described below : 6 User Guide Version 0.1 / Jan

13 CP8 Group This group is responsible for reset and clock control. They all map to coprocessor 8 registers. Item name Access right Description CFG Read-only CR0, configuration register Reset Write-only CR1, CPU/Device soft reset register ICE Group This group is responsible for ICE debug facility. They all map to coprocessor 14 registers. Item name Access right Description Status (ISR) Read-only ICE status register Control (ICR) R/W ICE control register Data (IDR) R/W ICE data register Instruction (IR) R/W Instruction register Trap (ITR) R/W ICE trap register Restore (IRR) R/W ICE restore register Instruction (ICNT) R/W Instruction counter Cycle (CCNT) R/W Cycle counter I Break Base 0 R/W Instruction break register 0 (Base) I Break Base 1 R/W Instruction break register 1 (Base) I Break Mask 0 R/W Instruction break register 0 (Mask) I Break Mask 1 R/W Instruction break register 1 (Mask) D Break Base 0 R/W Instruction break register 0 (Base) D Break Base 1 R/W Instruction break register 1 (Base) D Break Mask 0 R/W Instruction break register 0 (Mask) D Break Mask 1 R/W Instruction break register 1 (Mask) CP15 Group This group will control FA510 MPU and show MPU status. They all map to coprocessor 15 registers. Item name Access right Description ID Read-only CR0-0, ID code register Type Read-only CR0-1, Cache type register Control R/W CR1, Configuration register DCacheable R/W CR2, Data cacheable control register ICacheable R/W CR2, Instruction cacheable control register Bufferable R/W CR3, Write buffer control register DProtection R/W CR5, Data region protection register User Guide 7 Version 0.1 / Jan. 2004

14 IProtection R/W CR5, Instruction region protection register D_LockDown R/W CR9, Data cache lockdown I_LockDown R/W CR9, Instruction cache lockdown DScratchpad R/W CR11, Data scratchpad configuration register IScratchpad CR11, Instruction scratchpad configuration R/W register ECR R/W CR14, Extension control register DRegions Group DRegions maps to coprocessor 15, register 6. FA510 can set 8 data regions at most. Each item in this group represents setting value of each region. IRegions Group IRegions maps to coprocessor 15, register 6. FA510 can set 8 instruction regions at most. Each item in this group represents setting value of each region. Cache Operations Group This group will do coprocessor 15, CR7 operations. Item name Access right Description Invalidate_IC Write-only Invalidate I-cache all Invalidate_IC_Entry Write-only Invalidate I-cache entry Prefetch_IC_Entry Write-only Prefetch I-cache entry Invalid_DC Write-only Invalidate D-cache all Invalid_DC_Entry Write-only Invalidate D-cache entry Clean_DC Write-only Clean D-cache all Clean_DC_Entry Write-only Clean D-cache entry Clean_Invalid_DC Write-only Clean and invalidate D-cache all Clean_Invalid_DC_Entry Write-only Clean and invalidate D-cache entry Sync Write-only SYNC (Drain write buffer) Wait for Interrupt Disable Wait for interrupt Invalid_BTB Write-only Invalidate BTB all Invalid_IS Write-only Invalidate I-Spad all FA526 Coprocessor 8 User Guide Version 0.1 / Jan

15 FA526 RDI driver arranges coprocessor into 8 groups : CP8, ICE, CP15, cache operations, TLB operations, MMU test, PTLB content, STLB content groups. CP8, ICE groups are the same as FA510. Others are described below. CP15 Group This group will control FA526 MMU and show MMU status. They all map to coprocessor 15. Item name Access right Description ID Read-only CR0-0, ID code register Type Read-only CR0-1, Cache type register TLB Type Read-only CR0-3, TLB type register Control R/W CR1-0, Configuration register ECR R/W CR1-1, Extension control register TTBR R/W CR2, Translation table base register DACR R/W CR3, Domain access control register FSR R/W CR5, Data fault status register PFSR R/W CR5, Prefectch fault status register FAR R/W CR6, Fault address register D_LockDown R/W CR9-0, Data cache lockdown I_LockDown R/W CR9-0, Instruction cache lockdown DScratchpad R/W CR9-1, Data scratchpad configuration register IScratchpad CR9-1, Instruction scratchpad configuration R/W register PID R/W Process ID register Cache Operations Group This group will do coprocessor 15, CR7 operations. Item name Access right Description Invalidate_IC Write-only Invalidate I-cache all Invalidate_IC_Entry Write-only Invalidate I-cache entry Prefetch_IC_Entry Write-only Prefetch I-cache entry Invalid_DC Write-only Invalidate D-cache all Invalid_DC_Entry Write-only Invalidate D-cache entry Clean_DC Write-only Clean D-cache all Clean_DC_Entry Write-only Clean D-cache entry Clean_Invalid_DC Write-only Clean and invalidate D-cache all Clean_Invalid_DC_Entry Write-only Clean and invalidate D-cache entry User Guide 9 Version 0.1 / Jan. 2004

16 Sync Write-only SYNC (Drain write buffer) Wait for Interrupt Disable Wait for interrupt Invalid_BTB Write-only Invalidate BTB all Invalid_IS Write-only Invalidate I-Spad all Invalid_IC_DC Write-only Invaildate ICache and DCache all TLB Operations Group This group will do coprocessor 15, CR8 and CR10 operation and can do TLB operation. Item name Access right Description Invalid_UTLB Write-only Invalidate UTLB all Invalid_UTLB_Entry Write-only Invalidate UTLB entry Translate_Lock_UTLB_Entry Write-only Translate and lock UTLB entry Unlock_UTLB Write-only Unlock UTLB all MMU Test Group This group will do coprocessor 15, register 15 operation and can be set to access TLB content. Item name Access right Description TLBI R/W TLB index register TLB Tag R/W TLB tag register TLB RAM1 R/W TLB RAM1 register TLB RAM2 R/W TLB RAM2 register PTLB Content and STLB Content Groups These two groups represent the content of TLB table. 4.2 ARMSD Debug Internal Variable FA510 coprocessor 15 register 7, FA526 coprocessor 15 register 7, register 8 and register 10 have many operations inside them. In AXD debugger, user can use self describe coprocessor to do these operations. But ARMSD debugger doesn t support self descirbe coprocessor and user can not just write raw coprocessor register to do all the operations. User must do the operation with debug internal variables. The following sections describe how to do coprocessor operation with debug internal variables fa5_cp15_instruction_extension 10 User Guide Version 0.1 / Jan

17 Both FA510 and FA526 coprocessor 15, register 7 operations can be achieved by two steps : 1. Set $fa5_cp15_instruction_extension 2. Write coprocessor 15, CR7. When FA5 RDI driver do write coprocessor 15, CR7, it will reference $fa5_cp15_instruction_extension value, and do the corresponding operation. The following table shows the mapping between $fa5_cp15_instruction_extension and CR7 operation. Function $fa5_cp15_instruction_extension Remark Invalidate I-cache all 0 Invalidate I-cache entry 1 Prefetch I-cache entry 2 Invalidate D-cache all 3 Invalidate D-cache entry 4 Clean D-cache all 5 Clean D-cache entry 6 Clean and invalidate D-cache all 7 Clean and invalidate D-cache entry 8 SYNC (Drain write buffer) 9 Wait for interrupt 10 Invalidate BTB all 11 Invalidate I-Spad all 12 Invalidate Icache and Dcache all 13 Only FA fa5_cp15_tlb_operation FA526 coprocessor 15, register 8 operations can be achieved by two steps : 1. Set $fa5_cp15_tlb_operation 2. Write coprocessor 15, CR8 When FA5 RDI driver do write coprocessor 15, C8, it will reference $fa5_cp15_tlb_operation value, and do the corresponding operation. The following table shows the mapping between $fa5_cp15_tlb_operation and CR8 operation. Function $fa5_cp15_tlb_operation Invalidate UTLB all 0 User Guide 11 Version 0.1 / Jan. 2004

18 Invalidate UTLB entry fa5_cp15_tlb_lockdown FA526 coprocessor 15, register 10 operations can be achieved by two steps : 1. Set $fa5_cp15_tlb_lockdown 2. Write coprocessor 15, CR10 When FA5 RDI driver do write coprocessor 15, CR10, it will reference $fa5_cp15_tlb_lockdown value, and do the corresponding operation. The following table shows the mapping between $fa5_cp15_tlb_lockdown and CR10 operation. Function $fa5_cp15_tlb_lockdown Translate and lock UTLB entry 0 Unlock UTLB all fa5_cp15_tlb_test_operation FA526 coprocessor 15, register 15 operations can be achieved by two steps : 1. Set $fa5_cp15_tlb_test_operation 2. Write coprocessor 15, CR15 or read coprocessor 15, CR15 When FA5 RDI driver do write coprocessor 15, C15, it will reference $fa5_cp15_tlb_test_operation value, and do the corresponding operation. The following table shows the mapping between $fa5_cp15_tlb_test_operation and CR15 operation. Function $fa5_cp15_tlb_test_operation TLB Tag 1 TLB RAM1 2 TLB RAM2 3 TLB Tag Match 4 12 User Guide Version 0.1 / Jan