ARM Trusted Firmware: Changes for Axxia

Transcription

1 ARM Trusted Firmware: Changes for Axxia atf_84091c4_axxia_1.39 Clean up klocwork issues, Critical and Error only, and only in code added to support Axxia. atf_84091c4_axxia_1.38 Allow non-secure access to the CCN registers. This is required, for example, to implement some work arounds. Add work around for CVE (Spectre Variant 4). This should only be enabled when building for Axxia Include WORKAROUND_CVE_2018_3639=1 on the make command line to enable the work around and WORKAROUND_CVE_2018_3639=0 to disable it. atf_84091c4_axxia_1.37 Enable PMU register access from EL0. atf_84091c4_axxia_1.36 Support unfused 6700 parts. atf_84091c4_axxia_1.35 Add a patch for CVE (Spectre/Meltdown) on atf_84091c4_axxia_1.34 Enable cache protection for Support the new B0 version of unfused A0 parts are not supported. Note that from this version on, atf_84091c4_axxia_1.33 Enable L1/L2 cache ecc correction on Add EDAC suppport for

2 atf_84091c4_axxia_1.32 Enable L1/L2 cache ecc protection. Not tested on Add new services for ccn504 for EDAC driver L3 accesses. atf_84091c4_axxia_1.31 Add support for L2 power control. When enabled, a cluster s L2 will be powered down when all cores in the cluster are disabled. Change the delay mentioned in the previous version to a cache flush. atf_84091c4_axxia_1.30 Updated support for AXC6700 power management. Adds a delay when powering down atf_84091c4_axxia_1.29 Initial support for AXC6700 power management. atf_84091c4_axxia_1.28 Update the commit log no code changes. atf_84091c4_axxia_1.27 If the last DDR retention reset was caused by timer 7, set bit 1 in the pscratch register. Fix compiler warnings when building with GCC 6. Don t reset the ELM trace buffer during DDR retention resets. Correct the peripheral clock speed calculation. atf_84091c4_axxia_1.26 Before disabling DSP clusters, flush the L2 cache. atf_84091c4_axxia_1.25 Flush the DSP cluster s L2 cache before disabling the cluster. 2

3 atf_84091c4_axxia_1.24 Increase the length of the CDC L2CC power down retry loop. The original length was too short in simulation. atf_84091c4_axxia_1.23 Further power management updates. L2 power control works but is not enabled by default pending investigation of the L2 reset logic. Flush all caches before initiating a DDR retention reset. Add OEM functions to get and set the ACTLR_EL3 and ACTLR_EL2. This is required for performance testing. atf_84091c4_axxia_1.22 Updates to 5600 power management. atf_84091c4_axxia_1.21 Do not power down the L2 cache during power management. atf_84091c4_axxia_1.20 Update power control. CPU off and on work on Fix error print when controlling DSP clusters on atf_84091c4_axxia_1.19 Add support for OEM functions. Support control of DSP clusters on 6700 using OEM functions. atf_84091c4_axxia_1.18 Use the correct address for CDC3. atf_84091c4_axxia_1.17 Add a function to control the DSPs. For now, this just enables DSP cluster 0. 3

4 atf_84091c4_axxia_1.16 Updates to the Run in Syscache feature. Works on 5600 but not atf_84091c4_axxia_1.15 Support the correct coherency bits on atf_84091c4_axxia_1.14 Remove debug print statements. atf_84091c4_axxia_1.13 Use the ARM physical timer to trigger DDR retention reset instead of the watchdog. atf_84091c4_axxia_1.12 DDR retention reset updates. atf_84091c4_axxia_1.11 Use chip instead of system reset. atf_84091c4_axxia_1.10 Do not use the SFONLY or HAM L3 states. To flush the L3 cache, use ON->OFF->ON instead of ON->SFONLY->ON. atf_84091c4_axxia_1.9 Add the peripheral clock frequency and baud rate to the parameters passed from the SPL. atf_84091c4_axxia_1.8 Support the 4th cluster on 5600 hardware. 4

5 atf_84091c4_axxia_1.7 Simplify the build options. The SPL will pass options indicating the target (5600 or 6700), the platform (simulation, emulation, or hardware), and options. Add support to boot without initializing system memory. atf_84091c4_axxia_1.6 Fix emulation boot problems introduced in 1.5. atf_84091c4_axxia_1.5 Switch from PSCI compat to native mode. Add code to power down cores, caches, and clusters. atf_84091c4_axxia_1.4 Add the DSP clusters to the coherency domain. atf_84091c4_axxia_1.3 Set the counter frequency for secondary cores. atf_84091c4_axxia_1.2 Instead of setting the counter frequency, use the frequency set by the SPL. atf_84091c4_axxia_1.1 Updated to the latest ARM Trusted Firmware (commit 84091c4) DDR Retention support Support for config ring accesses. 5

6 Get the last group when making interrupts accessible to Linux (non-secure) Increase the number of clusters required for XLF Clear the OS Lock for Secondary Cores Add a compile time option to leave the L3 cache in SFONLY. Only issue invalidate cache operations when memory is cacheable. Add coherency bits for the new (3.7) XLF emulation images Only issue clean and invalidate to cachable memory Changes for X9 Multi-Cluster in Simulation GIC address updates for XLF. Use the correct cluster mask bits for XLF Add a memory mapping for CCN on XLF. Don t enable IGRPEN1 during GIC initialization. Enabling IGRPEN1 causes XLF to fail, and isn t necessary on X9. 6

7 Use the same GIC addresses for simulation and emulation/hardware Implement PSCI reset. Add the other clusters to the coherency domain as needed Set the cluster coherency bits correctly for emulation. Flush the L3 cache in simulation Enable the L3 cache before starting U-Boot Handle simulation, emulation, and hardware differences at run time. Don t use a scratch register for the jump address, just jump to the base of LSM. Updated MMU setup for emulation Add cluster 0 to the coherency domain Change the Initial version. 7