Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems

Transcription

1 Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems Liang Shi, Chun Jason Xue and Xuehai Zhou Joint Research Lab of Excellence, CityU-USTC Advanced Research Institute, Suzhou, China Department of Computer Science and Technology, University of Science and Technology of China, Hefei, China Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong th IEEE Real-Time and Embedded Technology and Applications Symposium 1

2 Outline Introduction Related Works CFLRU BPLRU FAST scheme Proposed Scheme VM Management - WBC-LRU WBC Management - PCLRU Communication Between VM And WBC Simulation Conclusion 2

3 Introduction (1/2) Characteristics of flash memory Advantages small & lightweight shock resistance low power consumption Drawbacks asymmetric speed of read and write operations inability of in-place updates limited lifetime Reducing write activities on flash memory is an efficient way to improve the performance and endurance of flash memory. 3

4 Introduction (2/2) Management schemes on virtual memory have not yet considered the existence of WBC equipped in flash memory. Propose new management schemes for VM as well as WBC cooperatively for flash memory based systems to reduce write activities and to improve I/O performance. Experimental results show that the proposed strategies can reduce the number of write activities by 28.6% in average* improve I/O performance by 34.8% in average (* compared with CFLRU and BPLRU) 4

5 Related Works (1/3) VM management strategy CFLRU (Clean First Least Recently Used) evicts all the clean pages in a predefined window in the LRU model first Windows size is determined carefully so that the hit ratio of main memory can be kept in a bearable level. When there is no clean page in the window, a dirty page can be selected to evict. It postpones the evictions of all of the dirty pages. exploits the asymmetric speed of read and write operations of flash memory to reduce the number of write activities 5

6 Related Works (2/3) WBC management strategies BPLRU (Block Padding Least Recently Used) focuses on improving the performance of random write operation on flash memory uses block padding techniques to change random writes into sequential writes significantly reduces the number of erase operations on flash memory However, it also introduces additional read and write operations. 6

7 Fully Associative Sector Translation Layer (3/3) write sequence: p8, p12, p1, p5, p9, p13 B0 B1 B2 B3 L0 s block associativity: 4 L1 s block associativity: 4 Result 1. no block merge 2. high block associativity Problem: requires a large cost per block merge 7

8 Proposed Scheme (1/10) System Architecture Write operation write data into WBC flush dirty data to flash memory at the end Read operation can read data from both WBC and flash memory respectively 8

9 Proposed Scheme (2/10) All the pages with the same logic block number are linked into a single page cluster. The page clusters are logically partitioned into two parts based on the cluster size: large cluster set (LCS) part and small cluster set (SCS) part. LCS and SCS constitute the cluster set (CS) of the WBC. 9

10 Proposed Scheme (3/10) Virtual Memory Management CFLRU is not aware of WBC proposed algorithm: Write-Buffer-Cache aware LRU (WBC-LRU) delays the write back operations of dirty pages from VM to WBC when both of these conditions are met: The selected dirty page does not belong to the current CS of WBC. No new cluster can be added to the WBC. by evicting the pages belonging to WBC, WBC-LRU can increase the average size of clusters. 10

11 C - clean pages D - dirty pages Proposed Scheme (4/10) C1 does not belong to CS, so C1 is delayed. C2 belongs to CS, so C2 is selected to be written back to WBC. 11

12 Proposed Scheme (5/10) WBC-LRU (Cont.) also applies a window issue: window size» too large: too many read operations could be induced LCSthreshold limit the number of clusters in LCS is dynamically adjusted at run time» avoid the cases that WBC has not enough or excessive number of clusters 12

13 Proposed Scheme (6/10) CS CS = {C1,C3,C4, = {C1,C3,C5,C7,C8} C5,C7,C8} LCSthreshold = 43 NCLCS = 23 MRU LRU SCS C4 LCS C5 SCS C8 SCS C1 LCS C7 SCS C3 write buffer cache delay D C1 D C5 D C6 D C3 D C11 D C4 virtual memory window 13

14 Proposed Scheme (7/10) Write Buffer Cache Management Strategy proposed algorithm: Partition-Cluster LRU (PCLRU) cluster eviction is determined by the following rules: Large clusters at the LRU position can be evicted Small clusters should be given a chance to grow larger If the selected LRU cluster is a small cluster, cluster_tag is checked. if cluster_tag is set, evict; Otherwise, delay the eviction. 14

15 Proposed Scheme (8/10) MRU C11 C3 C9 C9 C7 C7 C2 C2 C4 C20 C4 C20 C12 C12 C3 S L L S SL L S SL L S S write buffer cache write page of C11 C3 NCLCS = 34 S: SCS L: LCS LRU NCLCS = C11 C3 C9 C7 C2 C4 C20 C12 S L L S L S L S 15

16 Proposed Scheme (9/10) Communication Between Virtual Memory and Write Buffer Cache VM is not able to communicate with WBC directly Sol: to simulate the actions of WBC in OS two approaches software approach» to amend current replacement algorithm of VM in OS by adding WBC-LRU mechanism to VM» to add a function in the page fault handler. All the data structures are updated only when dirty pages are written back to WBC.» Problem: software mechanism can be time-consuming 16

17 Proposed Scheme (10/10) hardware assisted approach» Add hardware signals to accelerate and simplify the processing hitting or missing signal evicting signal free of busy signal» only need to maintain LCSthreshold, NCLCS and CS for WBC-LRU. The proposed mechanisms can be implemented in software with VM, and simple hardware can be added to improve the implementation performance. 17

18 Simulation (1/7) Simulation Methodology trace-driven simulator contains a main memory paging system, a WBC, an FTL and a storage model with NAND flash memory 4GB NAND flash memory, 2KB per page, 64pages per block, 512 bytes per sector, and 4 sectors per page uses Valgrind on x86-linux machine to collect memory trace adopt fully-associative sector translation layer (FAST) as the FTL scheme 18

19 Comparing with LRU+BPLRU-PD and CFLRU(0.3)+BPLRU-PD Simulation (2/7) WBC-LRU(0.3)+PCLRU can increase the average size of destaged clusters by 1.38x and 1.42x on average reduce the number of destaged clusters by 37.5% and 24.1% on average WBC-LRU(0.7)+PCLRU can further increase the average size of destaged clusters by 1.56x and 1.61x on average reduce the number of destaged cluster by 49.2% and 39.5% on average 19

20 for the same window size, WBC-LRU can achieve higher hit ratio than CFLRU Comparing with LRU+BPLRU-PD and CFLRU+BPLRU-PD WBC-LRU(0.3)+PCLRU can increase the hit ratio by 8.3% and 11.7% on average WBC-LRU(0.7)+PCLRU can further increase the hit ratio by 15.5% and 18.9% on average Simulation (3/7) 20

21 Simulation (4/7) 21

22 Simulation (5/7) two sources for write operations in flash memory buffer write natural write operations from WBC s cluster evictions GC write resulting from merge operations copy and write operations to collect invalid pages 22

23 Simulation (6/7) 23

24 Simulation (7/7) 24

25 Conclusion This paper proposes cooperative VM and WBC management for flash based systems. For VM, designing a replacement algorithm, which is aware of the state information of the WBC. And for WBC, also designing an algorithm to cooperate with VM to increase the average size of destaged clusters. Simulation results show that the proposed strategies can reduce the number of writes and erases and improve I/O performance significantly compared with the best known techniques. 25