Training Platform. Reference Manual. Features tools for: Reference Manual

Transcription

1 Training Platform Features tools for: JTAG Boundary Scan JTAG Programming/Configuration Jennic JN Debugging Jennic JN Flash Programming Serial Memory - In System Programming Atmel AVR - In System Programming V1.0 Atomic Programming Ltd

2 Contents Contents...2 Introduction Board Layout Jumper Settings In SPI Programming Mode In Normal Mode Installation Accessing the Serial Port Configuration Hardware Clock Control Application Boundary Scan Testing Board Testing Using AP-SCAN Board Testing Using APEL Atmel AVR Microcontroller Hardware Generating Code for the AVR Programming the AVR Jennic JN5148 Module Hardware Flash Programming Using the Jennic Flash Programmer (Method 1) Programming the SPI Flash Directly (Method 2) Using GDB Altera CPLD Support Compiling the Source Modifying the JAM / SVF Files SVF File Modification EPM240T100 SVF Modification EPM3032AT44 SVF Modification JAM File Modification EPM240T100 JAM Modification EPM3032AT44 JAM Modification Programming the Training Platform SVF Programming JAM Programming Appendix 1: PCB Schematic...20 Appendix 2: Bill of Materials...21 Revision History...22 V1.0 Atomic Programming Ltd

3 1 Introduction This document lists the functionality available on the Atomic Programming Training Platform. 1.1 Board Layout The Training Platform is primarily a JTAG test platform built around three JTAG devices Atmel AtMega164PA (U1) with IO available on J3 and J4 Altera EPM240T100 CPLD (U2) with 16 LEDS Altera EPM3032AT44 (U3) with IO connected to both other devices. Additionally the board also has support for a Jennic JN5148 Wireless Microcontroller Module. The standard Jennic Interface connector (J6) is also provided. Both the AVR and the JN5148 can access the serial port provided by the FT232RL (U4) USB interface (J5 -Power). UART operation can be monitored using LED D17 and D18. 4 jumpers H1-4 determine the operating configuration. V1.0 Atomic Programming Ltd

4 1.2 Jumper Settings The Training Platform can be used in two modes (Normal and Programming Mode). This mode is controlled using the Clock Control Application (see Section 3.3) In SPI Programming Mode H1 Mode In Normal Mode 0 Atmel AVR Programming 1 JN5148 Flash Programming (Method 2) Table 1: SPI Programming Mode H2 H1 Mode 0 0 USB UART connected to AtMega164 Uart0 0 1 USB UART connected to AtMega164 Uart1 1 0 USB UART connected to JN5148 Uart0 1 1 USB UART connected to JN5148 Uart1 Table 2: UART Configuration H4 H3 Mode 0 0 GDB JTAG PORT to JN5148 Uart0 (H2 ignored) 0 1 GDB JTAG PORT to JN5148 Uart1 (H2 ignored) 1 0 GDB Disabled, UARTS Enabled 1 1 GDB Disabled, UARTS Disabled Table 3: GDB Configuration V1.0 Atomic Programming Ltd

5 2 Installation All reference material related to the Training Platform is included in the AP-Scan software installation. The latest version is available at All reference material will be installed to My Documents (or Documents in Vista and above) in a folder called Atomic Training Platform. This will include the following folders. 1) AVR - This folder will contain three folders i) AVRSVF A command-line utility for converting the SVF files from AVR Studio 4 ii) Getting Started Documentation This includes a getting started guide for AVR Studio, the ATMega164 datasheet and the instruction manual for the AVR. iii) LEDCycle A sample application for AVRStudio to get you started. 2) BSDL - BSDL files for the JTAG devices from the corresponding manufacturer. The information included in these files has already been imported into AP-Scan and APEL. 3) FT232R - Datasheet and MProg template used when configuring the device. 4) RTL - Verilog source for both CPLDS. The platform is pre-configured with these files 5) VB.NET - Sample application for controlling the operating mode on the Training Platform V1.0 Atomic Programming Ltd

6 3 Accessing the Serial Port The Training Platform is connected to a PC USB port using an FTDI FT232 device. The datasheet for this device is included in the training platform package. 3.1 Configuration The serial port can be connected to one of four UART interfaces. Two UARTS are available on the ATMega164PA and two are available on the JN5148 Module. See Table 2 for configuration details. 3.2 Hardware Two LEDs Rx and Tx (D17 and D18) give you the status of the data transferred through the serial port. These are connected to CB0 and CB1 on the FT232 respectively. Three other signals control the board. Signal CB4 is used as a clock source for the platform. Two signals (CB2 and CB3 are used to control the clock mode and also put the board into SPI programming mode. See table below. These signals can be controlled using the Clock Control Application (see Section 3.3). CB3 CB2 Operating Mode System Clock Source 0 0 SPI Programming Mode. 6MHz from FTR232R CB4 pin 0 1 Normal Mode 16MHz (from JN5148 DIO10) 1 0 Normal Mode ATMega164PA XTAL1 Output 1 1 Normal Mode 6MHz from FTR232R CB4 pin Table 4: Clock Control Modes 3.3 Clock Control Application An application has been included for the Training Platform that can access the Serial Port. A link has been included on the Windows Start Menu. Select the hardware from the list and click Connect. Once connected this utility has the following features: 1) Send and receive data to the serial port 2) Control the operating mode of the training platform This program has been written in VB.NET and compiled in Microsoft Visual Basic 2008 Express Edition that can be downloaded for free from the Microsoft web page. The source code has been included in the Atomic Training Platform Package. V1.0 Atomic Programming Ltd

7 4 Boundary Scan Testing 4.1 Board Testing Using AP-SCAN The Training Platform can be used with the AP-114 ISP/JTAG Programmer to demonstrate the AP- Scan Software. See the separate AP-114 and AP-Scan documentation for more details. In this mode the AP-114 connects using the standard 10-way JTAG connector J1. The training platform can be tested in both Normal and SPI Programming Mode. Note: The training data for both modes will be different. In the example above we can see: 1) The three devices in the scan chain. a. The AtMega164P has a yellow background that indicates that an event is still pending (i.e. waiting for a pin to go high (or low). A rule has been set up ensuring that this happens before the board is passed). b. The EPM240T100 device has a green background. This means that the device has passed all rules on all pins on the device. c. The EPM3032AT44 device has a pink background. This indicates that a rule on this device has been broken. 2) The Device window shows the selected device. The device is selected by clicking on the device in the Scan Chain window. The current status of each pin is shown. 3) The Pin Properties window has two purposes. a. Show rules attached to each pin. The pin is selected by clicking on the pin in the Device Window b. Show list of pins failures across all devices. Clicking on a failure in the list will select the device in the Device window and select the failed pins rules in the Pin Details window 4) The Operations window performs the following functions a. Allows tests to be run on the Board under Test (BUT) b. Allows the software to train itself against a known good board. This training data can then be saved to allow other boards to be tested. The software can also be controlled using ActiveX to allow integration into your own production systems such as LabVIEW. V1.0 Atomic Programming Ltd

8 4.2 Board Testing Using APEL The Training Platform can be used to demonstrate the APEL scripting language. The APEL language allows each pin of each device in the JTAG chain to be controlled independently and is useful for: 1) Testing devices that are not on the scan chain (sensors etc) 2) Programming devices that are not on the scan chain (flash memory etc). See APEL documentation for more details. In this mode the AP-114 connects using the standard 10- way JTAG connector J1. Below is an example of a test script using APEL This example generates patterns on the LEDS. It does this in the following way. 1) The Chain command defines the expected chain on the BUT (Board under test). 2) The Alias command (highlighted in yellow) defines a bus containing all 16 LEDs. This allows for easier control of them. The Alias command can be used to define address and data buses even when these pins are on different devices in the scan chain. 3) The FOR loop is used to cycle through all of the LEDS. 4) The bus defined on line 26 has a value applied to it on line 42. This is then loaded into the devices using the LOAD command 5) The CLOCK command is used to generate a delay by applying clock pulses to TCLK before moving onto the next line. Example scripts for the Training Platform are available on the webpage. V1.0 Atomic Programming Ltd

9 5 Atmel AVR Microcontroller The Atomic Training Platform has an ATMega164PA device included. The data sheet for this device has been included in the Atomic Training Platform package. 5.1 Hardware Two expansion connectors have been included to give access to the signals on the device. This allows the platform to be used to device your own applications Expansion Connector 1 Pin Signal Primary Function Secondary Functions 1 PA0 ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) 2 PA1 ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) 3 PA2 ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) 4 PA3 ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) 5 PA4 ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) 6 PA5 ADC5 (ADC input channel 5) PCINT5 (Pin Change Interrupt 5) 7 PA6 ADC6 (ADC input channel 6) PCINT6 (Pin Change Interrupt 6) 8 PA7 ADC0 (ADC input channel 7) PCINT0 (Pin Change Interrupt 7) 9 PB0 T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) 10 PB1 T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) 11 PB2 AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10) 12 PB3 AIN1 (Analog Comparator Negative Input) OC0A (Timer/Counter 0 Output Compare Match A Output) PCINT11 (Pin Change Interrupt 11) 13 PB4 SS (SPI Slave Select input) OC0B (Timer/Counter 0 Output Compare Match B Output) PCINT12 (Pin Change Interrupt 12) 14 PB5 MOSI (SPI Bus Master Output/Slave Input) PCINT13 (Pin Change Interrupt 13) 15 PB6 MISO (SPI Bus Master Input/Slave Output) PCINT14 (Pin Change Interrupt 14) 16 PB7 SCK (SPI Bus Master clock input) PCINT15 (Pin Change Interrupt 15) 17 PC0 SCL (2-wire Serial Clock Line) PCINT16 (Pin Change Interrupt 16) 18 PC1 SDA (2-wire Serial Data Input/Output Line) PCINT17 (Pin Change Interrupt 17) 19 PC6 TOSC1 (Timer Oscillator pin 1) PCINT22 (Pin Change Interrupt 22) 20 PC7 TOSC2 (Timer Oscillator pin 2) PCINT23 (Pin Change Interrupt 23) Table 5: J3 - First Expansion Connector for the AtMega164PA device NOTE: PC2-PC5 have not been included because they are the JTAG signals used as to connect the JTAG chain together and are not available for development. V1.0 Atomic Programming Ltd

10 Expansion Connector 2 Pin Signal Primary Function Secondary Functions 1 PD0 RXD0 (USART0 Receive Pin) PCINT24 (Pin Change Interrupt 24) 2 PD1 TXD0 (USART0 Transmit Pin) PCINT25 (Pin Change Interrupt 25) 3 PD2 INT0 (External Interrupt0 Input) RXD1 (USART1 Receive Pin) 4 PD3 INT1 (External Interrupt1 Input) TXD1 (USART1 Transmit Pin) 5 PD4 2 OC1B (Timer/Counter1 Output Compare Match B Output) 6 PD5 2 OC1A (Timer/Counter1 Output Compare Match A Output) 7 PD6 2 ICP1 (Timer/Counter1 Input Capture Trigger) 8 PD7 2 OC2A (Timer/Counter2 Output Compare Match A Output) PCINT26 (Pin Change Interrupt 26) PCINT27 (Pin Change Interrupt 27) XCK1 (USART1 External Clock Input/Output) PCINT28 (Pin Change Interrupt 28) OC2B (Timer/Counter2 Output Compare Match B Output) PCINT29 (Pin Change Interrupt 29) PCINT30 (Pin Change Interrupt 30) PCINT31 (Pin Change Interrupt 31) 9 RSTN A low level on this pin for longer than the minimum pulse length will generate a reset 10 AREF Analog reference pin for the analog-to-digital converter. 11 RXD 1 RxData signal (Data sent from the EPM240T100 to be received by the PC) 12 CB2 1 Clock Mode Control signal from FT232 Device 13 TXD 1 RxData signal (Data sent from the PC to the EPM240T100 device) 14 CB3 1 Clock Mode Control signal from FT232 Device 15 RTS 1 Request to Send signal from the PC 16 CB4 1 Clock source from FT232 Device 17 CTS 1 Clear to Send signal to be sent to the PC 18 - Not Connected 19 Vcc V cc 20 GND Ground Table 6: J4 - Second Expansion Connector for the AtMega164PA device NOTE 1: Pins signals are to/from the FT232 device (U4) NOTE 2: PD4-7 have the four switches SW1-SW4 mapped to them inside the EPM240T100 device 5.2 Generating Code for the AVR Code can be developed for the AVR using AVR Studio 4, which is free to download from the Atmel Web Page. To ease your development, the AVR instruction set and novice guide to building Applications for the AVR have been included in the Atomic Training Platform package. A sample application has also been included. This code is pre-programmed in the device. V1.0 Atomic Programming Ltd

11 5.3 Programming the AVR The AVR can be programmed in two ways. 1) Use AVFSVF.exe (included with the Atomic Training Platform package) to convert your output from AVR Studio 4 into an SVF file that can be used to program the AVR using the SVF Player. This method uses the JTAG chain to program and is therefore, only suitable for AVR devices that have a JTAG interface. Connect the 10-way header from the AP-114 to J1on the Training Platform. 2) Use the ApAVR Application as shown below. This application uses SPI mode Programming. To use this mode on the Training Platform: a. Connect the 10-way header from the AP-114 to J2 on the Training Platform b. Set Jumper H1 to 0 c. Put the Training Platform into SPI programming mode. See section V1.0 Atomic Programming Ltd

12 6 Jennic JN5148 Module Mezzanine connectors have been included on the training platform to support Jennic JN5148-M0X modules that come with the JN5148 EK010 Evaluation Kit. 6.1 Hardware The standard Jennic 40-way connector has also been included. Details are given below 2 J Pin Signal Primary Function Secondary Function 1 DIO 0 SPI Slave Select 1 (output) Digital I/O 2 DIO 1 SPI Slave Select 2 (output) Digital I/O 3 DIO 2 SPI Slave Select 3 (output) Digital I/O 4 DIO 3 SPI Slave Select 4 (output) Digital I/O 5 DIO 4 UART0 Clear To Send (input) Digital I/O 6 DIO 5 UART0 Request To Send (input) Digital I/O 7 DIO 6 UART0 Transmit Data (output) Digital I/O 8 DIO 7 UART0 Receive Data (input) Digital I/O 9 DIO 8 Timer0 clock/gate (input) Digital I/O 10 DIO 9 Timer0 capture (input) Digital I/O 11 DIO 10 Timer0 PWM (output) Digital I/O 12 DIO 11 Timer1 clock/gate (input) Digital I/O 13 DIO 12 Timer1 capture (input) Digital I/O 14 DIO 13 Timer1 PWM (output) Digital I/O 15 DIO 14 SIF_CLK/IP_CLK Digital I/O 16 DIO 15 SIF_DATA/IP_DO Digital I/O 17 DIO 16 IP_DI Digital I/O 18 DIO 17 UART1 Clear To Send (input)/ip_sel Digital I/O 19 DIO 18 UART1 Request To Send (input)/ip_int Digital I/O 20 DIO 19 UART1 Transmit Data (output) Digital I/O 21 DIO 20 UART1 Receive Data (input) Digital I/O 22 SCLK SPI Master Clock Out / Slave Clock In 23 MISO SPI Master In / Slave Out 24 MOSI SPI Master Out / Slave In 25 SSZ SPI Select Out from JN SSM SPI Select In to FLASH device 27 RESETN Active Low Reset See note below 28 C1P [+] 29 C1M [-] 30 C2P [+] 31 C2M [-] Comparator inputs Comparator inputs 32 DAC1 Digital to Analogue output V1.0 Atomic Programming Ltd

13 33 DAC2 Digital to Analogue output 34 ADC1 Analogue to Digital input 35 ADC2 Analogue to Digital input 36 ADC3 Analogue to Digital input 37 ADC4 Analogue to Digital input 38 GND Ground 39 VCC V cc 40 GND Ground Table 7: Expansion Connector Pinout Note Pin 27 If used as an output, this line will go low when the reset switch is pressed. The line may also be used to reset external devices simultaneously. Alternatively as an input, it can be shorted to ground to allow external devices to force a system reset. 6.2 Flash Programming There are two ways of programming the Flash memory on the JN5148 Module. Method 1 will be familiar to Jennic customers. This uses the Jennic Flash Programming Utility and the serial port on the Training Platform Method 2 demonstrates using the ApPC software to program the SPI flash device directly, This faster method would be recommended for production applications Using the Jennic Flash Programmer (Method 1) The hardware should be set up as follows H2 H1 Mode H4 H3 Mode 0 0 USB UART connected to AtMega164 Uart0 0 0 GDB JTAG PORT to JN5148 Uart0 0 1 USB UART connected to AtMega164 Uart1 0 1 GDB JTAG PORT to JN5148 Uart1 1 0 USB UART connected to JN5148 Uart0 1 0 GDB Disabled, UARTS Enabled 1 1 USB UART connected to JN5148 Uart1 1 1 GDB Disabled, UARTS Disabled Table 8: Jumper Settings for Jennic Flash mode programming To put the device into programming mode, follow the procedure below with power applied to the platform: 1. Hold down the reset button (SW5). 2. Hold down the programming button (SW6). 3. Release the reset button. 4. Release the programming button. The device should now be in programming mode and awaiting commands from the Flash programming utility. Once the device has been programmed, to exit programming mode, press and release the reset button. Note: For details of how to use the Flash programming utility, refer to the Jennic Flash Programmer Application User Guide (JN-UG-3007). V1.0 Atomic Programming Ltd

14 6.2.2 Programming the SPI Flash Directly (Method 2) To use this mode 1) Run the Clock Control application from the Windows Start Menu and put the Training Platform into SPI Programming Mode. 2) The hardware should be set up as follows H1 Mode 0 Atmel AVR Programming 1 JN5148 Flash Programming (Method 2) Table 9: Jumper Settings for SPI mode programming 3) Connect the AP-114 to the 10-way JTAG connector J2 4) Run the ApPC Software as normal, selecting the device package type as ISP 6.3 Using GDB Before you start you must enable the JTAG interface on the JN5148 by programming a small program into the JN5148 (see JN-AN-1118-JN514x-JTAG-Application-Debug.pdf included in the Training Platform documentation) Once this is complete one of the following two modes should be used depending on which UART port is required. H2 H1 Mode H4 H3 Mode 0 0 USB UART connected to AtMega164 Uart0 0 0 GDB JTAG PORT to JN5148 Uart0 0 1 USB UART connected to AtMega164 Uart1 0 1 GDB JTAG PORT to JN5148 Uart1 1 0 USB UART connected to JN5148 Uart0 1 0 GDB Disabled, UARTS Enabled 1 1 USB UART connected to JN5148 Uart1 1 1 GDB Disabled, UARTS Disabled Table 10: Jumper Settings for GDB Debug mode 1) Connect the AP-114 to the 10-way JTAG connector J2 2) Follow the example in JN-AN-1118-JN514x-JTAG-Application-Debug.pdf V1.0 Atomic Programming Ltd

15 7 Altera CPLD Support 7.1 Compiling the Source The source code for the EPM3032AT and the EP240T100 has been included (along with the Altera Quartus project) and has been tested using Altera Quartus II 8.0 and 9.0 web editions. This software is free to download from the Altera website. 7.2 Modifying the JAM / SVF Files The standard JAM and SVF files generated by Quartus II assume that only that device is in the JTAG chain. On the Training Platform there are three devices in the chain. The JAM/SVF file will need modifying to allow for this. The scan chain on the Training Platform is: For example, when we are programming the EPM240T100 we need account for the lengths of the instruction and data chains in the other two devices. During programming, the other devices are put into bypass mode. This means that their data chain length is 1. The instruction length can be found from the BSDL file for the device. If the device already exists in the boundary scan software then chain length details can be viewed using the library function. In our system the instruction lengths are: Device Instruction Chain Length AtMega164PA 4 EPM240T EPM3032AT44 10 Table 11: BSDL Instruction chain lengths on the Training Platform SVF File Modification The four commands to modify the chain are I) HDR - Add data to the header of the data chain II) TDR - Add data to the trailer of the data chain III) HIR - Add data to the header of the instruction chain IV) TIR - Add data to the trailer of the instruction chain V1.0 Atomic Programming Ltd

16 7.2.2 EPM240T100 SVF Modification For the EPM240T100 there is one device before in the chain and one device after. For the instruction chain there are 10 bits (EPM3032AT44) before the device and 4 bits (AtMega164PA) after the device. We also want TDI to be high during these cycles so that the bypass command is loaded. Our instruction commands are: HIR 10 TDI(3FF); // 10 bits long loading 10 '1's in the instruction register of the EPM3032AT44 TIR 4 TDI(F) ; // Four bits long loading four '1's into the instruction register of the AtMega164PA We have now set the data chain lengths to 1 so our data commands are: HDR 1 TDI(0); TDR 1 TDI(0) ; // One bit long for the EPM3032AT44. The value loaded on TDI is not important // One bit long for the AtMega164PA. The value loaded on TDI is not important These modifications have been made at line 28 of main_epm240.svf EPM3032AT44 SVF Modification For the EPM3032AT44 there is two devices before in the chain and none after. For the instruction chain there are 10 bits (EPM3032AT44) and 4 bits (AtMega164PA) before the device. We also want TDI to be high during these cycles so that the bypass command is loaded. Our instruction commands are: HIR 0 TDI(0); TIR 14 TDI(3FFF); // No Instruction Header Required // Four bits long loading four '1's into the instruction register of the AtMega164PA We have now set the data chain lengths to 1 so our data commands are: HDR 0 TDI(0); // No Data Header Required TDR 2 TDI(3) ; // Two 1 bit registers both set to 1 These modifications have been made at line 32 of EPM3032A.svf JAM/STAPL File Modification The four commands to modify the chain are PREDR POSTDR PREIR POSTIR - Add data to the header of the data chain - Add data to the trailer of the data chain - Add data to the header of the instruction chain - Add data to the trailer of the instruction chain EPM240T100 JAM/STAPL Modification For the EPM240T100 there is one device before in the chain and one device after. For the instruction chain there are 10 bits (EPM3032AT44) before the device and 4 bits (AtMega164PA) after the device. We also want TDI to be high during these cycles so that the bypass command is loaded. Our instruction commands are: PREIR 10; // 10 bits long loading 10 '1's in the instruction register of the EPM3032AT44 POSTIR 4; // Four bits long loading four '1's into the instruction register of the AtMega164PA V1.0 Atomic Programming Ltd

17 We have now set the data chain lengths to 1 so our data commands are: POSTDR 1; // One bit long for the AtMega164PA. PREDR 1; // One bit long for the EPM3032AT44. These procedure have been added to main_epm240.jam PROCEDURE DO_INIT_CONFIGURATION USES TEMP_DATA; PRINT "Configuring For Training Platform"; PREIR 10; POSTIR 4; PREDR 1; POSTDR 1; V146 = 1; ENDPROC; This procedure has been added to each of the actions defined in the JAM file ACTION PROGRAM = L0, DO_BLANK_CHECK OPTIONAL, DO_VERIFY RECOMMENDED, DO_SECURE OPTIONAL, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_BYPASS_CFM OPTIONAL, DO_BYPASS_UFM OPTIONAL, DO_REAL_TIME_ISP OPTIONAL, DO_READ_USERCODE OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION BLANKCHECK = L17, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_BYPASS_CFM OPTIONAL, DO_BYPASS_UFM OPTIONAL, DO_REAL_TIME_ISP OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION VERIFY = L18, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_BYPASS_CFM OPTIONAL, DO_BYPASS_UFM OPTIONAL, DO_REAL_TIME_ISP OPTIONAL, DO_READ_USERCODE OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION ERASE = L24, DO_BLANK_CHECK OPTIONAL, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_BYPASS_CFM OPTIONAL, DO_BYPASS_UFM OPTIONAL, DO_REAL_TIME_ISP OPTIONAL, DO_INIT_CONFIGURATION, L27; EPM3032AT44 JAM/STAPL Modification For the EPM3032AT44 there is two devices before in the chain and none after. For the instruction chain there are 10 bits (EPM3032AT44) and 4 bits (AtMega164PA) before the device. We also want TDI to be high during these cycles so that the bypass command is loaded. Our instruction commands are: POSTIR 14; PREIR 0; // Four bits long loading four '1's into the instruction register of the AtMega164PA // No Instruction Header Required V1.0 Atomic Programming Ltd

18 We have now set the data chain lengths to 1 so our data commands are: POSTDR 2; // Two 1 bit registers both set to 1 PREDR 0; // No Data Header Required These procedure have been added to epm3032a.jam PROCEDURE DO_INIT_CONFIGURATION USES TEMP_DATA; PRINT "Configuring For Training Platform"; PREIR 0; POSTIR 14; PREDR 0; POSTDR 2; ENDPROC; This procedure has been added to each of the actions defined in the JAM file ACTION PROGRAM = L0, DO_BLANK_CHECK OPTIONAL, DO_VERIFY RECOMMENDED, DO_SECURE OPTIONAL, DO_LOW_TEMP_PROGRAMMING OPTIONAL, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_READ_USERCODE OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION BLANKCHECK = L17, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION VERIFY = L18, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_READ_USERCODE OPTIONAL, DO_INIT_CONFIGURATION, L27; ACTION ERASE = L24, DO_BLANK_CHECK OPTIONAL, DO_DISABLE_ISP_CLAMP OPTIONAL, DO_INIT_CONFIGURATION, L27; 7.3 Programming the Training Platform The Training Platform can be programmed using either JAM or SVF files generated from Quartus II. Once these files have been modified (See Section 7.4) they can be programmed using the ApSelector Software included with ApPC SVF Programming 1) Connect the AP-114 to J1. 2) Start the Atomic AP-114 ISP Software 3) Select the SVF Player tab 4) Click 'Select FileName' and browse to the modified SVF file to program. 5) Add -v to the additional options so that we can watch what the SVF Player is doing. 6) Click Start V1.0 Atomic Programming Ltd

19 7.3.2 JAM Programming 1) Connect the AP-114 to J1 2) Start the Atomic AP-114 ISP Software 3) Select the JAM Player tab 4) Click 'Select FileName' and browse to the modified JAM file to use 5) The list of actions available in the JAM file will now be updated. Select PROGRAM from the pull-down list. 6) Add -v to the additional options so that we can watch what the SVF Player is doing 7) Click Start V1.0 Atomic Programming Ltd

20 Appendix 1: PCB Schematic V1.0 Atomic Programming Ltd

21 Appendix 2: Bill of Materials Item Qty Component Reference Description Manufacturer Manufacturer Part 1 14 C1, C8-19, C22 Capacitor 100nF 16V 0603 X7R PhyComp(Yageo) C2 Capacitor 10nF 0603 X7R EPCOS B37931K5103K C3-4 Capacitor 47pF 50V 0603 NPO PhyComp(Yageo) C20-21 Capacitor 10uF Tant Case A KEMET B45196H2106K D1-18 SMD LED PLCC-2 RED VISHAY TLMS3000-GS H1-4 Connector Header 3-Way 2.54mm pitch HARWIN M J1-2 Header SMT 2 X 5 Way TYCO J5 USB Mini-D SMT Molex J7-8 Header SMT 2 X 20 Way HARWIN M FE1 FERRITE BEAD, 0805 CASE, 60OHM Murata BLM21PG600SN1D R1-16, R22-23 Resistor 680R % PhyComp(Yageo) R17-20 Resistor 1K % Tyco CR1J1K0F 13 4 R24-27 Resistor 100K % PhyComp(Yageo) RC0603FR-07100KL 14 2 R28-29 Resistor 10K % PhyComp(Yageo) SW1-6 SMD Switch push button (Tactile) Multicomp DTSM-32S-B 16 1 SW7 SPDT Slide Switch Tyco SLS121PC U1 ATMEGA164PA-20AU Atmel ATMEGA164PA-20AU 18 1 U2 ATMEPM240T100C5N Altera EPM240T100C5N 19 1 U3 EPM3032ATC44 Altera EPM3032ATC44-7N 20 1 U4 FT232RL FTDI FT232RL 21 1 U5 LD1117AS33TR-V REG, LDO 3V3, SMD ST LD1117AS33TR V1.0 Atomic Programming Ltd

22 Revision History Version Date Description Jul-2010 First Release Important Notice Atomic Programming Ltd. reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time, and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders, and should verify that such information is current and complete. All products are sold subject to Atomic Programming s terms and conditions of sale, available at the time of order acknowledgment. Information relating to device applications, and the like, is intended as suggestion only and may be superseded by updates. It is the customer s responsibility to ensure that their application meets their own specifications. Atomic Programming Ltd. makes no representation and gives no warranty relating to advice, support or customer product design. Atomic Programming Ltd assumes no responsibility or liability for the use of any of its products, conveys no license or title under any patent, copyright to these products, and makes no representations or warranties that these products are free from patent, copyright or mask work infringement, unless otherwise specified. Atomic Programming Ltd s products are not intended for use in life support systems/appliances or any systems where product malfunction can reasonably be expected to result in personal injury, death, severe property damage or environmental damage. Customers of Atomic Programming Ltd. using or selling Atomic Programming products for use in such applications do so at their own risk and agree to fully indemnify Atomic Programming for any damages resulting from such use. All trademarks are the property of their respective owners. Atomic Programming Ltd 13 Springfield Avenue Sheffield. S7 2GA Tel/Fax: +44(0) Designed and manufactured in the UK V1.0 Atomic Programming Ltd