Lecture 7: Introduction to Co-synthesis Algorithms

Transcription

1 Design & Co-design of Embedded Systems Lecture 7: Introduction to Co-synthesis Algorithms Sharif University of Technology Computer Engineering Dept. Winter-Spring 2008 Mehdi Modarressi

2 Topics for today Chapter 2 of the book Co-synthesis Algorithms Introduction Preliminaries Hardware/Software Partitioning 2

3 Introduction to HW/SW Co-Synthesis Algorithms Introduction 3

4 Introduction Implementing a system? Why use CPU? Easier implementation ti Easier (and cheaper) to change and debug Why use hardware modules? Meeting other constraints performance, power consumption, etc Found a CPU meeting all non-functional constraints? Yes! What could be better? Use the CPU. No! Design custom logic, or a combination of both Design & Co-design of Embedded Systems 4

5 Introduction (cont d) Why more than one CPU or custom logic? Why not use the fastest available CPU? Design & Co-design of Embedded Systems 5

6 Introduction (cont d) Reason 1: Exponential cost per CPU performance Figure: 300 late-1996 retail prices of 250 Pentium Processor Cost (US $) Clock speed (MHz) Pentium processor prices Design & Co-design of Embedded Systems 6

7 Introduction (cont d)

8 Introduction (cont d) Exponential price/performance implies Paying for performance in a uni-processor is very expensive Using multiple small CPUs is cheaper Communication overhead is added, but still an economic choice Processors need not be CPUs. But special-function units. Special-purpose PEs can be even cheaper than dedicated CPU! Measured in system manufacturing cost, not necessarily in design cost Design & Co-design of Embedded Systems 8

9 Introduction (cont d) Reason 2: Scheduling overhead Switching overhead Reason 3: Power Design & Co-design of Embedded Systems 9

10 Introduction (cont d) Definition HW/SW co-synthesis: process of simultaneously design the SW architecture of an application and the HW architecture on which that SW is executed. Design & Co-design of Embedded Systems 10

11 Introduction (cont d) Problem Specification Co-Synthesis SW (app.) Arch. Communication i Channels HW Engine PE PE PE Mem Design & Co-design of Embedded Systems 11

12 Introduction (cont d) Hardware Architecture One or more Processing-Elements (PEs) Software (Application) Architecture includes Process structure Each process executes sequentially Determines The amount of parallelism The amount of communication Allocation of the processes onto PEs in the HW engine Communication channels Hardware elements Software primitives Fall 2005 Design & Co-design of Embedded Systems 12

13 Introduction to HW/SW Co-Synthesis Algorithms Preliminaries

14 Preliminaries Rate (execution rate) Maximum frequency at which a processing must be done Single-rate vs. Multi-rate Example of multi-rate system audio/video decoder Design & Co-design of Embedded Systems 14

15 Preliminaries (cont d) Latency Required maximum time between starting and finishing a processing task Design & Co-design of Embedded Systems 15

16 Behavior Models (cont d) Single-rate systems Standard model: Data Flow Graph (DFG) or FSM Not suitable to model multi-rate tasks Due to unified system state Design & Co-design of Embedded Systems 16

17 Behavior Models (cont d) Multi-rate systems Common model: Task Graph Task Graph Each Node: Process Each Edge: Communication Edge label: Communication rate P1 10 kb/s 50 kb/s P2 P3 Design & Co-design of Embedded Systems 17

18 Architectural Models (cont d) The hardware engine also needs a description HW-engine is another graph Generally: Processing Elements (PE) as nodes + communication channels as edges Problem: How to model busses? Solution: Nodes also used for channels Edges represents nets connecting PEs and channels Nodes are labeled with their type Design & Co-design of Embedded Systems 18

19 Architectural Models (cont d) CPU scheduling Process vs. thread (light-weight process) We use these terms interchangeably Scheduling policies to run multiple processes on a single CPU Non-preemptive vs. preemptive (prioritized) Time-slicing not normally used in embedded systems Design & Co-design of Embedded Systems 19

20 Introduction to HW/SW Co-Synthesis Algorithms Hardware/Software Partitioning

21 Introduction to HW/SW Partitioning The most important co-synthesis step Definition A HW/SW partitioning algorithm implements a specification on some sort of multiprocessor architecture Usually Multiprocessor architecture = one CPU + some ASICs on CPU bus or communication infrastructure 21

22 Platform-Based Design Design space Design space exploration Analyzing the set of possible designs and selecting a solution among the designs that meets the specifications Platform-base design Limiting the design space 22

23 Platform-Based Design In a platform Type of CPU is fixed and given Some useful peripherals and related drivers are given The communication infrastructure is given Custom hardware components (ASIC or FPGA) must be synthesized What function to implement on each ASIC? What characteristics should the implementation have? There are a programming and development tool Example: Xilinx EDK (Embedded Development Kit) for Virtex platforms. 23

24 PowerPC-Based Platform in Xilinx FPGAs 24

25 HW/SW Partitioning Partitioning decisions: Various ways of deciding on what task gets carried out in HW or SW depending on the design constraints and objectives. The simplest partitioning decision: CPU performs less computationally-intensive functions ASICs used to accelerate Computationally-intensive functions Frequently-used functions 25

26 HW/SW Partitioning Example for (i=0; i<10000;i++) s=s+a[i]*a[i]; [] [] b=1/sqrt(s); Multiply-accumulate is called 10,000 times (often used) 1/sqrt(s) is called only once (rarely used). inverse square root function should be implemented in SW multiply accumulate is implemented in HW 26

27 HW/SW Partitioning Partitioning decision for FSMD at coarser granularities Converting FSMD to probabilistic FSM model Adding the probability of each transition Calculate the probability of the system being in any given state S in some time n. Implement the frequently occurring states in hardware 27

28 HW/SW Partitioning Solving a probabilistic FSM Differential equations Monte Carlo Simulation 28

29 Solving a probabilistic FSM 29

30 Solving a probabilistic FSM Monte Carlo simulation More interesting way! Random-based simulation 30

31 Assignment Check the course webpage 31