Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool

Transcription

1 Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool Jin Hee Kim and Jason Anderson FPL 2015 London, UK September 3, 2015

2 2 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design cost saving compared to custom layout Manual layout is time costly Number of design rule increases as process decreases Completes VTR (Verilog-to-Routing) flow Flow currently ends after routing Architectures from VTR can be realized in silicon SoC integration Easily integrated Allows programmability on SoCs Democratizes access to FPGA fabrics Dominated by big companies Opens up FPGAs to other companies

3 3 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design cost saving compared to custom layout Manual layout is time costly Number of design rule increases as process decreases Completes VTR (Verilog-to-Routing) flow Flow currently ends after routing Architectures from VTR can be realized in silicon SoC integration Easily integrated Allows programmability on SoCs Democratizes access to FPGA fabrics Dominated by big companies Opens up FPGAs to other companies

4 4 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design cost saving compared to custom layout Manual layout is time costly Number of design rule increases as process decreases Completes VTR (Verilog-to-Routing) flow Flow currently ends after routing Architectures from VTR can be realized in silicon SoC integration Easily integrated Allows programmability on SoCs Democratizes access to FPGA fabrics Dominated by big companies Opens up FPGAs to other companies

5 5 FPGA Architecture Island-style FPGA block IO IO IO 6-LUT IO IO IO IO IO IO xbar 6-LUT 6-LUT IO IO IO Island-style FPGA

6 6 FPGA Architecture Horizontal and vertical routing tracks Switch block and connection block IO IO IO IO IO IO IO IO IO Switch IO IO IO Island-style FPGA Connection

7 7 Extensive Architecture (EArch) 1 Fracturable LUT 8 inputs (2 shared) 1 Luu, Jason. Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays. Diss. University of Toronto, 2014.

8 8 VTR Flow Takes Verilog circuits and places and route on an FPGA Currently VTR ends after routing Verilog Circuits Elaboration Odin II Synthesis & Tech Map ABC FPGA Architecture Description File Packing Placement VPR Routing Timing & Area Estimation Quality of Results

9 9 VTR Flow C code to extend VTR to generate RTL (Verilog) and bitstream Verilog Circuits Elaboration Odin II Synthesis & Tech Map ABC FPGA Architecture Description File Packing Placement Routing VPR FPGA Fabric RTL and Bitstream Generator Timing & Area Estimation Quality of Results

10 10 FPGA Fabric RTL Generation VTR represents the complete architecture in memory Walk the in-memory architecture model to generate Verilog for: blocks Intra-logic block routing Inter-logic block routing

11 11 Generating Verilog for blocks: Declare and instantiate modules from primitives (IO, LUT, ) 6-LUT LL U T F F F F F F F F F F F FPGA Element

12 12 Generating Verilog for Routing Intra-logic block routing: 6-LUT crossbar connectivity multiple edges connecting to one pin Inter-logic block routing: Switch Connection

13 13 Generating Verilog for Configuration Configuration cells () are attached to all MUXes and LUTs Switch Connection

14 14 Generating Verilog for Configuration Configuration cells are all connected like a shift register Number of configuration bits are in ~ for 20x20 FPGA Configuration Cell Chain

15 15 Bitstream Generation VTR stores placed and routed circuit in memory Follows the same order as RTL generation Configure LUTs and MUXes as necessary Connection

16 16 Bitstream Generation VTR stores placed and routed circuit in memory Follows the same order as RTL generation Configure LUTs and MUXes as necessary 0 1 Connection

17 17 ASIC Design Flow FPGA Fabric SDC FPGA Fabric RTL Synthesis: Synopsys Design Compiler Area Analysis Synthesized Netlist Technology Libraries Place and Route: Cadence Encounter GDSII Golden Netlist + Parasitic Capacitance Info Design SDC Timing Analysis: PrimeTime Delay Analysis

18 18 Synthesis: Constraints Area Top-level is not constrained For all other modules, constrain area to be minimum Set max area to 0 Timing Set clock frequency and input-to-output delays Cannot apply constraints with combinational loops Designs configured in FPGAs generally do not have loops Timing analysis tools does not know how to handle loops Need to break loops by disabling timing arcs Balanced Optimize for both area and timing

19 19 Synthesis: Constraints Area Top-level is not constrained For all other modules, constrain area to be minimum Set max area to 0 Timing Set clock frequency and input-to-output delays Cannot apply constraints with combinational loops Designs configured in FPGAs generally do not have loops Timing analysis tools does not know how to handle loops Need to break loops by disabling timing arcs Balanced Optimize for both area and timing

20 20 Synthesis: Constraints Area Top-level is not constrained 6- For all other modules, constrain area to be minimum Set max area to 0 Timing Set clock frequency and input-to-output xbar delays LUT Cannot apply constraints with combinational loops Designs configured in FPGAs generally do not have loops Timing analysis tools does not know how to handle 6- loops Need to break loops by disabling timing arcs LUT Balanced Optimize FPGA Top Level for both area and timing Breaking Combinational Loops LUT 6- F F 0 F F 1 F F n

21 21 Synthesis: Constraints Area Top-level is not constrained For all other modules, constrain area to be minimum Set max area to 0 Timing Set clock frequency and input-to-output delays Cannot apply constraints with combinational loops Designs configured in FPGAs generally do not have loops Timing analysis tools does not know how to handle loops Need to break loops by disabling timing arcs Balanced Optimize for both area and timing

22 22 Place and Route Placed and routed as a flat design VTR has certain notion of where each logic block is located but Encounter tool does not Floorplanning: blocks, IOs, and routing MUXes are floorplanned at their respective x and y location from VTR 85% utilization 2 Parasitic capacitances obtained 2 Kuon, Ian, and Jonathan Rose. "Measuring the gap between FPGAs and ASICs." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 26.2 (2007):

23 23 Floorplanning Impact FPGA with Floorplanning FPGA without Floorplanning

24 24 Floorplanning Impact Configuration Cells Configuration Cells FPGA with Floorplanning FPGA without Floorplanning

25 25 Floorplanning Impact clb_1_9 clb_1_8 clb_1_9 clb_1_8 FPGA with Floorplanning FPGA without Floorplanning

26 FPGA Layout 26

27 27 PrimeTime Timing analysis for design on FPGA Find critical path and delay When programmed, should not have loops Unused blocks should not be included Constraint file produced from VTR to imitate a programmed FPGA Disable timing arc Different than synthesis

28 28 PrimeTime: Programming Design IO IO IO IO IO IO Bloc k Bloc k Bloc k Bloc k Bloc k Bloc k Bloc k Bloc k Bloc k IO IO IO xbar 6-LUT 6-LUT 6-LUT 0 1 n IO IO IO Green line represents programmed path

29 29 PrimeTime: Programming Design IO IO Bloc k Bloc k 6-LUT 6-LUT 1 Bloc k IO The critical path now will be determined from the used paths

30 30 Verification Pre-synthesis Post-synthesis Post-place and route Verilog Circuit Random Vector Testbench Design Original = ModelSim VTR + RTL and Bitstream Generator FPGA Fabric RTL Bitstream Design FPGA Initialize configuration cells

31 31 Experimental Setup FPGA architecture 20 x 20 logic blocks 300 routing channel width 3 87% length 4 wires and 13% length 16 wires 3 EArch (no carry chain and no hard blocks) 1 FPGA fabric type Area-optimized Timing-optimized Balanced TSMC 65nm library 3 Murray, Kevin E., et al. "Titan: Enabling large and complex benchmarks in academic CAD." Field Programmable and Applications (FPL), rd International Conference on. IEEE, 2013.

32 32 Area Comparison Similar architecture to Altera s Stratix III 65nm process 10 fracturable LUTs 50% depopulated crossbar No carry-chain Stratix III LAB tile area 4 : mm 2 Can achieve relatively close area with area-optimized FPGA Fabric # of Std. Cells Total Area (mm 2 ) Tile Area (mm 2 ) Area-optimized 3,577, x Timing-optimized 7,521, x Balanced 5,298, x Tile Area Vs. Stratix III 4 Wong, Henry, Vaughn Betz, and Jonathan Rose. "Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture." Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2011.

33 33 Area Breakdown 100% 90% 7% 13% 20% 80% 70% 60% 50% 25% 25% 25% 2% 28% 1% Intra- Routing Inter- Routing (Buffers) 40% 30% 20% 10% 0% 40% 19% 14% 11% 7% 28% 21% 14% Area-optimized Timing-optimized Balanced Inter- Routing Configuration () Configuration (Routing)

34 34 Delay Comparison Experiment 1: Architecture delay (benchmark agnostic) L 0 : xbar LUT L 4 : length 4 wire xbar LUT L 16 : length 16 wire xbar LUT Experiment 2: Benchmark delay Design tool and architecture dependent

35 35 Delay Comparison: Architecture Average delay of paths in 6 different areas of FPGA 2.3x to 3.5x slower as the wire length grows FPGA Fabric L 0 (ns) L 4 (ns) L 16 (ns) Area-optimized Timing-optimized Balanced Stratix III

36 36 Delay Breakdown: Architecture 100% L 0 L 4 L 16 90% 80% 70% 60% 50% 40% 30% 20% Inter- Routing Intra- Routing 10% 0%

37 37 Delay Comparison: Design Benchmark Area-optimized (ns) Timing-optimized (ns) Balanced (ns) Stratix III (ns) alu apex des ex ex5p misex pdc seq spla diffeq dsip elliptic frisc tseng addshift fsm Geo. Mean Combinational circuits Sequential circuits 3.8x

38 38 Conclusion VTR extended to generate synthesizable FPGA fabric RTL and bitstream ASIC design flow used to synthesize 3 FPGA fabrics Area-optimized Timing-optimized Balanced Area-optimized fabric is 1.5x bigger than Stratix III Designs on timing-optimized fabric is 3.8x slower

39 Questions? 39