ADVANCE INFORMATION MACH4-32/MACH4LV-32
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1 MACH 4 FAMILY COM L: -7/0//5 IND: -0//4/ MACH4-3/MACH4LV-3 High-Performance EE CMOS Programmable Logic DISTITIVE CHARACTERISTICS 44 pins in PLCC, 44 and 4 pins in TQFP 3 macrocells 7.5 ns t PD Commercial, 0 ns t PD Industrial MHz f CNT 3 I/Os; dedicated inputs/clocks 3 flip-flops Up to 0 product terms per macrocell, with XOR Flexible clocking Two global clock pins with selectable edges Asynchronous mode available for each macrocell SpeedLocking for guaranteed fixed timing 5-V and 3.3-V supply voltage options JEDEC compatible for both 5-V and 3.3-V versions 5-V or 3.3-V in-system programmable through JTAG (IEEE Std. 49.) interface JTAG boundary scan testing capability Input and output switch matrices for high routability and pinout retention Zero-hold-time input register option Peripheral Component Interconnect (PCI) compliant (-7/-0/- speed grades) Enhanced features Bus-Friendly inputs and I/Os PAL Block programmable power-down mode for further power savings Individual output slew rate control Both 5-V and 3.3-V supply voltage options are safe for mixed supply voltage system designs Fully pin-out and function compatible with the MACHSP MACH 4 Family GENERAL DESCRIPTION The MACH4-3 (M4-3) and MACH4LV-3 (M4LV-3) are members of Vantis high-performance EE CMOS MACH 4 family. This device has the same macrocell capability of the popular MACHSP, with significant additional functional features. The M4-3 (M4LV-3) consists of 4 PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. Publication# 53 Rev: A Amendment/0 Issue Date: August 997 This document contains information on a product under development at Vantis. The information is intended to help you evaluate this product. Vantis reserves the right to change or discontinue work on this proposed product without notice.
2 V A N T I S The M4-3 (M4LV-3) has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic together on the same device. The two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. Up to 0 product terms per macrocell can be assigned. It is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. The M4-3 (M4LV-3) macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type, T-type, J-K, or S-R to help reduce the number of product terms used. The flip-flop can also be configured as a latch. The register type decision can be made by the designer using software. All macrocells can be connected to an I/O cell through the output switch matrix. The output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes. The M4-3 (M4LV-3) is fully pin-out and function compatible with the MACHSP. Each PAL block has a programmable power-down mode for further power saving of up to 50%; each I/O has an individually programmable output slew-rate control bit; and all inputs and I/Os feature the Bus-Friendly circuitry which weakly holds the voltage at the input to a logic low or high level depending on the last driven logic level. Both 5-V and 3.3-V supply operation versions are safe for mixed supply voltage system designs. The 3.3-V supply operation device has its power consumption significantly reduced due to the lower supply voltage, while providing the same high performance as the 5-V version. Vantis offers software design support for MACH devices through its own development system and device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and HP workstations under advanced operating systems such as Windows 3., Windows 95 and NT, SunOS and Solaris, and HPUX. MACHXL software is a complete development system for the PC, supporting Vantis' MACH devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and truth tables. Functional simulation and static timing analysis are also included in this easy-to-use system. This development system includes high-performance device fitters for all MACH devices. The same fitter technology included in MACHXL software is seamlessly incorporated into third-party tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MI. Interface kits and MACHXL configurations are also available to support design entry and verification with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology. These MACHXL configurations and interfaces accept EDIF.0.0 netlists, generate JEDEC files for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for design simulation. Vantis offers in-system programming support for MACH devices through its MACHPRO software enabling MACH device programmability through JTAG compliant ports and easy-to-use PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General. MACH4-3/3-7/0//5 MACH4LV-3/3-7/0//5
3 V A N T I S BLOCK DIAGRAM Block A I/O0 I/O7 I/O I/O5 Clock Generator 66 X 90 AND Logic Array and Logic Allocator MACH 4 Family CLK0/I0, CLK/I 6 6 Central Switch X 90 AND Logic Array and Logic Allocator Clock Generator I/O4 I/O3 Block B I/O6 I/O3 53A- MACH4-3/3-7/0//5 MACH4LV-3/3-7/0//5 3
4 V A N T I S CONNECTION DIAGRAM Top View 44-Pin PLCC I/O5 I/O6 I/O7 TDI CLK0/I0 TCK I/O I/O9 I/O0 I/O I/O7 I/O6 I/O5 I/O4 TDO CLK/I TMS I/O3 I/O I/O I/O I/O3 I/O4 I/O5 I/O6 I/O7 I/O I/O9 I/O0 I/O4 I/O3 I/O I/O I/O0 I/O3 I/O30 I/O9 I/O Block A Block B 53A- Note: Pin-compatible with the M4(LV)-64, MACHSP and MACHSP. PIN DESIGNATIONS CLK/I = Clock or Input = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 4 MACH4-3/3-7/0//5 MACH4LV-3/3-7/0//5
5 V A N T I S CONNECTION DIAGRAM Top View 44-Pin TQFP MACH 4 Family I/O I/O3 I/O4 I/O5 I/O6 I/O7 I/O I/O9 I/O I/O4 I/O3 I/O I/O I/O0 I/O3 I/O30 I/O9 I/O Block A I/O5 I/O6 I/O7 TDI CLK0/I0 TCK I/O I/O9 I/O0 I/O I/O7 I/O6 I/O5 I/O4 TDO CLK/I TMS I/O3 I/O I/O Block B A-3 Note: Pin-compatible with the M4(LV)-64, MACH SP and MACH SP. PIN DESIGNATIONS CLK/I = Clock or Input = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH4-3/3-7/0//5 MACH4LV-3/3-7/0//5 5
6 V A N T I S CONNECTION DIAGRAM Top View 4-Pin TQFP I/O I/O3 I/O4 I/O5 I/O6 I/O7 I/O I/O9 I/O0 I/O4 I/O3 I/O I/O I/O0 I/O3 I/O30 I/O9 I/O I/O5 I/O6 I/O7 TDI CLK0/I0 TCK I/O I/O9 I/O0 I/O I/O7 I/O6 I/O5 I/O4 TDO CLK/I TMS I/O3 I/O I/O A-4 Note: Pin-compatible with the M4(LV)-64. PIN DESIGNATIONS CLK/I = Clock or Input = Ground I = Input I/O = Input/Output V CC = Supply Voltage = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Trademarks Copyright 997 Advanced Micro Devices, Inc. All rights reserved. AMD, Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, MACH, MACHXL, MACHPRO and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.s 6 MACH4-3/3-7/0//5 MACH4LV-3/3-7/0//5
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