Page 1. ElapC5 05/11/2012 ELETTRONICA APPLICATA E MISURE 2012 DDC 1. C5 Bus protocols. Ingegneria dell Informazione

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1 Ingegneria dell Informazione C5 Bus protocols ELETTRONIC PPLICT E MISURE Dante DEL CORSO Indirizzamento rbitraggio Parametri di prestazione Trasferimenti source sync. Trasferimenti DDR C5 PROTOCOLLI DI» Indirizzamento» rbitraggio» Parametri di prestazioni» Trasferimenti source sync.» Trasferimenti DDR 05//202 - ElapC5-202 DDC 05//202-2 ElapC5-202 DDC C5 ddressing and allocation Services provided by the cycle level Single-slave: addressing techniques Multimaster systems: channel allocation llocation model and basic techniques (TP, CD, arb) Priority, starvation, fairness Bus performance analysis Performance improvement techniques References D. Del Corso: Elettronica per Telecomunicazioni: cap. 5.4 M. Zamboni: Elettronica dei sistemi di interconnessione, cap..4 Transfer of information units (byte, word,...), with compliance to timing specification for correct writing into destination register. Information comes from a SOURCE, and is stored at the DESTINTION Extended protocols allows to handle also -to-n and N-to-M asynchronous INF transfer (N-partner protocols) Cycles realize RED or WRITE operations The service uses power and requires time 05//202-3 ElapC5-202 DDC 05//202-4 ElapC5-202 DDC Definition of transaction Point-to-point systems Sequence of one or more cycles, which moves information units with an associated meaning (address, data, priority vector, ) Transaction level elements: : activates the operations SLVE: responds to Master commands Point-to-point: The two elements exchanging information are already defined. Write: M S () M S SLVE Read: S M 3 05//202-5 ElapC5-202 DDC 05//202-6 ElapC5-202 DDC Page 202 DDC

2 Multipoint systems (busses) Bussed systems Several units share the same physical channel. First operation: select participants in the transfer SLVE The system configuration can be modified by adding/removing boards OPEN MODULR systems ll units must follow the same protocol What is a protocol? set of rule which interfaces must abide to carry out a correct information transfer Parameters: Number of boards Speed and width of transactions (throughput) Physical and electric structure (connector, format, levels,..) 05//202-7 ElapC5-202 DDC 05//202-8 ElapC5-202 DDC Busses vs point-to-point Transaction protocol Point-to-point links Several connection ports on each unit, with independent physical channels Well defined electrical conditions Needs routing from one unit to next ones Better speed performance set of point-to-point can emulate a bus Multipoint/bussed links Single port on each unit, single physical channel Variable electrical conditions (number of boards o the bus) Needs allocation and addressing Better modularity Mandatory in multipoint systems (busses). Specific cycles to select participating units selection of slave: ddressing selection of master: llocation (of the channel) The actual information transfer can be carried out only after these cycles LLOCTION DDRESSING TRNSFER 05//202-9 ElapC5-202 DDC 05//202-0 ElapC5-202 DDC Single-master, N-slave systems ddressing techniques No need to identify the master (already there) The participating slave is selected with an DDRESSING operation SLVE Two degrees of freedom Coded/Decoded Coded: N bits select among 2 N elements» Memory cell selection Decoded: M bits select M elements (single- or therm. code)» Direct selection of registers,» Memory cell selection after address decoder Logic/Geographic (position) Selection depends from the name of the slave unit» Memory, register bank Selection depends o the position (backplane slot) of the unit» Configuration identification (at startup) 05//202 - ElapC5-202 DDC 05//202-2 ElapC5-202 DDC Page DDC 2

3 Structure of slave units Logic vs geographic addressing ddress decoder Recognizes address issued by the master Uses comparators, decoders, Timing and control Creates internal command Handles handshake (is async/semisync) and data buffers Core Register, memory, operating units, Data buffers Unit load toward the bus Proper bus driving/sensing ddressing mode Coded: each slave is enabled by a multibit code (address) Linear: each bit enables a single slave» Multiple slaves can be selected in a single cycle Logic addressing Each unit has an address independent from position» Wired or programmed on the board Geographical addressing Slave address depend on position in the bus» ddress defined on the connector 05//202-3 ElapC5-202 DDC 05//202-4 ElapC5-202 DDC Logic addressing Geographic addressing Wired code Wired code Independent select commands Board select coded select commands (address) Board select Independent select commands Board select coded select commands (address) Board select 05//202-5 ElapC5-202 DDC 05//202-6 ElapC5-202 DDC C5 ddressing and allocation Transfers in multimaster systems Single-slave: addressing techniques Multimaster systems: channel allocation llocation model and basic techniques (TP, CD, arb) Priority, starvation, fairness Bus performance analysis Performance improvement techniques In a multimaster/multislave system the first part of the transaction must select the active Master/Slave pair SLVE 05//202-7 ElapC5-202 DDC 05//202-8 ElapC5-202 DDC Page DDC 3

4 Channel allocation Model of the allocation system The master which is allowed to initiate a transaction is selected with an LLOCTION (RBITRTION) Request-allocator-grant chain Goal: avoid collisions SLVE 05//202-9 ElapC5-202 DDC 05// ElapC5-202 DDC llocation techniques Examples of allocation techniques Collision: access to a resource by two users at the same time Must be avoided preliminary channel allocation llocation with token passing Round robin passing of GRNT (no REQUEST evaluation) llocation with collision detection GRNT to all requesters collisions llocation with arbitration Evaluation of REQUEST No collision Deterministic access Group of people: collision many talk at same time Meeting (few people) Token passing: GRNT) assigned in round robin Independent from presence of request, can be rejected Unsupervised group When nobody id speaking, anybody can start to talk Possible collision; detect, stop, retry (CSM-CD) Supervised groups central RBITER evaluates requests GRNT assigned following a rule (time, priority, ) No collision, deterministic access 05//202-2 ElapC5-202 DDC 05// ElapC5-202 DDC Bus allocation with arbitration rbitration policy Token passing Networks: Logic token (permission to use the resource) exchanged among potential masters Ripple arbiters (Daisy chain): Physical token (logic state) CSM/CD: Carrier Sense Multiple cc. Collision Detection Used in networks rbitration: used for parallel buses Requires an RBITER Centralized vs Distributed High efficiency FCFS (first Come First Served) Cannot get infinite time resolution» Events may be too close to be distinguishable Needs also some other mechanism Priority Sequences of high priority requests can block the system Starvation Need for Fairness mechanisms Fairness lock can act also as synchronizer Examples in the following slides 05// ElapC5-202 DDC 05// ElapC5-202 DDC Page DDC 4

5 First Come First Served arbitration Priority arbitration Requests pile-up Start of service Requests pile-up Start of service 05// ElapC5-202 DDC 05// ElapC5-202 DDC Starvation Fairness Sampling of requests service samp serv samp Requests pile-up Starvation (3 and 4 blocked) 05// ElapC5-202 DDC 05// ElapC5-202 DDC Fairness procedure C5 ddressing and allocation Freeze status of requests Take a snapshot of requests Serve received request Do not accept new ones s all pending requests have been served, Take a new snapshot and freeze Single-slave: addressing techniques Multimaster systems: channel allocation llocation model and basic techniques (TP, CD, arb) Priority, starvation, fairness Bus performance analysis Performance improvement techniques Repeat the sequence 05// ElapC5-202 DDC 05// ElapC5-202 DDC Page DDC 5

6 rbitration circuits Selection of the Master & Slave Basic circuit: priority encoder Linear Centralized: Combinatorial network; ND gates, blocking from all higher levels Distributed: Daisy chain; ND, with blocking from next higher level Coded Centralized Distributed» Parallel»Serial» Self-selection circuits (based on wired logic) Operation : selection of Master (channel allocation) Operation 2: selection of Slave (addressing) SLVE 05//202-3 ElapC5-202 DDC 05// ElapC5-202 DDC ctual data transfer Performance of a bus M and S selection builds a virtual P-to-P channel The pair of unit carries out the information transfer in the following cycle(s) SLVE mount of information transferred in a time unit: THROUGHPUT (T) T = W x S W: bus width (parallel, num bit/cycle) S: bus speed (cycles/second) if the cycle/transaction uses a time tc, S = /tc Cycle duration t C depends from: Electrical parameters: t TX, t K Module parameters: t SU, t H, t WR, t EN,... Protocol (transitions/cycle, protocol type, ) 05// ElapC5-202 DDC 05// ElapC5-202 DDC Protocol performance analysis Multiplexed bus Synchronous protocol (RD/WR) Speed depend from slowest device, Cycle time depends from t K in write operations, Cycle time depends from t TX in read operations (without pipeline) synchronous protocol daptive speed, depends from speed of involved devices Cycle time depends from t TX, both for RD and WR Worst: Semisynchronous Must wait for possible Wait request: delay > 2 t TX Best: Source Synchronous For RD/WR both units must be able to handle control signals Basic structure for parallel bus ddress and Data use separate wires/tracks Driver/receiver, tracks on backplane, connector pins are expensive resources» Use space»use power Reduce the number of wires by using the same connection for different signals: MULTIPLEXED ddress, data, other information use the same wires at different times. 05// ElapC5-202 DDC 05// ElapC5-202 DDC Page DDC 6

7 Parallel vs multiplexed busses Cycle performance improvement Parallel: separate lines for address and data DDRESS DTI CYCLE DD X X X X DD2 TRNSCTION CYCLE DT DT2 Multiplexed: address, data, other information, over a unique set of lines INF CYCLE DD CYCLE DT TRNSCTION DD2 DT2 Read and Write cycles The complete cycle requires two state transitions in each control signals Power consumption depends from number of transitions Data bandwidth less than control bandwidth (one transition/cycle vs two/cycle) Reduce the number of transitions on control signals DDR cycles Double Data Rate Use both transitions on commands (STB and CK) Higher complexity Reduced power consumption, higher speed 05// ElapC5-202 DDC 05// ElapC5-202 DDC Dual-edge handshake (DDR) Source synchronous cycles Remove useless control signals transitions Reduce power consumption INF STB CK INF STB CK t C t C INF INF t C INF2 In WRITE cycles INF and STB move in the same direction (Master Slave) Two timing parameters: Cycle duration (inverse of cycle rate = num of cycles / sec) Latency of data (how long to wait to get data) Latency depends from the transmission time t TX and from the skew t K Cycle rate depends from the skew t K not from the transmission time t TX SS protocols are used for high speed RMs (SSTL-2) 05// ElapC5-202 DDC 05// ElapC5-202 DDC Burst transfer Burst transfer interface Locality of SW: In most cases a packet of data/instructions is transferred to/from sequential memory locations. Only first address is sent Long packets doubled amount of INF in the same time bus DD STB board DD Standard memory: address is provided directly from the bus. MEMORY ddress cycle Data cycle Data cycle2 Data cyclen Block transfer memory board: address is locally generated by a controller. INF DD DT DT2 DT3 TRNSCTION DD STB bus board CONTR. DD MEMORY 05//202-4 ElapC5-202 DDC 05// ElapC5-202 DDC Page DDC 7

Burst transfer: DDR memory Beyond Source Synchronous Source Synchronous DDR block transfer DQS (Data Strobe) driven by memory (dual edge) 2 clock cycles latency With Source Synchronous protocol SS

8 Burst transfer: DDR memory Beyond Source Synchronous Source Synchronous DDR block transfer DQS (Data Strobe) driven by memory (dual edge) 2 clock cycles latency With Source Synchronous protocol SS Read requires STB controlled by slave The access time is always there Better performance with pipeline latency cycle To increase speed the key is skew t K not t TX Skew comes from the use of separate physical channels (wires) for INF and STB How can we get rid of skew? Embedded clock and self-synchronizing modulations Code timing and INF on the same physical connection From parallel to multiple serial channels 05// ElapC5-202 DDC 05// ElapC5-202 DDC C5 final test When and why do we need an addressing operation? Which is the use of the geographic addressing? When and why do we need an allocation operation? Describe the operation of a bus arbiter Define the performance of a bus and the parameters which influence this performance. Which parameters define the minimum cycle time? Compare minimum cycle times of synchronous and asynchronous protocols. Describe the motivation of DDR protocols. Which are the benefits of multiplexed busses? Describe the benefits of block transfer transactions. 05// ElapC5-202 DDC Page DDC 8

ECE 551 System on Chip Design

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