High Speed Area Efficient VLSI Architecture for DCT using Proposed CORDIC Algorithm

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1 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: High Speed Area Effiient VLSI Arhiteture for DCT using Proposed CORDIC Algorithm Deepnarayan Sinha 1, Prashant Chaturvedi 1, Dr. Rita Jain 2 M. Teh Student (VLSI) & Professor, Department of Eletronis and Communiation Engineering, NCT Bhopal, M.P, India 1 Professor & HOD, Department of Eletronis and Communiation Engineering, NCT Bhopal, M.P, India 2 ABSTRACT: Low-power layout is one of the most vital hallenges to maximize battery life in portable devies and to save the energy during simulation operation. Image and video ompressor is widely used in Disrete Cosine Transform (DCT). Many types of tehniques are used in design disrete osine transform (DCT). Multiplier and adder are two main omponents in design to DCT, Loeffer (1989) have developed a new arhiteture DCT, it onsists of 11 multipliations and 29 additions. By now a day we required low hip area and fast speed algorithm, but the multiplier onsumed large area ompared to adder. We are designed to multiplier less CORDIC (Coordinate Rotation Digital Computer) algorithm based on DCT. CORDIC is a main omponent of shift and add for rotation vetor and plan whih is usually used for alulation of trigonometri funtions. CORDIC algorithm is effiient area and delay ompared to existing algorithms. All design are implementation Xilinx 1.1i and verified the result. KEYWORDS: - Disrete Cosine Transform, Disrete Fourier Transform, Coordinate Rotation Digital Computer I. INTRODUCTION For a long term the field of virtual signal Proessing has been dominated by Miroproessors. that is espeially due to the fat they provide designers with the blessings of unmarried yle multiply-gather eduation in addition to unique addressing modes. even though these proessors are reasonably-pried and bendy they are exeptionally slow on the subjet of performing sure disturbing signal proessing duties e.g. photograph Compression, virtual verbal exhange and Video Proessing. Of past due, rapid advanements were made inside the field of VLSI and IC layout. As a result unique purpose proessors with ustom-arhitetures have ome up. higher speeds an be performed by way of those ustomized hardware answers at ompetitive pries. to feature to this, numerous easy and hardware-effiient algorithms exist whih map niely onto those hips and an be used to deorate veloity and flexibility at the same time as appearing the favored signal proessing obligations [1][2][]. One suh easy and hardware-effiient algorithm is CORDIC, an aronym for Coordinate Rotation virtual omputer, proposed with the aid of Jak E Volder [. CORDIC uses only Shift-andAdd mathematis with table look-as muh as implement speial apabilities. with the aid of making moderate modifiations to the preliminary situations and the LUT values, it is able to be used to suessfully enfore Trigonometri, Hyperboli, Exponential features, Coordinate hanges and so on. the usage of the same hardware. sine it makes use of simplest shift-upload arithmeti, VLSI implementation of suh an set of rules is easily workable. DCT set of rules has numerous programs and is extensively used for photograph ompression. imposing DCT the use of CORDIC algorithm redues the range of omputations at some stage in proessing, inreases the auray of reonstrution of the piture, and dereases the hip viinity of implementation of a proessor onstruted for this reason. This redues the overall energy onsumption. FPGA provides the hardware environment wherein dediated proessors an be tested for their apability. They perform numerous high-speed operations that an not be realized via a simple miroproessor. The number one benefit that FPGA gives is On-web site 2 programmability. Therefore, it bureauray the suitable platform to put into effet and hek the apability of a ommitted proessor designed using CORDIC algorithm [5]. The advanes in IC generation have outstanding pastimes in developing speial reason, parallel proessor arrays suh systoli arrays had been extensively used. The basi arithmeti omputation of those parallel arrays has often been Copyright to IJIRSET DOI: /IJIRSET

2 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: implemented with a MAC, due to the fat those operations arise in DSP programs. The redution in hardware ost also motivated the development of sophistiated signal proessing algorithms whih want the assessment of apabilities together with trigonometri and logarithmi apabilities, whih annot be evaluated effetively with MAC based totally arithmeti gadgets. So whilst sign proessing algorithms ontain those fundamental funtions, it's far sure to observe signifiant overall performane failure. So an arithmeti omputing set of rules alled CORDIC (Coordinate Rotation virtual p) has aquired tremendous interest, beause it gives an iterative system to orretly alulate eah of these standard apabilities. Speially, all the evaluation duties in CORDIC are formulated as a rotation of vetors in various Coordinate systems. by means of varying a few parameters, the equal CORDIC proessor is apable of iteratively alulates those standard features the use of the idential hardware inside the idential quantity of implementation of pipelined VLSI array proessors. II. LITERATURE REVIEW CORDIC or Coordinate Rotation virtual laptop is a easy and hardware-green algorithm for the implementation of diverse simple, espeially trigonometri, funtions. Instead of using Calulus based totally methods suh as polynomial or rational useful approximation, it makes use of easy shift, upload, subtrat and table look-up operations to reap this goal. The CORDIC algorithm beome first proposed through Jak E Volder in it's also applied in both Rotation mode or Vetoring mode. In either mode, the algorithm is rotation of a perspetive vetor by way of a exat perspetive but in variable guidelines. This onstant rotation in variable diretion is arried out thru an iterative series of addition/subtration followed through bit-shift operation. The final result is aquired via as it should be saling the end result obtained after suessive iterations. Attributable to its simpliity the CORDIC set of rules an be without diffiulty implemented on a VLSI gadget. x ( 0 ) x ( ) x ( ) x ( ) x (1) x ( 6 ) x ( 2 ) x ( 5 ) X (1) X ( ) X (5 ) X () X ( 2 ) X (6 ) X (0 ) X ( ) Figure 1: 8-point Disrete Cosine Transform Hardware requirement and ost of CORDIC proessor is less as most effetive shift registers, adders and look-up table (ROM) are required range of gates required in hardware implementation, inlusive of on an FPGA, is minimal as hardware omplexity is greatly redued as ompared to different proessors together with DSP multipliers it's miles tremendously easy in layout No multipliation and only addition, subtration and bit-moving operation ensures simple VLSI implementation. Postpone worried for the duration of proessing is omparable to that in the implementation of a Copyright to IJIRSET DOI: /IJIRSET

3 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: department or retangular-rooting operation. Both if there is a lak of a hardware multiplier (e.g. uc, up) or there is a need to optimize the variety of logi gates (e.g. FPGA) CORDIC is the preferred hoie. III. DISCRETE COSINE TRANSFORM Disrete Cosine Transformation (DCT) is the most widely used transformation algorithm. DCT, first proposed by way of Ahmed [9] et al, 19, has got greater importane in urrent years, in partiular in the fields of photograph Compression and Video Compression. This hapter makes a speiality of green hardware implementation of DCT by way of reduing the variety of omputations, enhaning the auray of reonstrution of the unique information, and lowering hip plae. due to whih the eletriity onsumption additionally dereases. DCT also improves veloity, ompared to different trendy piture ompression algorithms like JPEG. DCT output F(0) 0.5( f (0) f (1) f (2) f () f () f (5) f (6) f ()) os F(1) 0.5[{( f (0) f ()}os { f (1) f (6)}os { f (2) 5 f (5)}os { f () f ()}os ] 2 F (2) 0.5[{( f (0) f () f () f ()}os { f (1) f (2) 6 f (5) f (6)}os ] F() 0.5[{( f (0) f ()}os { f (6) f (1)}os 5 { f (5) f (2)}os { f () f ()}os ] F () 0.5[( f (0) f () f () f () f (1) f (2) f (5) f (6))os ] 5 F(5) 0.5[{( f (0) f ()}os { f (6) f (1)}os { f (2) f (5)} os { f () f ()}os ] 6 F(6) 0.5[{( f (0) f () f () f ()}os { f (1) f (2) f (5) 2 f (6)}os ] 5 F() 0.5[{( f (0) f ()}os { f (6) f (1)}os { f (2) f (5)}os { f () f ()}os ] Copyright to IJIRSET DOI: /IJIRSET

4 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: IV. CORDIC ALGORITHM The simple form of CORDIC is based on observation that if a unit length vetor with at (x,y)=(1,0) is rotated by an angle degrees, its new end point will be at ( x, y) (sin, os ) thus oordinates an be omputed by finding the oordinates of new end point of the vetor after rotation by an angle. Rotation of any (x, y) vetor: Basi equation of CORDIC algorithm Rearrange equations (1) (2) () () Rotations and pseudo rotation: Consider the vetor in figure having one end point at O and other with Co-ordinates. If is rotated the origin by angle as shown in figure thaw end point will have oordinates satisfying. Figure 2 A pseudo rotation steps in CORDIC V. SIMULATION RESULT All of the designing and experiment onerning set of rules that we've noted in this paper is being advaned on Xilinx 1.1i updated version. Xilinx 9.2i has ouple of the hanging apabilities inluding low memory requirement, rapid debugging, and low prie. The present day release of ISETM (inorporated software environment) layout tool provides the low reminisene requirement approximate 2 perentage low. ISE 1.1i that offers advaned gear like smart bring Copyright to IJIRSET DOI: /IJIRSET

5 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: together tehnology with higher utilization in their omputing hardware gives faster timing losure and higher fine of results for a better time to designing answer. Figure : Resister transfer Level (RTL) View of 8-point DCT Table 1: Devie Utilization Mamatha I et Proposed al. Number of Register Numbe of Slie LUTs LUT-FF Pairs Number of DSP 8Es 2 - Number of IOBs Maximum Frequeny Operation 22.9MHz MHz Copyright to IJIRSET DOI: /IJIRSET

6 International Journal of Innovative Researh in Siene, Engineering and Tehnology Website: Number of Register 2500 Numbe of Slie LUTs LUT-FF Pairs Number of DSP 8Es Mamatha I et al. Proposed Number of IOBs Maximum Frequeny Operation Figure : Bar Graph of the 8-point DCT VI. CONCLUSION We found that CORDIC based DCT algorithm is the best algorithm in the existing algorithm. So we are implementation to CORDIC based DCT algorithm in this paper. The performane evaluation of the various sub modules are arried out using Xilinx 1.1 ISE Simulator and it was found that the iruits designed using DCT logi showed a redued delay and power. As a future work more arithmeti and logial funtion an be used. REFERENCES [1] Mamatha I, Nikhita Raj J, Shikha Tripathi, Sudarshan TSB, Systoli Arhiteture Implementation of 1D DFT and 1D DCT, /15/$ IEEE. [2] Liyi Xiao Member, IEEE and Hai Huang, Novel CORDIC Based Unified Arhiteture for DCT and IDCT, 2012 International Conferene on Optoeletronis and Miroeletronis (ICOM) /12/$ IEEE. [] Shymna Nizar N.S,Abhila and R Krishna, An Effiient Folded Pipelined Arhiteture For Fast Fourier Transform Using Cordie Algorithm, 201 IEEE International Conferene on Advaned Communiation Control and Computing Tehnologies (lcaccct) IEEE. [] E. Jebamalar Leavline, S.Megala2 and D.Asir Antony Gnana Singh, CORDIC Iterations Based Arhiteture for Low Power and High Quality DCT, 201 International Conferene on Reent Trends in Information Tehnology /1/$ IEEE. [5] Satyasen Panda, Performane Analysis and Design of a Disreet Cosine Transform proessor Using CORDIC algorithm, [6] Keshab K. Parhi, VLSI Digital Signal Proessing Systems, design and implementation, Wiley. [] Deepika Ghai, COMPAATIVE ANALYSIS OF VARIOUS CORDIC TECHNIQUES, June, [8] Yuan-Ho Chen et al, A High Performane Video Transform Engine by Using Spae- Time Sheduling Strategy, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO., APRIL [9] Xue Liu, Feng Yu, Ze-ke Wang, " A Pipelined Arhiteture for Normal I/O Order FFT", Journal of Zhejiang University-SCIENCE C (Comput & Eletron), vol.12, no.1, 2011, pp::6-82. [10] Weihua Zheng, Kenli Li, Keqin Li, "A Fast Algorithm Based on SRFFT for Length N=qx2m DFTs", IEEE Trans. Ciruits and Systems-II: Express Briefs, vol. 61, no.2, 201, pp: [11] Weihua Zheng, Kenli Li, and Keqin Li," A Fast Algorithm Based on SRFFT for Length N = q 2m DFTs, IEEE Trans. Ciruits Syst.II, Exp. Briefs, vol. 61, no. 2, pp , Feb. 201 Copyright to IJIRSET DOI: /IJIRSET