Design of High Speed Mac Unit

Transcription

1 Design of High Speed Ma Unit 1 Harish Babu N, 2 Rajeev Pankaj N 1 PG Student, 2 Assistant professor Shools of Eletronis Engineering, VIT University, Vellore , TamilNadu, India. 1 harishharsha72@gmail.om, 2 rajeevpankaj@vit.a.in Abstrat Radix-4 tehnique is most employed tehnique to redue the power onsumption and delay when ompared to all other tehniques in whih we use the booth reoding table for obtaining partial produts thus it an be used in a MAC unit. By using arry selet adder the partial produts are added. By using this RTL oding for 8 8 and using multipliation with modified booth tehnique and the MAC units for , the Simulation is performed in ModelSim. Pipelining is implemented with two yles to improve the speed of the MAC Unit. The synthesis arried in (Cadene) r and area, delay, power report are obtained. Index Terms Radix-4 multipliation, neg3 addition, 2 yle pipelining. I. INTRODUCTION Multiplier is the important blok in almost all the arithmeti logi units. These multipliers are mostly used in the fields of the Digital Signal Proessing (DSP), Fast Fourier Transform, onvolution, filtering and miroproessor appliations. Sine multiplier is the main omponent and hene a high speed and area effiient multiplier is needed to ahieve this one of the finest tehnique is by using Radix -4 enoding. Radix-4 MBE is mostly used beause it redues total number of partial produt rows to half while maintaining the generation of eah partial produt row fast. If n is the total number of bits in multiplier, radix-4 MBE tehnique redues these partial produt rows by +1.By using the proposed tehnique we are making that +1 partial produts to By adding neg3 at the top of the first partial produt row. onei +1 Twoi negi onei 1(a) xj Xj-1 twoi Ppij negi 1(b) Figure 1. Gate-level diagram for partial produt generation using MBE (a) MBE signals generation.(b) Partial produt generation The MBE signal generation unit is alled as enoding tehnique, partial produt generation tehnique is alled as a deoding sheme after obtaining the partial produts we should add them to add it we are using the arry selet adder module[2]. After summing of all the partial produts we an get the desired output by adding the vetors in whih we an use the Modified arry selet adder to inrease the speed of operation and to redue the power onsumption [1]. Modified booth algorithm onsumes less power when ompared to other type of multipliation algorithms beause of using Modified sqrt arry selet adder iruit by IJEDR International Journal of Engineering Development and Researh ( 1453

2 replaing the ripple arry adder iruit by BEC Unit whih inbuilt redue the power onsumption as an inremental unit.by applying pipelining the delay gets further redued. x7 x6 x5 x4 x3 x2 x1 x0 pp80 pp80 pp80 pp70 pp60 pp50 pp40 pp30 pp20 pp10 pp00 Figure 2. Sign extension prevention measure on the partial produt array of a 8 8 radix-4 MBE multiplier[2]. neg3 x7 x6 x5 x4 x3 x2 x1 x0 pp80 pp70 pp60 pp50 pp40 pp30 pp20 pp10 pp neg3 Figure 3. Idea for reduing the partial produt array[2]. The main idea to redue the power onsumption is by using redution of partial produt array. Thus speed and power an be improved by using these neg3 bit to add at the top of the first partial produt row[3]. x7 x6 x5 x4 x3 x2 x1 x0 qq90 qq90 qq80 qq70 qq60 pp50 pp40 pp30 pp20 pp10 pp00 Figure 4. Resultant rows after inorporating the idea neg(n/2)-1 qqn-2 ppn-2 qqn-1 ppn-1 qqn ppn qqn+1 qqn+2 II. Figure 5. The method for adding the last Neg bit in the first row[2] ADDING THE PARTIAL PRODUCTS USING CARRY SELECT ADDER Normal arry selet adder In this arry selet adder iruit we are using the two ripple arry adder bloks parallel in whih it is having more power onsumption beause of more hardware iruitry. Here in this arry selet adder iruit we are replaing the normal ripple adder blok with Binary to exess one onverter. In whih the binary to exess one module onsists of adding one to ripple result whih redues the no of gates so the power onsumption dereases, and speed inreases to high level. By using this in partial produts addition the results are better optimized with respet to power and delay when ompared with other type of adders. The redued gates an be shown in the form of equations as eo=~bo e1=bo^b1 e2=b2^ (bo&b1) e3=b3^ (bo&b1&b2) x=(b0&b1&b2&b3) IJEDR International Journal of Engineering Development and Researh ( 1454

3 The above expressions we get it from K-Map[1] Modified sqrt arry selet adder A [15:11] B [15:11] A [10:7] B [10:7] A [6:4] B [6:4] A [3:2] B [3:2] A [1:0] B [1:0] Cin 15:11 RCA 10:7 RCA 6:4 RCA 3:2 RCA 1:0 RCA 6 Bit BEC 5 Bit BEC 4 Bit BEC 3 Bit BEC Cout 12:6 10:5 8:4 6:3 III. BASIC MAC UNIT Sum [15:11] Sum [10:7] Sum [6:4] Sum [3:2] Sum [1:0] Figure 6. Modified sqrt arry selet adder[1] In this MAC Unit we are generating the produts and adding them using a aumulator register to store the values by using lok. Example of MAC Expression AB+CD+EF whih an be obtained from Fig 7 with pipelined arhiteture. Whenever pipelining is employed the ritial path gets redued and throughput of the arhiteture gets improved whih inbuilt inrease the speed. Pipelining is implemented in two lok yles, Whenever pipelining is implemented using an extra register the speed gets inreased but there is a hange in power onstraints also[4]. By inreasing the speed of the unit there is little bit inrease in power onstraints. X[15:0] Y[15:0] Reg X Reg Y PP Unit Cyle 1 Modified Carry Selet Adder 33 Pipelined Register [32:0] Reg-Aumulate [32:0] Aumulate Adder Cyle 2 Reg Output O [32:0] Figure 7. MAC Arhiteture The 2-yle MAC Unit is having a ritial path whih goes through the PP unit and the final adder a pipeline register is plaed before aumulator by opying into temporary register whih has no impat on funtionality. By using the pipelining, our MAC unit gives the orret output in eah lok yle, and no extra lok pulses to be added at the end of the loop. By inorporating several guarding bits, making longer devies feasible without making any overflow onsiderations. So the use of guarding bits in a tehnique where the aumulated is send bak to the PP s input, whih would most ertainly have a negative impat on hardware iruitry whih makes arhiteture omplex to solve the issues regarding guard bits. Thus pipelining provides inrease in fastness of the devie by 28% with a slight inrease of power onsumption, whenever we attempt for 3 yles then power onsumption inrease to maximum level in order to minimize it the two yle onfiguration is better employed in the MAC arhiteture. IJEDR International Journal of Engineering Development and Researh ( 1455

4 IV. RESULTS AND ANALYSIS The neg3 method addition gives better results when ompared to other multipliation tehniques whih give less delay onsumption when ompared with modified booth algorithm, but this delay is more than Vedi, array multipliation tehniques but better than baugh wooley multipliation [6]. So in order to improve the speed pipelining is implemented so that MAC Unit operates with high throughput but little bit inrease with power onsumption, beause the inrease in power onsumption doesn t affet the performane beause modified booth multipliation takes minimum power onsumption next to baugh wooley multipliation. So by implementing pipelining the inrease in power onsumption is very less when ompared to all other MAC Units [7]. Figure 8. MAC without pipelining Multipliation type Delay(ns) Power(nW) Modified Booth 8 X Negi method 8 X Modified Booth 16X Negi method 16X Modified Booth 32X Negi method 32X a. Comparison of Power, Delay in multipliation V. CONCLUSION Figure 9.MAC with pipelining MAC Unit Delay ns Area (No of ells) Total Power (nw) without pipelining 8X With pipelining 8X without pipelining 16X with pipelining 16 X without pipelining 32X with pipelining 32X b. Comparison of Power, Delay in and MAC Unit The Pipelined MAC Unit gives lesser delay when ompared to all other MAC Units and reasonable power onsumption beause the negi method of Modified Booth multiplier gives less power onsumption when ompared to other multipliation algorithms sine Modified arry selet adder is used for adding the partial produts. so by applying the pipelining the delay also gets redued and shows better performane. IJEDR International Journal of Engineering Development and Researh ( 1456

5 VI. ACKNOWLEDGMENT We thank the Shool of Eletronis Engineering, VIT University, Vellore for providing the tool Cadene environment and giving us valuable suggestions. REFERENCES [1] R.Priya, J.Senthil Kumar, Implementation and Comparison of Effetive Area Effiient Arhitetures for CSLA 2013 IEEE International Conferene on Emerging Trends in Computing, Communiation and Nanotehnology (ICECCN ), 2013 [2] Fabrizio Lamberti, Nikos Andrikos, Elisardo and Paolo Montushi, Reduing the Computation Time in (Short Bit-Width) Two s Complement Multipliers, IEEE Transations on Computers, Vol. 60, No. 2, February [3] F. Lamberti, N. Andrikos, E. Antelo, and P. Montushi, Speeding-Up Booth Enoded Multipliers by Reduing the Size of Partial Produt Array, internal report, pp. 1-14, [4] Tung Thanh Hoang, Magnus Sj alander, and Per Larsson-Edefors High-Speed, Energy-Effiient 2-Cyle Multiply Aumulate Arhiteture, pp 978-1, IEEE2009. [5] J.-Y. Kang and J.-L. Gaudiot, A Fast and Well-Strutured Multiplier, Pro. Euromiro Symp. Digital System Design, pp , Sept [6] Magnus Själander and Per Larsson-Edefors, High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Redution Tree, 2008 IEEE [7] Debaprasad Das and Hafizur Rahaman, A Novel Signed Array Multiplier 2010 International Conferene on Advanes in Computer Engineering, 2010 IEEE. [8] Dr. K.S. Gurumurthy, M.S Prahalad, Fast and Power Effiient Array of Array Multiplier using Vedi Multipliation [9] Morris Mano, Computer System Arhiteture, 3rd edition, Prientie-Hall, New Jersey, USA, 1993, pp IJEDR International Journal of Engineering Development and Researh ( 1457