Cache Impact on Program Performance. T. Yang. UCSB CS240A. 2017

Transcription

1 Cache Impact on Program Performance T. Yang. UCSB CS240A. 2017

2 Multi-level cache in computer systems Topics Performance analysis for multi-level cache Cache performance optimization through program transformation Processor Datapath Control L1 cache L2 Cache L3 cache Caching Main meory Disk

3 3

4 Cache misses and data access time D 0 : total memory data accesses. D 1 : missed access at L1. m 1 local miss ratio of L1: m 1 = D 1 /D 0 D 2 : missed access at L2. m 2 local miss ratio of L2: m 2 = D 2 /D 1 D 3 : missed access at L3 m 3 local miss ratio of L2: m 3 = D 3 /D 2 Memory and cache access time: δ i : access time at cache level i δ mem : access time in memory. Average access time = total time/d 0 = δ 1 + m 1 *penalty CPU

5 Average memory access time (AMAT) AMAT= Data found in L1 Data found in L2, L3 or memory δ 1 + m 1 *penalty ~2 cycles

6 Total data access time Average time = Data found in L2 Data found in L3 or memory δ 1 + m 1 [δ 2 + m 2 Penalty] ~2 cycles

7 Total data access time Found in L3 or memory Average time = δ 1 + m 1 [δ 2 + m 2 Penalty] ~2 cycles

8 Total data access time No L3. Found in memory Average time = δ 1 + m 1 [δ 2 + m 2 δ mem ] ~2 cycles ~10 cycles ~ cycles

9 Total data access time Found in L3 Found in memory Average memory access time (AMAT)= δ 1 + m 1 [δ 2 + m 2 [δ 3 + m 3 δ mem ]]

10 Local vs. Global Miss Rates Local miss rate the fraction of references to one level of a cache that miss. For example, m 2 = D 2 /D 1 Notice total_l2_accesses is L1 Misses Global miss rate the fraction of references that miss in all levels of a multilevel cache Global L2 miss rate = D 2 /D 0 L2$ local miss rate >> than the global miss rate Notice Global L2 miss rate = D 2 /D 0 = D 1 /D 0 * D 2 /D 1 = m 1 m 2 10

11 Global miss rate L1 Cache: 32KB I$, 32KB D$ L2 Cache: 256 KB L3 Cache: 4 MB 10/4/17 Fall Lecture 11

12 Average memory access time with no L3 cache δ 1 + m 1 [δ 2 + m 2 δ mem ] AMAT = = δ 1 + m 1 δ 2 + m 1 m 2 δ mem = δ 1 + m 1 δ 2 + GMiss 2 δ mem

13 Average memory access time with L3 cache δ 1 + m 1 [δ 2 + m 2 [δ 3 + m 3 δ mem ]] AMAT = = δ 1 + m 1 δ 2 + m 1 m 2 δ 3 +m 1 m 2 m 3 δ mem = δ 1 + m 1 δ 2 + GMiss 2 δ 3 + GMiss 3 δ mem

14 Example What is average memory access time?

15 Example What is the average memory access time with L1, L2, and L3?

16 Example

17 Cache-aware Programming Reuse values in cache as much as possible exploit temporal locality in program Example 1: Y[2] is revisited continously For i=1 to n y[2]=y[2]+3 Example 2 with access sequence: Y[2] is revisited after a few instructions later

18 Cache-aware Programming Take advantage of better bandwidth by getting a chunk of memory to cache and use whole chunk Exploit spatial locality in program For i=1 to n y[i]=y[i]+3 Visiting Y[1] benefits next access of Y[2] 4000 Y[0] Y[1] Y[2]] Y[3] Y[4] Y[31] 32-Byte Cache Block Tag Memory 18

19 2D array layout in memory (just like 1D array) for(x = 0; x < 3; x++){ for(y = 0; y < 3; y++) { a[y][x]=0; // implemented as array[3*y+x]=0 } } àaccess order a[0][0], a[1][0], a[2][0], a[3][0]

20 Exploit spatial data locality via program rewriting: Example 1 Each cache block has 64 bytes. Cache has 128 bytes Program structure (data access pattern) char D[64][64]; Each row is stored in one cache line block Program 1 for (j = 0; j <64; j++) for (i = 0; i < 64; i++) D[i][j] = 0; 64*64 data byte access à What is cache miss rate? Program 2 for (i = 0; i < 64; i++) for (j = 0; j < 64; j++) D[i][j] = 0; What is cache miss rate?

21 Data Access Pattern and cache miss for (i = 0; i <64; j++) for (j = 0; j < 64; i++) D[i][j] = 0; 1 cache miss in one inner loop iteration Miss hit hit hit hit D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] j Cache block D[63,0] D[63,1]. D[63,63] 64 cache miss out of 64*64 access. There is spatial locality. Fetched cache block is used 64 times before swapping out (consecutive data access within the inner loop i

22 Memory layout and data access by block Memory layout of Char D[64][64] same as Char D[64*64] Data access order Memory layout of a program Program in 2D loop Miss hit hit hit hit D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] j D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] Cache block Cache block D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] i D[63,0] D[63,1]. D[63,63] 64 cache miss out of 64*64 access. D[63,0] D[63,1]. D[63,63] Cache block D[63,0] D[63,1]. D[63,63]

23 Data Locality and Cache Miss for (j = 0; j <64; j++) for (i = 0; i < 64; i++) D[i][j] = 0; 64 cache miss in one inner loop iteration D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] j D[63] D[63,0]. D[63,63] 100% cache miss There is no spatial locality. Fetched block is only used once before swapping out. i

24 Memory layout and data access by block Data access order of a program D[0,0] D[1,0]. D[63,0] D[0,1] D[1,1]. D[63,1] Cache block Cache block Memory layout D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] i Program in 2D loop j D[0,0] D[0,1]. D[0,63] D[1,0] D[1,1]. D[1,63] D[63] D[63,0]. D[63,63] D[0,63] D[1,63]. D[63,63] Cache block D[63,0] D[63,1]. D[63,63] 100% cache miss

25 Summary of Example 1: Loop interchange alters execution order and data access patterns Exploit more spatial locality in this case

26 Program rewriting example 2: cache blocking for better temporal locality Cache size = 8 blocks =128 bytes Cache block size =16 bytes, hosting 4 integers Program structure int A[64]; // sizeof(int)=4 bytes for (k = 0; k<repcount; k++) for (i = 0; i < 64; I +=stepsize) A[i] =A[i]+1 Analyze cache hit ratio when varying cache block size, or step size (stride distance)

27 Example 2: Focus on inner loop for (i = 0; i < 64; i +=stepsize) A[i] =A[i]+1 memory Cache block Data access order/index s Stepsize S=1 S=2 S=4 S=8 Step size or also called stride distance

28 Step size =2 for (i = 0; i < 64; I +=stepsize) A[i] =A[i]+1 //read, write A[i] Memory Cache block Data access order/index S=2 M/H H/H M/H H/H M/H H/H

29 Repeat many times for (k = 0; k<repcount; k++) for (i = 0; i < 64; I +=stepsize) A[i] =A[i]+1 //read, write A[i] Memory Cache block Data access order/index S=2 integers M/H H/H M/H H/H M/H H/H Array has 16 blocks. Inner loop accesses 32 elements, and fetches all 16 blocks. Each block is used as R/W/R/W. Cache size = 8 blocks and cannot hold all 16 blocks fetched.

30 Cache blocking to exploit temporal locality For (k=0; k=100; k++) for (i = 0;i <64;i+=S) A[i] =f(a[i]) K=0 to K=0 to Pink code block can be executed fitting into cache K=0 to K=1 K=2 K=3 Rewrite program with cache blocking

31 Rewrite a program loop for better cache usage Loop blocking (cache blocking) Rewrite as with blocksize=2 More general: Given for (i = 0; i < 64; i+=s) A[i] =f(a[i]) Rewrite as: for (bi = 0; bi<64; bi=bi+blocksize) for (i = bi; i<bi+ blocksize;i+=s) A[i] =f(a[i])

32 Example 2: Cache blocking for better performance For (k=0; k=100; k++) for (i = 0; i < 64; i=i+s) A[i] =f(a[i]) Rewrite as: For (k=0; k=100; k++) for (bi = 0; bi<64; bi=bi+blocksize) for (i = bi; i<bi+blocksize; i+=s) A[i] =f(a[i]) Look interchange for (bi = 0; bi<64; bi=bi+blocksize) For (k=0; k=100; k++) for (i = bi; i<bi+ blocksize; i+=s) A[i] =f(a[i]) Pink code block can be executed fitting into cache

33 Example 3: Matrix multiplication C=A*B Cij=Row Ai * Col Bj For i= 0 to n-1 For j= 0 to n-1 For k=0 to n-1 C[i][j] +=A[i][k]* B[k][j]

34 Example 3: matrix multiplication code 2D array implemented using 1D layout for (i = 0; i < n; i++) for (j = 0; j < n; j++) for (k = 0; k < n; k++) C[i+j*n] += A[i+k*n]* B[k+j*n] 3 loop controls can interchange (C elements are modified independently with no dependence) Which code has better cache performance (faster)? for (j = 0; j < n; j++) for (k = 0; k < n; k++) for (i = 0; i < n; i++) C[i+j*n] += A[i+k*n]* B[k+j*n]

35 Example 3: matrix multiplication code 2D array implemented using 1D layout for (i = 0; i < n; i++) for (j = 0; j < n; j++) for (k = 0; k < n; k++) C[i+j*n] += A[i+k*n]* B[k+j*n] 3 loop controls can interchange (C elements are modified independently with no dependence) Which code has better cache performance (faster)? -- Study impact of stride on inner most loop which does most computation for (j = 0; j < n; j++) for (k = 0; k < n; k++) for (i = 0; i < n; i++) C[i+j*n] += A[i+k*n]* B[k+j*n]

36 Example 4: Cache blocking for matrix transpose for (x = 0; x < n; x++) { for (y = 0; y < n; y++) { dst[y + x * n] = src[x + y * n]; } src } y dst x Rewrite code with cache blocking

37 Example 4: Cache blocking for matrix transpose for (x = 0; x < n; x++) { for (y = 0; y < n; y++) { dst[y + x * n] = src[x + y * n]; } } Rewrite code with cache blocking for (i = 0; i < n; i += blocksize) for (x = i; x < i+blocksize; ++x) for (j = 0; j < n; j += blocksize) for (y = j; y < j+blocksize; ++y) dst[y + x * n] = src[x + y * n];