Cache Memories. EL2010 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 2010

Transcription

1 Cache Memories EL21 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 21

2 Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance

3 Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L1, then in L2, then in main memory. Typical bus structure: CPU chip register file cache bus L1 cache ALU system bus memory bus L2 cache bus interface I/O bridge main memory

4 Inserting an L1 Cache Between the CPU and Main Memory The transfer unit between the CPU register file and the cache is a 4-byte block. The transfer unit between the cache and main memory is a 4-word block (16 bytes). line line 1 block 1 block 21 block 3 a b c d... p q r s... w x y z... The tiny, very fast CPU register file has room for four 4-byte words. The small fast L1 cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks.

5 General Org of a Cache Memory Cache is an array of sets. 1 valid bit per line t bits per line B = 2 b bytes per cache block Each set contains one or more lines. set : valid valid 1 1 B 1 B 1 E lines per set Each line holds a block of data. valid 1 B 1 S = 2 s sets set 1: valid 1 B 1 valid 1 B 1 set S-1: valid 1 B 1 Cache size: C = B x E x S data bytes

6 Addressing Caches Address A: t bits s bits b bits set : v v 1 1 B 1 B 1 m-1 <> <set index> <block offset> set 1: set S-1: v v v v B 1 B 1 B 1 B 1 The word at address A is in the cache if the bits in one of the <valid> lines in set <set index> match <>. The word contents begin at offset <block offset> bytes from the beginning of the block.

7 Direct-Mapped Cache Simplest kind of cache Characterized by exactly one line per set. set : valid cache block E=1 lines per set set 1: valid cache block set S-1: valid cache block

8 Accessing Direct-Mapped Caches Set selection Use the set index bits to determine the set of interest. set : valid cache block selected set set 1: valid cache block m-1 t bits s bits 1 b bits set index block offset set S-1: valid cache block

9 Accessing Direct-Mapped Caches Line matching and word selection Line matching: Find a valid line in the selected set with a matching Word selection: Then extract the word =1? (1) The valid bit must be set selected set (i): w w 1 w 2 w 3 (2) The bits in the cache line must match the bits in the address m-1 =? t bits 11 s bits b bits i 1 set index block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte.

10 Direct-Mapped Cache Simulation t=1 s=2 b=1 x xx x M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads): [ 2 ], 1 [1 2 ], 13 [111 2 ], 8 [1 2 ], [ 2 ] [ 2 ] (miss) v data 1 m[1] M[-1] m[] 13 [111 2 ] (miss) v data 1 m[1] M[-1] m[] (1) (3) 1 1 m[13] M[12-13] m[12] 8 [1 2 ] (miss) v data 1 1 m[9] M[8-9] m[8] [ 2 ] (miss) v data 1 m[1] M[-1] m[] (4) 1 1 M[12-13] (5) 1 1 m[13] M[12-13] m[12]

11 Why Use Middle Bits as Index? High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing line Cache Consecutive memory lines map to different cache lines Can hold C-byte region of address space in cache at one time High-Order Bit Indexing Middle-Order Bit Indexing

12 Cache Example Problem 32 bit address 4K cache sets 1 word per line (32 bit data) Byte addressable Memory address structure? Cache line structure? Cache size?

13 Cache Example Memory address 4K sets requires 12 bits (496 = 2 s ) s = 12 1 word 32 bit = 4 bytes (4 = 2 b ) b = 2 Tag = = 18 Cache line structure 1 valid bit 18 bit 1 word : 32 bit Total 51 bit Cache size V (1) Tag (18) Tag (18) C = S x Line = 496 x 51 bit = bit Set (12) Block (2) Word (32) (8) (8) (8) (8)

14 Cache access problem Cache: 8 bit address and 1 word block Direct Mapped : 16 sets each line contains one word Show the final content of the cache given 2,3,11,16,21,13,64,48,19,11,3,22,4,27,6,11 memory access

15 2 1 miss 3 11 hit miss 16 1 miss miss miss 64 1 miss miss hit hit 3 11 miss hit 4 1 miss miss hit hit Set V Tag B B1 B2 B3 1 M[] M[1] M[2] M[3] 1 1 M[4] M[5] M[6] M[7] 2 1 M[8] M[9] M[1] M[11] 3 1 M[12] M[13] M[14] M[15] 4 1 M[16] M[17] M[18] M[19] 5 1 M[2] M[21] M[22] M[23] 6 1 M[24] M[25] M[26] M[27] M[48] M[49] M[5] M[51]

16 Cache access problem Cache: 8 bit address and 1 word block Direct Mapped : 16 sets each line contains one word s = 4, b = 2, and = 2 Access 2 [ 1]: Set : miss 3 [ 11]: Set : hit 11 [ 1 11]: Set 2 : miss 16 [ 1 ]: set 4 : miss 21 [ 11 1]: Set 5 : miss 13 [ 11 1]: Set 3 : miss 64 [1 ]: Set : miss 48 [ 11 ]: Set 12 : miss 19 [ 1 11]: Set 4 : hit 11 [ 1 11]: Set 2 : hit 3 [ 11]: Set : miss 22 [ 11 1]: Set 5 : hit 4 [ 1 ]: Set 1 : miss 27 [ 11 11]: Set 6 : miss 6 [ 1 1]: Set 1 : hit 11 [ 1 11]: Set 2 : hit Set Valid Tag Block 1 M[-3] M[8-11] A B C D E F

17 Set Associative Caches Characterized by more than one line per set set : valid cache block valid cache block E=2 lines per set set 1: set S-1: valid cache block valid cache block valid cache block valid cache block

18 Accessing Set Associative Caches Set selection identical to direct-mapped cache set : valid valid cache block cache block Selected set set 1: valid valid cache block cache block m-1 t bits s bits 1 b bits set index block offset set S-1: valid valid cache block cache block

19 Accessing Set Associative Caches Line matching and word selection must compare the in each valid line in the selected set. =1? (1) The valid bit must be set selected set (i): w w 1 w 2 w 3 (2) The bits in one of the cache lines must match the bits in the address m-1 =? t bits 11 s bits b bits i 1 set index block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte.

20 Cache Example Problem 32 bit address 2K cache sets (2 way set associative) 1 word per line (32 bit data) Byte addressable Memory address structure? Cache line structure? Cache size?

21 Cache access problem Cache: 8 bit address and 1 word block Two-way Set Associative : 8 sets each line contains one word Show the final content of the cache given 2,3,11,16,21,13,64,48,19,11,3,22,4,27,6,11 memory access

22 2 1 miss 3 11 hit miss 16 1 miss miss miss 64 1 miss miss hit hit 3 11 hit hit 4 1 miss miss hit hit Set V Tag B B1 B2 B3 1 M[] M[1] M[2] M[3] 1 1 M[64] M[65] M[66] M[67] 1 M[4] M[5] M[6] M[7] 2 1 M[8] M[9] M[1] M[11] 3 1 M[12] M[13] M[14] M[15] 4 1 M[16] M[17] M[18] M[19] 1 1 M[48] M[49] M[5] M[51] 5 1 M[2] M[21] M[22] M[23] 6 M[24] M[25] M[26] M[27] 7

23 Fully Set Associative Caches Characterized by only one set valid cache block set : valid cache block valid cache block valid cache block valid cache block valid cache block E= n lines per set

24 Accessing Fully Set Associative Caches No Set selection set : valid valid cache block cache block valid cache block t bits b bits valid cache block m-1 block offset valid cache block valid cache block

25 Accessing Fully Set Associative Caches Line matching and word selection must compare the in each valid. =1? (1) The valid bit must be set set : w w 1 w 2 w 3 (2) The bits in one of the cache lines must match the bits in the address m-1 =? t bits 11 b bits 1 block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte.

26 Cache Example Problem 32 bit address 1K cache lines (Fully associative) 1 word per line (32 bit data) Byte addressable Memory address structure? Cache line structure? Cache size?

27 Cache access problem Cache: 8 bit address and 1 word block Fully Associative : 8 lines contains one word Show the final content of the cache given 2,3,11,16,21,13,64,48,19,11,3,22,4,27,6,11 memory access

28 2 1 miss 3 11 hit miss 16 1 miss miss miss 64 1 miss miss hit hit 3 11 hit hit 4 1 miss miss hit hit Set V Tag B B1 B2 B M[24] M[25] M[26] M[27] 1 1 M[8] M[9] M[1] M[11] 1 1 M[16] M[17] M[18] M[19] 1 11 M[2] M[21] M[22] M[23] 1 11 M[12] M[13] M[14] M[15] 1 1 M[64] M[65] M[66] M[67] 1 11 M[48] M[49] M[5] M[51] 1 1 M[4] M[5] M[6] M[7]

29 Multi-Level Caches Options: separate data and instruction caches, or a unified cache Processor Regs L1 d-cache L1 i-cache Unified L2 Cache Memory disk size: speed: $/Mbyte: line size: 2 B 3 ns 8-64 KB 3 ns 8 B 32 B larger, slower, cheaper 1-4MB SRAM 6 ns $1/MB 32 B 128 MB DRAM 6 ns $1.5/MB 8 KB 3 GB 8 ms $.5/MB

30 Intel Pentium Cache Hierarchy Regs. L1 Data 1 cycle latency 16 KB 4-way assoc Write-through 32B lines L1 Instruction 16 KB, 4-way 32B lines L2 Unified 128KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Processor Chip

31 Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses/references) Typical numbers: 3-1% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: 1 clock cycle for L1 3-8 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 25-1 cycles for main memory

32 Writing Cache Friendly Code Repeated references to variables are good (temporal locality) Stride-1 reference patterns are good (spatial locality) Examples: cold cache, 4-byte words, 4-word cache blocks int sumarrayrows(int a[m][n]) { int i, j, sum = ; int sumarraycols(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Miss rate = 1/4 = 25% Miss rate = 1%

33 The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance.

34 Memory Mountain Test Function /* The test function */ void test(int elems, int stride) { int i, result = ; volatile int sink; for (i = ; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, ); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */

35 Memory Mountain Main Routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES (1 << 1) /* Working set size ranges from 1 KB */ #define MAXBYTES (1 << 23) /*... up to 8 MB */ #define MAXSTRIDE 16 /* Strides range from 1 to 16 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traversing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to 1 */ Mhz = mhz(); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= 1) { for (stride = 1; stride <= MAXSTRIDE; stride++) printf("%.1f\t", run(size, stride, Mhz)); printf("\n"); exit();

36 The Memory Mountain read throughput (MB/s) Slopes of Spatial Locality xe L2 L1 Pentium III Xeon 55 MHz 16 KB on-chip L1 d-cache 16 KB on-chip L1 i-cache 512 KB off-chip unified L2 cache Ridges of Temporal Locality s1 s3 s5 mem 8k 2k stride (words) s7 s9 s11 s13 s15 8m 2m 512k 128k 32k working set size (bytes)

37 Ridges of Temporal Locality Slice through the memory mountain with stride=1 illuminates read throughputs of different caches and memory 12 main memory region L2 cache region L1 cache region m 4m 2m 124k 512k 256k 128k 64k 32k 16k 8k 4k 2k 1k read througput (MB/s) working set size (bytes)

38 A Slope of Spatial Locality Slice through memory mountain with size=256kb shows cache block size.

39 Matrix Multiplication Example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) Block size Exploit spatial locality Description: Multiply N x N matrices O(N3) total operations Accesses N reads per source element N values summed per destination but may be able to hold in register /* ijk */ for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Variable sum held in register

40 Miss Rate Analysis for Matrix Multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is very large Approximate 1/N as. Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop k j j i k i A B C

41 Layout of C Arrays in Memory (review) C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = ; i < N; i++) sum += a[][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = ; i < n; i++) sum += a[i][]; accesses distant elements no spatial locality! compulsory miss rate = 1 (i.e. 1%)

42 Matrix Multiplication (ijk) /* ijk */ for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Inner loop: (i,*) (*,j) (i,j) A B C Row-wise Columnwise Fixed Misses per Inner Loop Iteration: A B C

43 Matrix Multiplication (jik) /* jik */ for (j=; j<n; j++) { for (i=; i<n; i++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum Misses per Inner Loop Iteration: A B C Inner loop: (i,*) (*,j) (i,j) A B C Row-wise Columnwise Fixed

44 Matrix Multiplication (kij) /* kij */ for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C

45 Matrix Multiplication (ikj) /* ikj */ for (i=; i<n; i++) { for (k=; k<n; k++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C

46 Matrix Multiplication (jki) /* jki */ for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (*,j) (k,j) A B C Misses per Inner Loop Iteration: A B C Column - wise Fixed Columnwise

47 Matrix Multiplication (kji) /* kji */ for (k=; k<n; k++) { for (j=; j<n; j++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Misses per Inner Loop Iteration: A B C Inner loop: (*,k) (k,j) (*,j) A B C Columnwise Fixed Columnwise

48 Summary of Matrix Multiplication ijk (& jik): 2 loads, stores misses/iter = 1.25 kij (& ikj): 2 loads, 1 store misses/iter =.5 jki (& kji): 2 loads, 1 store misses/iter = 2. for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r;

49 Pentium Matrix Multiply Performance Miss rates are helpful but not perfect predictors. Code scheduling matters, too. 6 5 Cycles/iteration kji jki kij ikj jik ijk Array size (n)

50 Improving Temporal Locality by Blocking Example: Blocked matrix multiplication block (in this context) does not mean cache block. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A 11 A 12 A 21 A 22 X B 11 B 12 B 21 B 22 = C 11 C 12 C 21 C 22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C 11 = A 11 B 11 + A 12 B 21 C 12 = A 11 B 12 + A 12 B 22 C 21 = A 21 B 11 + A 22 B 21 C 22 = A 21 B 12 + A 22 B 22

51 Blocked Matrix Multiply (bijk) for (jj=; jj<n; jj+=bsize) { for (i=; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] =.; for (kk=; kk<n; kk+=bsize) { for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum;

52 Blocked Matrix Multiply Analysis Innermost loop pair multiplies a 1 X bsize sliver of A by a bsize X bsize block of B and accumulates into 1 X bsize sliver of C Loop over i steps through n row slivers of A & C, using same B Innermost Loop Pair for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; kk jj jj i kk i A B C row sliver accessed bsize times block reused n times in succession Update successive elements of sliver

53 Pentium Blocked Matrix Multiply Performance Blocking (bijk and bikj) improves performance by a factor of two over unblocked versions (ijk and jik) relatively insensitive to array size. 6 5 Cycles/iteration Array size (n) kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25)

54 Concluding Observations Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor cache friendly code Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advane with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality)