Design and Implementation of MP3 Player Based on FPGA Dezheng Sun
|
|
- Nathaniel Anderson
- 6 years ago
- Views:
Transcription
1 Applied Mechanics and Materials Online: ISSN: , Vol. 443, pp doi: / Trans Tech Publications, Switzerland Design and Implementation of MP3 Player Based on FPGA Dezheng Sun College of Information Science and Engineering, Northeastern University, Shenyang , China Keywords: Mp3 Player,, FPGA Abstract. The paper adopts a method of a low speed processer and FPGA based hardware accelerator SOC units to develop the MP3 player, added with some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantage on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future because it s designed based on FPGA. In conclusion, it has a wide application prospect. Introduction The MP3 player is not only small size, light weight, large storage capacity and small power consumption. With increasing memory capacity and price continue to lower, MP3 players, car and portable audio field, more and more people are welcome, especially in the field of portable audio, MP3 players have occupied the absolute mainstream position, so the MP3 player is great application significance [1]. MP3 player performance mainly depends on the performance system with MP3 decoder, MP3 decoder system [2]; there are two main MP3 software decoding algorithms to optimize the design and MP3 hardware decoding study, Low-speed core processors and other hardware acceleration module SOC (System on a Chip, SoC) design and the external device to achieve [3]. MP3 Decoding Process Analysis MP3 decoding process shown in Fig. 1, the decoding process includes the extract stream synchronization (in units of frames) Huffman decoding, the scale factor decoding, inverse quantization, re-arrangement of the stereo processing, aliasing reconstruction IMDCT transform, sub-with integrated filter synthesis, the final output of the original PCM data. In the decoding process, the more time-consuming IMDCT and sub band filtering the two elements. Compiled, they occupy a considerable number of hardware resources; power consumption is particularly high for both the design computationally intensive algorithm IMDCT, sub-band synthesis filter to do hardware acceleration to improve overall system performance. IMDCT algorithm has long block and short block, long block input calculation is 18:00 short block input is 6:00, the length of the block input values are not 2 ^ n, so you can use the fast algorithm of Szu Wei, Lee, this the algorithm for the larger operations of input points, the faster the more obvious. Traditional IMDCT algorithm needed in the calculation of the long block is 36 * 18 multiplications and 36 * 17 addition, Szu Wei, Lee algorithm, the calculation of the long block only 43 multiplications and 115 additions, the operation speed of the program significantly improved. Calculated directly in the design sub-band filter, you need to perform 32 * 64 multiplication and 31 * 64 addition, the two-channel sampling rate of 44.1KHz, the multiplication capacity of (44100/32) * (64 * ) * 2 = million times / sec, while the system clock is generally used is 50MHz single cycle occupied 58.2% of the entire decoding time, seriously affecting the rate of decoding of the entire system. Therefore, according to the symmetry of the cosine function, combined with of Beyond of Gi Lee, the fast DCT algorithm to improve, improved sub-band integrated filter only needs 384 multiplications and 376 additions greatly enhance the speed of operation. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-09/05/16,22:17:51)
2 Applied Mechanics and Materials Vol The Hardware Design of the System Nios II-based embedded system mainly consists of three parts: IP library (the Nios II soft core processor, the Avalon bus peripheral interface), GNUPro software compiler, SOPC Builder development tool. Altera Corporation, CycloneII FPGA chip used in hardware design, model EP2C70F896C6 main peripheral equipment, including off-chip SDRAM memory, SD card, audio chips, WM8731, the LCD, the FPGA chip to complete the various hardware modules and data flow control chip memory to store program data and code execution, SD cards to store MP3 files, audio chip, the PCM data stream output, LCD display system status, IP core reuse is the key to the SOPC design. The hardware system architecture shown in Fig 2 Internal FPGA logic design is based on Quartus II development environment to the Verilog language programming, audio control, SD card reader, LCD drivers and other function modules. SOPC Builder configuration and Nios II soft core processor and the necessary peripherals, and then re-compile, download the configuration of the FPGA chip to form a connection of the hardware logic circuit, and finally verify that the system in order to achieve the output of MP3 audio files. In addition to the audio module, SD card control module, LCD display to the other modules in the drive module through SOPC Builder to add the IP core build. As for the child in the MP3 decoding algorithm with integrated filter, IMDCT transform two parts dealing with them the special time-consuming, against such time-consuming problem, you can use the software and hardware co-processing more time-consuming part of the hardware acceleration (software, often several times faster than the speed of processing of the original software.) to improve the entire system run time. This design method can be determined, in the consolidated mutual constraint relationship between the system software and hardware in order to ensure certainty, efficiency of the system. MP3 stream Frame synchronization and Error header information decoder Huffman Scale factor Inverse Quantization Re-arranged Left Audio PCM Stream Comes with Comprehensive filtering Right Audio PCM Stream Comes with Comprehensive filtering IMDCT IMDCT Aliasing Reconstruction Aliasing Reconstruction Stereo Processing Fig. 1 MP3 MP3 Audo Decode System Key Module MP3 Audio MP3 Audio Play Module Core Processing Module SD Card Module Display Module Fig. 2 MP3 Player Overall Function Structure Diagram
3 748 Computer-Aided Design, Manufacturing, Modeling and Simulation III System Software Design Configure Niosn Soft-Core System Modules Altera Corporation provide the SOPCBullder of development tools, you can very easily customize the system retaining nuclear. MP3 player system needs to configure the hardware logic of NIOSH, configured processor shown in Figure 4.2, on in eyelone11ep2c70f896c6 chips to achieve a soft core epu Nios11, OnChipRAM, and digital interface Nios11 soft-core CPU and Ip the module of ltrj by Avalon on-chip bus is connected. The purpose is to configure the soft-core processor of Niosn to use Ni0SH processor system to coordinate the work of the whole system. Shown in Fig. 3 Fig. 3 Configured Nios 2 soft-core system block diagram Huflhlan Decoding Module Since the Huffillan coding is carried out to quantify the value of the frequency domain, usually a large value is mainly concentrated in the low frequency part, and zero values are concentrated in the high frequency part, so each band the flexibility to choose a higher coding efficiency Huffillan table. Huffizzan decoding module function is to decode the compressed data input derived scaling factor (scalefactor); Then, in the process of decoding Huffinan, the use of side information obtained from the synchronization information processing module, draw Hu while an decoding required information, and then look for the advance in the ROM, built the corresponding Huffinan table, the final output of the original 576 frequency lines in the frequency domain to quantify value. These outputs are used for the next processing module - inverse quantization module. The overall decoding process is the Start of '1 'to done is set to '1' end, which quantify the value of the frequency domain to store the primary storage area to Huffinan module to facilitate debugging and inverse quantization module call. Fig. 4 is Huffnian decoding module data flow diagram. Fig. 4 Data flow diagram of Huffman decoding module The code is: Huffmancodebits () { For (l=o; l < big_ values*2; l+=2) Hcod [ x ] [ y ]
4 Applied Mechanics and Materials Vol If ( x ==15&&linbits>O) linbitsx If (x! = 0) signx If ( y ==15&&limits>O) linbitsy If (y! = 0) sign Is l =x If [l + l] =y For (: l<big_ values*2+countl*4; 1+=4) { Hcod [ v ] [ w ] [ y ] If (v! =0) sign If (w! =0) signw If (x! =0) signx If (y! =0) signy Is [1] =v Is [l+ l] =w Is [l+2] =x Is [l+3] =y For (; 1<576; l++) Is [1] =O Conclusions This is the MP3 decoder design based on SOPC technology, its advantages is that the system functions to improve flexibility, that does not change the circumstances of the hardware platform, casual, additions or deletions to the system and optimize to reduce the cost of the system, which is the other programs difficult to compare. Hardware decoding system using Verilog HDL language to describe, after the RTL-level simulation and verification, the Cyclone II device within EP2C8Q208 resources occupancy rate of 8% total register for the 3335 system frequencies up to 72MHz, the actual test, the design to achieve the desired effect. But there are still some places for improvement and could be improved, and this is also after the MP3 player design need to improve and focus of the study: (1) This design features simple, compiled FPGA chip resources occupied by relatively small, further increase in other functions, such as image display. (2) How to improve a more efficient algorithm to improve system uptime, reduce power consumption in order to achieve portable high performance, low power requirements, this is the future of MP3 design focus of the study. References [1] Eilert, J.Ehliaf, A., Dake Liu, Using low Precision floating Point numbers to reduce memory eost for MP3 decoding, Multimedia Signal Professing, IEEE 6th Workshop on 22 (44), (2004) [2] TaghiPour, H., Frounehi, J., Zarifi, M.H, Design and implementation of MP3 decoder using Partial dynamic reconfiguration on Virtex-4 FPGAs, Computer and Communication Engineering 34(15), (2008) [3] Nam, S.J., Kim, B.H., Im, C.D., Kim, J.B., Lee, S.J., Jeong, S.S., Kim, J.K., Park, S.J, a low Power MPEG1/11 layer 3 audiodeeoder, Circuits and Systems 2(55), (2001)
5 Computer-Aided Design, Manufacturing, Modeling and Simulation III / Design and Implementation of MP3 Player Based on FPGA /
The Implement of MPEG-4 Video Encoding Based on NiosII Embedded Platform
The Implement of MPEG-4 Video Encoding Based on NiosII Embedded Platform Fugang Duan School of Optical-Electrical and Computer Engineering, USST Shanghai, China E-mail: dfgvvvdfgvvv@126.com Zhan Shi School
More informationEMBEDDED SOPC DESIGN WITH NIOS II PROCESSOR AND VHDL EXAMPLES
EMBEDDED SOPC DESIGN WITH NIOS II PROCESSOR AND VHDL EXAMPLES Pong P. Chu Cleveland State University A JOHN WILEY & SONS, INC., PUBLICATION PREFACE An SoC (system on a chip) integrates a processor, memory
More informationBuilding Data Path for the Custom Instruction. Yong ZHU *
2017 2nd International Conference on Computer, Mechatronics and Electronic Engineering (CMEE 2017) ISBN: 978-1-60595-532-2 Building Data Path for the Custom Instruction Yong ZHU * School of Computer Engineering,
More informationDesign and Implementation of LED Display Screen Controller based on STM32 and FPGA Chi Zhang 1,a, Xiaoguang Wu 1,b and Chengjun Zhang 1,c
Applied Mechanics and Materials Online: 2012-12-27 ISSN: 1662-7482, Vols. 268-270, pp 1578-1582 doi:10.4028/www.scientific.net/amm.268-270.1578 2013 Trans Tech Publications, Switzerland Design and Implementation
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated
More informationRealization of Automatic Keystone Correction for Smart mini Projector Projection Screen
Applied Mechanics and Materials Online: 2014-02-06 ISSN: 1662-7482, Vols. 519-520, pp 504-509 doi:10.4028/www.scientific.net/amm.519-520.504 2014 Trans Tech Publications, Switzerland Realization of Automatic
More informationThe Analysis and Research of IPTV Set-top Box System. Fangyan Bai 1, Qi Sun 2
Applied Mechanics and Materials Online: 2012-12-13 ISSN: 1662-7482, Vols. 256-259, pp 2898-2901 doi:10.4028/www.scientific.net/amm.256-259.2898 2013 Trans Tech Publications, Switzerland The Analysis and
More informationA design of real-time image processing platform based on TMS320C6678
Advanced Materials Research Online: 2014-06-25 ISSN: 1662-8985, Vols. 971-973, pp 1454-1458 doi:10.4028/www.scientific.net/amr.971-973.1454 2014 Trans Tech Publications, Switzerland A design of real-time
More informationResearch on the Application of Digital Images Based on the Computer Graphics. Jing Li 1, Bin Hu 2
Applied Mechanics and Materials Online: 2014-05-23 ISSN: 1662-7482, Vols. 556-562, pp 4998-5002 doi:10.4028/www.scientific.net/amm.556-562.4998 2014 Trans Tech Publications, Switzerland Research on the
More informationTKT-2431 SoC design. Introduction to exercises. SoC design / September 10
TKT-2431 SoC design Introduction to exercises Assistants: Exercises and the project work Juha Arvio juha.arvio@tut.fi, Otto Esko otto.esko@tut.fi In the project work, a simplified H.263 video encoder is
More informationDigital Systems Design. System on a Programmable Chip
Digital Systems Design Introduction to System on a Programmable Chip Dr. D. J. Jackson Lecture 11-1 System on a Programmable Chip Generally involves utilization of a large FPGA Large number of logic elements
More informationDesign And Implementation Of USART IP Soft Core Based On DMA Mode
Design And Implementation Of USART IP Soft Core Based On DMA Mode Peddaraju Allam 1 1 M.Tech Student, Dept of ECE, Geethanjali College of Engineering & Technology, Hyderabad, A.P, India. Abstract A Universal
More informationDesign of Entropy Decoding Module in Dual-Mode Video Decoding Chip for H. 264 and AVS Based on SOPC Hong-Min Yang, Zhen-Lei Zhang, and Hai-Yan Kong
Design of Entropy Decoding Module in Dual-Mode Video Decoding Chip for H. 264 and AVS Based on SOPC Hong-Min Yang, Zhen-Lei Zhang, and Hai-Yan Kong School of Information Science and Engineering, Shandong
More informationCover TBD. intel Quartus prime Design software
Cover TBD intel Quartus prime Design software Fastest Path to Your Design The Intel Quartus Prime software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a
More informationNios II Soft Core-Based Double-Layer Digital Watermark Technology Implementation System
Nios II Soft Core-Based Double-Layer Digital Watermark Technology Implementation Third Prize Nios II Soft Core-Based Double-Layer Digital Watermark Technology Implementation System Institution: Participants:
More information3-D Accelerator on Chip
3-D Accelerator on Chip Third Prize 3-D Accelerator on Chip Institution: Participants: Instructor: Donga & Pusan University Young-Hee Won, Jin-Sung Park, Woo-Sung Moon Sam-Hak Jin Design Introduction Recently,
More informationMultimedia Decoder Using the Nios II Processor
Multimedia Decoder Using the Nios II Processor Third Prize Multimedia Decoder Using the Nios II Processor Institution: Participants: Instructor: Indian Institute of Science Mythri Alle, Naresh K. V., Svatantra
More informationECE332, Week 2, Lecture 3. September 5, 2007
ECE332, Week 2, Lecture 3 September 5, 2007 1 Topics Introduction to embedded system Design metrics Definitions of general-purpose, single-purpose, and application-specific processors Introduction to Nios
More informationECE332, Week 2, Lecture 3
ECE332, Week 2, Lecture 3 September 5, 2007 1 Topics Introduction to embedded system Design metrics Definitions of general-purpose, single-purpose, and application-specific processors Introduction to Nios
More informationESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer)
ESE Back End 2.0 D. Gajski, S. Abdi (with contributions from H. Cho, D. Shin, A. Gerstlauer) Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu 1 Technology advantages
More informationFPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
More informationDesign and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA
Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA Maheswari Murali * and Seetharaman Gopalakrishnan # * Assistant professor, J. J. College of Engineering and Technology,
More informationIntroduction to the Altera SOPC Builder Using Verilog Design
Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor
More informationThe Application of Programmable Controller to Chip Design. Shihong Lan 1, Jian Zhang 2
Applied Mechanics and Materials Online: 2013-01-11 ISSN: 1662-7482, Vol. 273, pp 722-725 doi:10.4028/www.scientific.net/amm.273.722 2013 Trans Tech Publications, Switzerland The Application of Programmable
More informationGraduate Institute of Electronics Engineering, NTU Advanced VLSI SOPC design flow
Advanced VLSI SOPC design flow Advisor: Speaker: ACCESS IC LAB What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 2 What s SOC? Definition of SOC Advantage
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based
More informationCover TBD. intel Quartus prime Design software
Cover TBD intel Quartus prime Design software Fastest Path to Your Design The Intel Quartus Prime software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a
More informationDesign and Realization of FPGA Based Phonetic Intelligent Home System Wei Zhuo
4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) Design and Realization of FPGA Based Phonetic Intelligent Home System Wei Zhuo Vocational Education
More informationDesign and Implementation of CNC Operator Panel Control Functions Based on CPLD. Huaqun Zhan, Bin Xu
Advanced Materials Research Online: 2013-07-31 ISSN: 1662-8985, Vol. 722, pp 428-432 doi:10.4028/www.scientific.net/amr.722.428 2013 Trans Tech Publications, Switzerland Design and Implementation of CNC
More informationIntroduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction
Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the
More informationDesigning Embedded Processors in FPGAs
Designing Embedded Processors in FPGAs 2002 Agenda Industrial Control Systems Concept Implementation Summary & Conclusions Industrial Control Systems Typically Low Volume Many Variations Required High
More informationCHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8
CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram
More informationOpen Access Research on FPGA Prototype Simulation in MP3 Audio Decoder Design
Send Orders for Reprints to reprints@benthamscience.ae The Open Automation and Control Systems Journal, 5, 7, 45-44 45 Open Access Research on FPGA Prototype Simulation in MP3 Audio Decoder Design Geng
More informationChapter 2 Getting Hands on Altera Quartus II Software
Chapter 2 Getting Hands on Altera Quartus II Software Contents 2.1 Installation of Software... 20 2.2 Setting Up of License... 21 2.3 Creation of First Embedded System Project... 22 2.4 Project Building
More informationLaboratory Exercise 5
Laboratory Exercise 5 Bus Communication The purpose of this exercise is to learn how to communicate using a bus. In the designs generated by using Altera s SOPC Builder, the Nios II processor connects
More informationThe RTP Encapsulation based on Frame Type Method for AVS Video
Applied Mechanics and Materials Online: 2012-12-27 ISSN: 1662-7482, Vols. 263-266, pp 1803-1808 doi:10.4028/www.scientific.net/amm.263-266.1803 2013 Trans Tech Publications, Switzerland The RTP Encapsulation
More informationEfficient VLSI Huffman encoder implementation and its application in high rate serial data encoding
LETTER IEICE Electronics Express, Vol.14, No.21, 1 11 Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding Rongshan Wei a) and Xingang Zhang College of Physics
More informationImplementation of FPGA Based MP3 player using Invers Modified Discrete Cosine Transform
Implementation of FPGA Based MP3 player using Invers Modified Discrete Cosine Transform Mr. Sanket Shinde Universal college of engineering, Kaman Email-Id:sanketsanket01@gmail.com Mr. Vinay Vyas Universal
More informationIntroduction to the Qsys System Integration Tool
Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will
More informationDRA AUDIO CODING STANDARD
Applied Mechanics and Materials Online: 2013-06-27 ISSN: 1662-7482, Vol. 330, pp 981-984 doi:10.4028/www.scientific.net/amm.330.981 2013 Trans Tech Publications, Switzerland DRA AUDIO CODING STANDARD Wenhua
More informationFPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE Standard
FPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE 754-2008 Standard M. Shyamsi, M. I. Ibrahimy, S. M. A. Motakabber and M. R. Ahsan Dept. of Electrical and Computer Engineering
More informationDesign of the Software for Wirelessly Intercepting Voices
Advanced Materials Research Online: 2014-05-23 ISSN: 1662-8985, Vols. 926-930, pp 2470-2473 doi:10.4028/www.scientific.net/amr.926-930.2470 2014 Trans Tech Publications, Switzerland Design of the Software
More informationDESIGN OF STANDARD AND CUSTOM PERIPHERAL USING NIOS II PROCESSOR
DESIGN OF STANDARD AND CUSTOM PERIPHERAL USING NIOS II PROCESSOR 1 K.J.VARALAKSHMI, 2 M.KAMARAJU 1 Student, 2 Professor and HOD E-mail: Kjvaralakshmi @gmail.com, prof.mkr @gmail.com Abstract- Today, Field
More informationCustomizing dynamic libraries of Qt based on the embedded Linux Li Yang 1,a, Wang Yunliang 2,b
Applied Mechanics and Materials Submitted: 2014-11-12 ISSN: 1662-7482, Vol. 740, pp 782-785 Accepted: 2014-12-02 doi:10.4028/www.scientific.net/amm.740.782 Online: 2015-03-09 2015 Trans Tech Publications,
More informationDesign and Implementation of Rijindael s Encryption and Decryption Algorithm using NIOS- II Processor
Design and Implementation of Rijindael s Encryption and Decryption Algorithm using NIOS- II Processor Monika U. Jaiswal 1, Nilesh A. Mohota 2 1 Student, Electronics Department, JDCOEM, Nagpur, India 2
More informationAnalysis of Resource Utilization in FPGA Implementation of an Embedded System Using Soft Core Processor.
Analysis of Resource Utilization in FPGA Implementation of an Embedded Using Soft Core Processor. M.U. Kharat, Ph.D. 1 and V.S. Rahangadale, M.E. 2 1 Department of Information Technology, G.H. Raisoni
More informationA SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN
A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN Xiaoying Li 1 Fuming Sun 2 Enhua Wu 1, 3 1 University of Macau, Macao, China 2 University of Science and Technology Beijing, Beijing, China
More informationUniversity of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA
University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring 2007 Lab 1: Using Nios 2 processor for code execution on FPGA Objectives: After the completion of this lab: 1. You will understand
More informationGraphics Controller Core
Core - with 2D acceleration functionalities Product specification Prevas AB PO Box 4 (Legeringsgatan 18) SE-721 03 Västerås, Sweden Phone: Fax: Email: URL: Features +46 21 360 19 00 +46 21 360 19 29 johan.ohlsson@prevas.se
More informationThe University of Reduced Instruction Set Computer (MARC)
The University of Reduced Instruction Set Computer (MARC) Abstract We present our design of a VHDL-based, RISC processor instantiated on an FPGA for use in undergraduate electrical engineering courses
More informationDesigning with Nios II Processor for Hardware Engineers
Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under
More informationDE2 Board & Quartus II Software
January 23, 2015 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours Email SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM contre47@nevada.unlv.edu Syllabus
More informationCreating projects with Nios II for Altera De2i-150. By Trace Stewart CPE 409
Creating projects with Nios II for Altera De2i-150 By Trace Stewart CPE 409 CONTENTS Chapter 1 Hardware Design... 1 1.1 Required Features... 1 1.2 Creation of Hardware Design... 1 Chapter 2 Programming
More informationA Digital Menu System Based on the Cloud client Technology Lin Dong 1, a, Weibo Li 1, b, Ping He 2,c,Jia Liu 1,d
Applied Mechanics and Materials Online: 2012-11-29 ISSN: 1662-7482, Vol. 235, pp 389-393 doi:10.4028/www.scientific.net/amm.235.389 2012 Trans Tech Publications, Switzerland A Digital Menu System Based
More informationIMPLEMENTATION OF TIME EFFICIENT SYSTEM FOR MEDIAN FILTER USING NIOS II PROCESSOR
IMPLEMENTATION OF TIME EFFICIENT SYSTEM FOR MEDIAN FILTER USING NIOS II PROCESSOR Tanushree Selokar 1 and Narendra G. Bawane 2 1, 2 Department of Electronics Engineering, R.T.M.N. University, Nagpur, India
More informationSimulating Nios II Embedded Processor Designs
Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance
More information9. Building Memory Subsystems Using SOPC Builder
9. Building Memory Subsystems Using SOPC Builder QII54006-6.0.0 Introduction Most systems generated with SOPC Builder require memory. For example, embedded processor systems require memory for software
More informationKeywords: Interactive electronic technical manuals; GJB6600; XML markup language; Automatic control equipment
Applied Mechanics and Materials Submitted: 2014-06-11 ISSN: 1662-7482, Vols. 602-605, pp 1165-1168 Accepted: 2014-06-11 doi:10.4028/www.scientific.net/amm.602-605.1165 Online: 2014-08-11 2014 Trans Tech
More informationPractical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937
More informationThe Design of CAN Bus Communication System Based on MCP2515 and S3C2440 Jinmei Liu, Junhong Wang, Donghui Sun
Advanced Materials Research Online: 2014-05-21 ISSN: 1662-8985, Vol. 933, pp 516-520 doi:10.4028/www.scientific.net/amr.933.516 2014 Trans Tech Publications, Switzerland The Design of CAN Bus Communication
More information«Real Time Embedded systems» Multi Masters Systems
«Real Time Embedded systems» Multi Masters Systems rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Chargé de cours rene.beuchat@hesge.ch LSN/hepia Prof. HES 1 Multi Master on Chip On a System On Chip, Master can
More informationDesign and Implementation of Effective Architecture for DCT with Reduced Multipliers
Design and Implementation of Effective Architecture for DCT with Reduced Multipliers Susmitha. Remmanapudi & Panguluri Sindhura Dept. of Electronics and Communications Engineering, SVECW Bhimavaram, Andhra
More information4K Format Conversion Reference Design
4K Format Conversion Reference Design AN-646 Application Note This application note describes a 4K format conversion reference design. 4K resolution is the next major enhancement in video because of the
More informationEarly Models in Silicon with SystemC synthesis
Early Models in Silicon with SystemC synthesis Agility Compiler summary C-based design & synthesis for SystemC Pure, standard compliant SystemC/ C++ Most widely used C-synthesis technology Structural SystemC
More informationEmbedded Systems. "System On Programmable Chip" NIOS II Avalon Bus. René Beuchat. Laboratoire d'architecture des Processeurs.
Embedded Systems "System On Programmable Chip" NIOS II Avalon Bus René Beuchat Laboratoire d'architecture des Processeurs rene.beuchat@epfl.ch 3 Embedded system on Altera FPGA Goal : To understand the
More informationLaboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication
Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Introduction All processors offer some form of instructions to add, subtract, and manipulate data.
More informationApplied mechanics and applied technology in fuel injection pump bench. Rotational speed measurement system design based on CPLD
Advanced Materials Research Online: 2014-03-24 ISSN: 1662-8985, Vol. 910, pp 316-319 doi:10.4028/www.scientific.net/amr.910.316 2014 Trans Tech Publications, Switzerland Applied mechanics and applied technology
More informationTHE DESIGN OF HIGH PERFORMANCE BARREL INTEGER ADDER S.VenuGopal* 1, J. Mahesh 2
e-issn 2277-2685, p-issn 2320-976 IJESR/September 2014/ Vol-4/Issue-9/738-743 S. VenuGopal et. al./ International Journal of Engineering & Science Research ABSTRACT THE DESIGN OF HIGH PERFORMANCE BARREL
More informationEN2911X: Reconfigurable Computing Lecture 01: Introduction
EN2911X: Reconfigurable Computing Lecture 01: Introduction Prof. Sherief Reda Division of Engineering, Brown University Fall 2009 Methods for executing computations Hardware (Application Specific Integrated
More informationTKT-2431 SoC design. Introduction to exercises
TKT-2431 SoC design Introduction to exercises Assistants: Exercises Jussi Raasakka jussi.raasakka@tut.fi Otto Esko otto.esko@tut.fi In the project work, a simplified H.263 video encoder is implemented
More informationSOCS BASED OPENRISC AND MICROBLAZE SOFT PROCESSORS COMPARISON STUDY CASES: AUDIO IMPLEMENTATION AND NETWORK IMPLEMENTATION BASED SOCS
SOCS BASED OPENRISC AND MICROBLAZE SOFT PROCESSORS COMPARISON STUDY CASES: AUDIO IMPLEMENTATION AND NETWORK IMPLEMENTATION BASED SOCS Faroudja Abid, Nouma Izeboudjen, Dalila Lazib, Mohamed Bakiri, Sabrina
More informationSISTEMI EMBEDDED. Embedded Systems SOPC Design Flow. Federico Baronti Last version:
SISTEMI EMBEDDED Embedded Systems SOPC Design Flow Federico Baronti Last version: 20160229 Definition(s) of Embedded Systems Systems with embedded processors Hamblen, Hall, Furman, Rapid Prototyping Of
More informationWhite Paper. The advantages of using a combination of DSP s and FPGA s. Version: 1.0. Author: Louis N. Bélanger. Date: May, 2004.
White Paper The advantages of using a combination of DSP s and FPGA s Version: 1.0 Author: Louis N. Bélanger Date: May, 2004 Lyrtech Inc The advantages of using a combination of DSP s and FPGA s DSP and
More informationHardware Software Co-design and SoC. Neeraj Goel IIT Delhi
Hardware Software Co-design and SoC Neeraj Goel IIT Delhi Introduction What is hardware software co-design Some part of application in hardware and some part in software Mpeg2 decoder example Prediction
More informationECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego
Advanced Digital Winter, 2009 ECE Department UC San Diego dey@ece.ucsd.edu http://esdat.ucsd.edu Winter 2009 Advanced Digital Objective: of a hardware-software embedded system using advanced design methodologies
More informationSOPC-Based Cooperative Awareness Nodes in Smart Multimedia Sensor Networks
2012 7th International ICST Conference on Communications and Networking in China (CHINACOM) SOPC-Based Cooperative Awareness Nodes in Smart Multimedia Sensor Networks Yi Zhou 1, Huiping Li 2, Chunlin Wan
More informationOptical Storage Technology. MPEG Data Compression
Optical Storage Technology MPEG Data Compression MPEG-1 1 Audio Standard Moving Pictures Expert Group (MPEG) was formed in 1988 to devise compression techniques for audio and video. It first devised the
More informationDesign of Embedded Hardware and Firmware
Design of Embedded Hardware and Firmware Introduction on "System On Programmable Chip" NIOS II Avalon Bus - DMA Andres Upegui Laboratoire de Systèmes Numériques hepia/hes-so Geneva, Switzerland Embedded
More informationImplementing Video and Image Processing Designs Using FPGAs. Click to add subtitle
Implementing Video and Image Processing Designs Using FPGAs Click to add subtitle Agenda Key trends in video and image processing Video and Image Processing Suite Model-based design for video processing
More informationPark Sung Chul. AE MentorGraphics Korea
PGA Design rom Concept to Silicon Park Sung Chul AE MentorGraphics Korea The Challenge of Complex Chip Design ASIC Complex Chip Design ASIC or FPGA? N FPGA Design FPGA Embedded Core? Y FPSoC Design Considerations
More informationDKAN0011A Setting Up a Nios II System with SDRAM on the DE2
DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera
More informationQUARTUS II Altera Corporation
QUARTUS II Quartus II Design Flow Design Entry Timing Constraints Synthesis Placement and Routing Timing, Area, Power Optimization Timing and Power Analyzer Optimized Design 2 Can I still use a Processor?
More informationPerceptual Coding. Lossless vs. lossy compression Perceptual models Selecting info to eliminate Quantization and entropy encoding
Perceptual Coding Lossless vs. lossy compression Perceptual models Selecting info to eliminate Quantization and entropy encoding Part II wrap up 6.082 Fall 2006 Perceptual Coding, Slide 1 Lossless vs.
More informationFPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
More informationLaboratory 4 Design a Muti-bit Counter and Programming a FPGA
Laboratory 4 Design a Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design entry included
More informationImplementation of A Optimized Systolic Array Architecture for FSBMA using FPGA for Real-time Applications
46 IJCSNS International Journal of Computer Science and Network Security, VOL.8 No.3, March 2008 Implementation of A Optimized Systolic Array Architecture for FSBMA using FPGA for Real-time Applications
More informationAdvanced course on Embedded Systems design using FPGA
Advanced course on Embedded Systems design using FPGA Subramaniam Ganesan, Phares A. Noel, Ashok Prajapati Oakland University, ganesan@oakland.edu, panoel@oakland.edu, akprajap@oakland.edu Abstract-As
More informationMulti-Functional Digital Albums Based on the Nios II Processor
Multi-Functional Digital Albums Based on the Nios II Processor Third Prize Multi-Functional Digital Albums Based on the Nios II Processor Institution: Participants: Instructor: Information Science Institute,
More informationREAL TIME DIGITAL SIGNAL PROCESSING
REAL TIME DIGITAL SIGNAL PROCESSING UTN - FRBA 2011 www.electron.frba.utn.edu.ar/dplab Introduction Why Digital? A brief comparison with analog. Advantages Flexibility. Easily modifiable and upgradeable.
More informationNIOS II Instantiating the Off-chip Trace Logic
NIOS II Instantiating the Off-chip Trace Logic TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... NIOS... NIOS II Application
More informationConstruction of the Library Management System Based on Data Warehouse and OLAP Maoli Xu 1, a, Xiuying Li 2,b
Applied Mechanics and Materials Online: 2013-08-30 ISSN: 1662-7482, Vols. 380-384, pp 4796-4799 doi:10.4028/www.scientific.net/amm.380-384.4796 2013 Trans Tech Publications, Switzerland Construction of
More informationResearch Of Data Model In Engineering Flight Simulation Platform Based On Meta-Data Liu Jinxin 1,a, Xu Hong 1,b, Shen Weiqun 2,c
Applied Mechanics and Materials Online: 2013-06-13 ISSN: 1662-7482, Vols. 325-326, pp 1750-1753 doi:10.4028/www.scientific.net/amm.325-326.1750 2013 Trans Tech Publications, Switzerland Research Of Data
More informationIntroduction to VHDL Design on Quartus II and DE2 Board
ECP3116 Digital Computer Design Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE2 Board Objective To learn how to create projects using Quartus II, design circuits and
More informationDesign and Verification Point-to-Point Architecture of WISHBONE Bus for System-on-Chip
International Journal of Emerging Engineering Research and Technology Volume 2, Issue 2, May 2014, PP 155-159 Design and Verification Point-to-Point Architecture of WISHBONE Bus for System-on-Chip Chandrala
More informationConstructing an University Scientific Research Management Information System of NET Platform Jianhua Xie 1, a, Jian-hua Xiao 2, b
Applied Mechanics and Materials Online: 2013-12-04 ISSN: 1662-7482, Vol. 441, pp 984-988 doi:10.4028/www.scientific.net/amm.441.984 2014 Trans Tech Publications, Switzerland Constructing an University
More informationIntroduction of the Research Based on FPGA at NICS
Introduction of the Research Based on FPGA at NICS Rong Luo Nano Integrated Circuits and Systems Lab, Department of Electronic Engineering, Tsinghua University Beijing, 100084, China 1 luorong@tsinghua.edu.cn
More information5: Music Compression. Music Coding. Mark Handley
5: Music Compression Mark Handley Music Coding LPC-based codecs model the sound source to achieve good compression. Works well for voice. Terrible for music. What if you can t model the source? Model the
More informationLayered Decoding With A Early Stopping Criterion For LDPC Codes
2012 2 nd International Conference on Information Communication and Management (ICICM 2012) IPCSIT vol. 55 (2012) (2012) IACSIT Press, Singapore DOI: 10.7763/IPCSIT.2012.V55.14 ayered Decoding With A Early
More informationDesign For High Performance Flexray Protocol For Fpga Based System
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) e-issn: 2319 4200, p-issn No. : 2319 4197 PP 83-88 www.iosrjournals.org Design For High Performance Flexray Protocol For Fpga Based System E. Singaravelan
More informationAn Infrastructural IP for Interactive MPEG-4 SoC Functional Verification
International Journal on Electrical Engineering and Informatics - Volume 1, Number 2, 2009 An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification Trio Adiono 1, Hans G. Kerkhoff 2 & Hiroaki
More information